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In-Reply-To: <35539292-53a8-292d-2f5d-f65ad02a36bb@suse.com>
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 1 Dec 2022 08:43:08 -0800
Message-ID: <CAMe9rOraH0v_oE251mP4JgifWuBWwUTr-NRv7DJ4e0--uqpFOQ@mail.gmail.com>
Subject: Re: [PATCH] x86: simplify and slightly correct XCHG vs NOP checking
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
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On Thu, Dec 1, 2022 at 1:11 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> For one, because of CheckRegSize, there's no need to check the size of
> both (register) operands. And then in process_suffix() check opcode
> space rather than the (potentially ambiguous) extension opcode.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -6686,8 +6686,7 @@ match_template (char mnem_suffix)
>               && t->opcode_modifier.opcodespace == SPACE_BASE
>               && i.types[0].bitfield.instance == Accum
>               && i.types[0].bitfield.dword
> -             && i.types[1].bitfield.instance == Accum
> -             && i.types[1].bitfield.dword)
> +             && i.types[1].bitfield.instance == Accum)
>             continue;
>           /* xrelease mov %eax, <disp> is another special case. It must not
>              match the accumulator-only encoding of mov.  */
> @@ -7408,11 +7407,10 @@ process_suffix (void)
>              need rex64. */
>           && ! (i.operands == 2
>                 && i.tm.base_opcode == 0x90
> -               && i.tm.extension_opcode == None
> +               && i.tm.opcode_modifier.opcodespace == SPACE_BASE
>                 && i.types[0].bitfield.instance == Accum
>                 && i.types[0].bitfield.qword
> -               && i.types[1].bitfield.instance == Accum
> -               && i.types[1].bitfield.qword))
> +               && i.types[1].bitfield.instance == Accum))
>         i.rex |= REX_W;
>
>        break;

OK.

Thanks.

-- 
H.J.