From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 2/6] x86-64: Intel64 adjustments for conditional jumps
Date: Fri, 06 Mar 2020 14:40:00 -0000 [thread overview]
Message-ID: <CAMe9rOraQBhZfWNJS2cmZ57wjcjQ2Fd0h2OPkaO6bguU0_qi0g@mail.gmail.com> (raw)
In-Reply-To: <da820d1f-252e-0984-04ad-fc4cf135f12d@suse.com>
On Fri, Mar 6, 2020 at 12:12 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Just like for unconditional direct JMP, AMD and Intel differ in their
> handling. Mirror JMP handling to Jcc.
>
> gas/
> 2020-03-XX Jan Beulich <jbeulich@suse.com>
>
> * testsuite/gas/i386/x86-64-branch-2.s,
> testsuite/gas/i386/x86-64-branch-3.s: Add Jcc cases.
> * testsuite/gas/i386/ilp32/x86-64-branch.d,
> testsuite/gas/i386/opcode-suffix.d,
> testsuite/gas/i386/x86-64-branch-2.d,
> testsuite/gas/i386/x86-64-branch-3.d,
> testsuite/gas/i386/x86-64-branch.d: Adjust expectations.
>
> opcodes/
> 2020-03-XX Jan Beulich <jbeulich@suse.com>
>
> * i386-dis.c (safe-ctype.h): Include.
> (X86_64_0F8x): New enumerator.
> (dis386): Extend comment ahead of it.
> (dis386_twobyte): Vector Jcc to X86_64_0F8x.
> (condition_code): New.
> (x86_64_table): Add X86_64_0F8x entry.
> (print_insn): Set condition_code. Move advancing of codep after
> it.
> (putop): Handle two-char escape case for 'C'. Handle 'C' prefix
> case for 'P' and '@'.
> * i386-opc.tbl (j<cc>): Split into AMD64 and Intel64 variants.
> * i386-tbl.h: Re-generate.
> ---
> I wonder if the suffix handling done here wouldn't also be the more
> suitable one for JMP and CALL. In particular the 'q' suffix printed
> unconditionally in 64-bit mode is more of a problem than helpful imo.
>
> --- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
> +++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
> @@ -22,7 +22,7 @@ Disassembly of section .text:
> [ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c
> [ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq 0x2a 26: R_X86_64_PLT32 foo-0x4
> [ ]*[a-f0-9]+: 66 e9 00 00 00 00 data16 jmpq 0x30 2c: R_X86_64_PLT32 foo-0x4
> -[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb 0x37 33: R_X86_64_PLT32 foo-0x4
> +[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jbq 0x37 33: R_X86_64_PLT32 foo-0x4
> [ ]*[a-f0-9]+: 66 c3 data16 retq *
> [ ]*[a-f0-9]+: 66 c2 08 00 data16 retq \$0x8
> [ ]*[a-f0-9]+: ff d0 callq \*%rax
I think it is a very bad idea to add suffix to jcc.
--
H.J.
next prev parent reply other threads:[~2020-03-06 14:40 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 8:09 [PATCH 0/6] x86: introduce "templated" insn templates Jan Beulich
2020-03-06 8:11 ` [PATCH 1/6] x86: allow opcode templates to be templated Jan Beulich
2020-03-06 14:42 ` H.J. Lu
2020-03-06 14:51 ` Jan Beulich
2020-03-06 15:38 ` H.J. Lu
2020-03-09 9:19 ` Jan Beulich
2020-03-09 12:15 ` H.J. Lu
2020-03-06 8:12 ` [PATCH 2/6] x86-64: Intel64 adjustments for conditional jumps Jan Beulich
2020-03-06 14:40 ` H.J. Lu [this message]
2020-03-06 14:54 ` Jan Beulich
2020-03-06 15:35 ` H.J. Lu
2020-03-09 7:11 ` Jan Beulich
2020-03-09 12:13 ` H.J. Lu
2020-03-11 8:59 ` Jan Beulich
2020-03-11 10:32 ` H.J. Lu
2020-04-24 6:36 ` Jan Beulich
2020-04-24 12:58 ` H.J. Lu
2020-03-06 8:12 ` [PATCH 3/6] x86: use template for SSE floating point comparison insns Jan Beulich
2020-03-06 14:43 ` H.J. Lu
2020-03-06 8:13 ` [PATCH 4/6] x86: use template for AVX/AVX512 " Jan Beulich
2020-03-06 14:45 ` H.J. Lu
2020-03-06 14:57 ` Jan Beulich
2020-03-06 15:32 ` H.J. Lu
2020-03-06 8:13 ` [PATCH 5/6] x86: use template for XOP integer comparison, shift, and rotate insns Jan Beulich
2020-03-06 14:46 ` H.J. Lu
2020-03-06 8:14 ` [PATCH 6/6] x86: use template for AVX512 integer comparison insns Jan Beulich
2020-03-06 14:46 ` H.J. Lu
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