From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112f.google.com (mail-yw1-x112f.google.com [IPv6:2607:f8b0:4864:20::112f]) by sourceware.org (Postfix) with ESMTPS id 34C7B3858D35 for ; Wed, 30 Aug 2023 15:25:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 34C7B3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-5925e580e87so61553357b3.1 for ; Wed, 30 Aug 2023 08:25:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693409137; x=1694013937; darn=sourceware.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=c+6nCAzHWI9LO4xbj8NMF0NOlSSlAzeWk3+waGb2j5o=; b=pTG52yoGgOY/rKONgu3/FDLc46mC94Bsf/gMurbdFZ56yks0ATarBqhX5NzgvDC8sE Ps6nWu6C0gYlum80Zmq61KB09UUE8LlBGvESj0EA2Wy+tMQDG6hYuk6c+QlkFgvV3lHx MetkLxwGJlc8BMHS0K6bPG8nT/nwG3yLJgyY13fOBv0HweNMm9EXMtJFHV2MIUR+C1ol Cla5FDDa5H7eb49tWTy2hL5zzFKt2m/mStgSeCgBBDiYa+BjgamLDbq4DmgYzHZSCs4b eDX5URV/qzA2OgEXocrVobqn0Ol36FLZoVGBBpknKzC7mZcAjqb2RVqgksjuxyNvGR/M tYtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693409137; x=1694013937; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c+6nCAzHWI9LO4xbj8NMF0NOlSSlAzeWk3+waGb2j5o=; b=Wt1EShc97Yh6vVJ8r/Zar0pGEwogOxYTDU6JgrKIaWqfgWoriiB5suBXkb6cjfv7FX wldhesCqh1REKjzVTjeTc1qGbMffVBK8Sylo4zy97krlNnV0a4Ikelxre1b3Igkolam4 bALJtLbmiJYr83WBTLu0PpsB4LBJOScVPDs1MJOGCuRJRO/vkt5C90wmLe2L3wpPYG3o +InV2SGhHMp9lsK83xi7IrPxQntWpMDfulaw7CEsLBIKtdB+HY4NmHxz+BMw+wb9XYBM 1Q3KlSZXWoWjgsc+NZo/2iMWBKrrd3RpMhvJKKK9Vq2BKEhPvhMASNdKuJiu0aq3Wv3e 8UOw== X-Gm-Message-State: AOJu0YwCBGSyRfiJMMctf1KZFb/kXda0Pu4HIsl4GE5RPWoR7YD72QRE KgU4TaNgvtqkLJMh1ICByU3a0zCcy1Ji440H8C0= X-Google-Smtp-Source: AGHT+IGMpe0790mw4JuBBw9+P5HXJv7cNABE7qyZvySA8mHjmduSmAD2z/Emay//B4RNStA3KSmf4dtuBZCIM7ujVxI= X-Received: by 2002:a05:690c:f12:b0:595:9a29:346a with SMTP id dc18-20020a05690c0f1200b005959a29346amr2143211ywb.50.1693409137392; Wed, 30 Aug 2023 08:25:37 -0700 (PDT) MIME-Version: 1.0 References: <6f819651-36c0-1c69-8224-fe21f0f96a3f@suse.com> <990c83c3-0776-efdd-e162-5c367f4ebdc2@suse.com> <1b1b6e37-9484-95d8-d63d-c586a064729f@suse.com> In-Reply-To: <1b1b6e37-9484-95d8-d63d-c586a064729f@suse.com> From: "H.J. Lu" Date: Wed, 30 Aug 2023 08:25:01 -0700 Message-ID: Subject: Re: [PATCH 5/5] x86: support AVX10.1 vector size restrictions To: Jan Beulich Cc: Binutils , "Jiang, Haochen" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3015.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Aug 30, 2023 at 12:57=E2=80=AFAM Jan Beulich wr= ote: > > On 29.08.2023 18:26, H.J. Lu wrote: > > On Fri, Aug 25, 2023 at 5:48=E2=80=AFAM Jan Beulich = wrote: > >> @@ -1673,6 +1680,12 @@ an unconditional jump to the target. > >> > >> Note that the sub-architecture specifiers (starting with a dot) can b= e prefixed > >> with @code{no} to revoke the respective (and any dependent) functiona= lity. > >> +Note further that @samp{.avx10.} can be suffixed with a vector len= gth > >> +restriction (@samp{/256} or @samp{/128}, with @samp{/512} simply rest= oring the > >> +default). Despite these otherwise being "enabling" specifiers, using= these > >> +suffixes will disable all insns with wider vector or mask register op= erands. > >> +On SVR4-derived platforms, the separator character @samp{/} can be re= placed by > >> +@samp{:}. > >> > >> Following the CPU architecture (but not a sub-architecture, which are= those > >> starting with a dot), you may specify @samp{jumps} or @samp{nojumps} = to > > > > Although CPUID bits in AVX10 spec may leave an impression that 128-bit, > > 256-bit and 512-bit vectors may be enabled independently. But it also = says > > > > A =E2=80=9Cconverged=E2=80=9D version of Intel AVX10 with maximum vecto= r lengths of 256 > > bits and 32-bit opmask registers will be supported across all Intel pro= cessors, > > while 512-bit vector registers and 64-bit opmasks will continue to be s= upported > > on some P-core processors. > > > > Adding avx10.1/128 isn't necessary. > > I agree it isn't necessary, but as expressed before I view it as desirabl= e. > Apart from the sentence you quoted the spec later also says "There are > currently no plans to support an Intel AVX10/128 implementation." For my > choice of also supporting the 128-bit restriction I'd like to put emphasi= s > on "currently". I think I said before that emulation environments (qemu, > sde to name just two well-known examples) are free to implement such > further restricted ISAs without then becoming out-of-spec. > > Plus supporting this mode right away has made me make certain adjustments > in what I'd call more clean a way, which I view as desirable as well. > Since AVX10 spec doesn't specify if mask registers should be limited to 16 bits for AVX10/128, doing it in assembler is premature. --=20 H.J.