From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 8E611385B804; Wed, 11 May 2022 17:59:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8E611385B804 Received: by mail-ej1-x62c.google.com with SMTP id l18so5597944ejc.7; Wed, 11 May 2022 10:59:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=6sMjg0Ze3sdnFKqNxVBLtlyLzRjVp/Dl2lRP7fjcY1I=; b=NtgtyqXTh9BOJi7kJr36RrK4Y6DfjwHVm2kjc0+lMSHa2KVJjwXXKNKA1ltTfjjH/c AoRmFZkvyyrPkcYCcFqWVsAf64lbeqXfJD6yJdMqPWXXLifya+wuwZlN8dwdMBQVTCEt tZ4lo9/81QVIeSatwFtzytlb8O/tlkACq/nsoufoJbbVr2cMcoZ4YSEwxnDzATAHJcHC FguAKbQK8CorNh+/ODEllBuJhdBy9aR3Kd4ikqSDiR3ZSrOYQrakju/K/5rci2LUBs+K 1e+8n9HNPkSgbXVo2elF8TWLqXXZGCn1ZABzjg5z6WuD/r1Sx9Q3Qzh4BV+ZwsVE7OEz 6/eg== X-Gm-Message-State: AOAM532wvCZur73KEXQb0WgI0AbOC1jS8+8cqWbnEeCTVFz6NbFk0DV/ R6FG6Z8RHaeZAducAlKP0aqmESdS8oYOkqcTk1i2TgbtMHM= X-Google-Smtp-Source: ABdhPJxV+ad/mdQB/0e41aRkH6xnKxIRM1PM56MlsfuoHKCps3TWDqEO/0z3m9YP2pDZQ2Qwn6JFiS1rX8BmydURdMM= X-Received: by 2002:a17:906:19c3:b0:6ec:c7b:ed28 with SMTP id h3-20020a17090619c300b006ec0c7bed28mr25520837ejd.612.1652291994875; Wed, 11 May 2022 10:59:54 -0700 (PDT) MIME-Version: 1.0 From: Dmitry Selyutin Date: Wed, 11 May 2022 20:59:19 +0300 Message-ID: Subject: [PATCH 1/2] ppc: extend opindex to 16 bits To: binutils@sourceware.org Cc: gdb-patches@sourceware.org, Alan Modra , Luke Kenneth Casson Leighton Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 May 2022 17:59:57 -0000 With the upcoming SVP64 extension[0] to PowerPC architecture, it became evident that PowerPC operand indices no longer fit 8 bits. This patch switches the underlying type to uint16_t, also introducing a special typedef so that any future extension goes even smoother. [0] https://libre-soc.org --- gas/config/tc-ppc.c | 11 ++++++----- include/opcode/ppc.h | 5 ++++- opcodes/ppc-dis.c | 12 ++++++------ 3 files changed, 16 insertions(+), 12 deletions(-) diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 72128af501..12a4314c94 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1553,7 +1553,7 @@ ppc_target_format (void) static bool insn_validate (const struct powerpc_opcode *op) { - const unsigned char *o; + const ppc_opindex_t *o; uint64_t omask = op->mask; /* The mask had better not trim off opcode bits. */ @@ -1634,8 +1634,9 @@ ppc_setup_opcodes (void) unsigned int i; /* An index into powerpc_operands is stored in struct fix - fx_pcrel_adjust which is 8 bits wide. */ - gas_assert (num_powerpc_operands < 256); + fx_pcrel_adjust which is 16 bits wide. + Also, this field is signed due to historical reasons. */ + gas_assert (num_powerpc_operands < PPC_OPINDEX_MAX); /* Check operand masks. Code here and in the disassembler assumes all the 1's in the mask are contiguous. */ @@ -3251,7 +3252,7 @@ md_assemble (char *str) char *s; const struct powerpc_opcode *opcode; uint64_t insn; - const unsigned char *opindex_ptr; + const ppc_opindex_t *opindex_ptr; int need_paren; int next_opindex; struct ppc_fixup fixups[MAX_INSN_FIXUPS]; @@ -3348,7 +3349,7 @@ md_assemble (char *str) { if (num_optional_operands == 0) { - const unsigned char *optr; + const ppc_opindex_t *optr; int total = 0; int provided = 0; int omitted; diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a9c2529831..e4af2a9089 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -29,6 +29,9 @@ extern "C" { #endif typedef uint64_t ppc_cpu_t; +typedef uint16_t ppc_opindex_t; + +#define PPC_OPINDEX_MAX INT16_MAX /* The opcode table is an array of struct powerpc_opcode. */ @@ -60,7 +63,7 @@ struct powerpc_opcode /* An array of operand codes. Each code is an index into the operand table. They appear in the order which the operands must appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; + ppc_opindex_t operands[8]; }; /* The table itself is sorted by major opcode number, and is otherwise diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 38ddeca262..45e8faeef5 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -546,7 +546,7 @@ operand_value_powerpc (const struct powerpc_operand *operand, /* Determine whether the optional operand(s) should be printed. */ static bool -skip_optional_operands (const unsigned char *opindex, +skip_optional_operands (const ppc_opindex_t *opindex, uint64_t insn, ppc_cpu_t dialect, bool *is_pcrel) { const struct powerpc_operand *operand; @@ -592,7 +592,7 @@ lookup_powerpc (uint64_t insn, ppc_cpu_t dialect) opcode < opcode_end; ++opcode) { - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -637,7 +637,7 @@ lookup_prefix (uint64_t insn, ppc_cpu_t dialect) opcode < opcode_end; ++opcode) { - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -691,7 +691,7 @@ lookup_vle (uint64_t insn, ppc_cpu_t dialect) uint64_t table_mask = opcode->mask; bool table_op_is_short = PPC_OP_SE_VLE(table_mask); uint64_t insn2; - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -746,7 +746,7 @@ lookup_spe2 (uint64_t insn, ppc_cpu_t dialect) uint64_t table_opcd = opcode->opcode; uint64_t table_mask = opcode->mask; uint64_t insn2; - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; int invalid; @@ -925,7 +925,7 @@ print_insn_powerpc (bfd_vma memaddr, if (opcode != NULL) { - const unsigned char *opindex; + const ppc_opindex_t *opindex; const struct powerpc_operand *operand; enum { need_comma = 0, -- 2.36.0