From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x2d.google.com (mail-oa1-x2d.google.com [IPv6:2001:4860:4864:20::2d]) by sourceware.org (Postfix) with ESMTPS id D6E793858D37 for ; Wed, 28 Dec 2022 01:08:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D6E793858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1433ef3b61fso17164716fac.10 for ; Tue, 27 Dec 2022 17:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ExAgUdgFbmeyruXwWvsMNqp7gLw/yTtvYWS1jxJRis4=; b=SZ9VnuGsJXY6UBSrD9SjAA4TRnhNSkaOh6M/NzsvaU85KmX1KaTlroQP/fx8E9Q1Gj baXucPjpEjSJB/DGpx2tiamjzlsEKgW5JEF5ZiE3aI7U9aMOHPEkM8+xDEKc3D0P9kNt kbek23R1HlX2pg6A4Y74aXPnJ5yZHMRG4WKe3OjyEb70QS+YFwDvVLAQVy+K0c83eS85 XTkyxc4lqgY2l4PfL+XEqbeTDiAGKPrmX3yZA5cCJY09edZQsIHeCTkB+6wMP8wV/nzt ekwqtZL2K4lqXizph6I5OG3643M0rbnOW7SUuVCn1qnCpuvZJmIEqmz0L7FYRvM/cqBv 4YlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ExAgUdgFbmeyruXwWvsMNqp7gLw/yTtvYWS1jxJRis4=; b=YXGRjV0vBpmxQhzeStBYJCG798n/HiQHNtvDops+4KHaO6UbpD/UwBMKZwVPZTRURV z5280ltUOeMnym0vk1IKXzoJLXAIfh3faaY7+yP08yRbZCnZS/3G6sQQy0IkpdJ68aIi RJTtuOKmrohcKh3Fv2vpFLWzg2SSb9pj6IIOUK23PhlP1fzuQ5jRs0aw8CXeiWOpiJCX hn/wrvgX3dcjNmJ2dUobVA2Hd+AmxG+9mu9pkG3R00rXQ86lWX7PoTY1oy++yxlf0Y+O utl84JmkJoqupPwN0idcOIUoXaJek/p7ysaLcvjAWj029qJxmBcz/xdP6Dm6OHlmZUEE Uvwg== X-Gm-Message-State: AFqh2kqXERfZYQGvRqHpEtkYDyDo3o26u4cpyB9Q2rBxHIwYoPmI27nS MwmvMU0qLGho/p5huaQKLkfxeTrkBQcwdUaju8uBaxcruHAJJDou X-Google-Smtp-Source: AMrXdXvl1HJveDy5BsIHLfmdALUNpkY19oqW5IIV/xaoocwMsgMs4grLSHN0XdeKKrb2dDSJDsgBEplQl8YdgtZzQ8A= X-Received: by 2002:a05:6870:be8e:b0:14f:c77b:c7b with SMTP id nx14-20020a056870be8e00b0014fc77b0c7bmr926827oab.244.1672189718171; Tue, 27 Dec 2022 17:08:38 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Wed, 28 Dec 2022 09:08:26 +0800 Message-ID: Subject: Re: [Offline] Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding To: Philipp Tomsich Cc: Palmer Dabbelt , =?UTF-8?Q?Christoph_M=C3=BCllner?= , Binutils , Andrew Waterman , Lifang Xia Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thanks for your help! Nelson On Wed, Dec 28, 2022 at 3:45 AM Philipp Tomsich wrote: > > Nelson, > > I had missed the OK on this one as I had been traveling for RISC-V Summit= and now took care of it. > > Applied to master, thanks! > Philipp. > > > On Thu, 22 Dec 2022 at 02:51, Nelson Chu wrote: >> >> Do we expect this in the 2.40 release? I haven't seen this in master fo= r now. >> >> Thanks >> Nelson >> >> On Sat, Dec 17, 2022 at 3:00 AM Palmer Dabbelt wrot= e: >> > >> > On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu = wrote: >> > > On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt = wrote: >> > > >> > >> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.= eu >> > >> wrote: >> > >> > From: Christoph M=C3=BCllner >> > >> > >> > >> > A recent change in the XTheadFmv spec fixed an encoding bug in th= e >> > >> > document. This patch changes the code to follow this bugfix. >> > >> > >> > >> > Spec patch can be found here: >> > >> > https://github.com/T-head-Semi/thead-extension-spec/pull/11 >> > >> >> > >> There's not much info in there. Was this just a bug in the ISA man= ual? >> > >> In other words, does the existing hardware (I know of at least C906= s and >> > >> C910s in the wild) behave the new way already? In that case >> > >> >> > > >> > > Yes, this was just a bug in the ISA manual, which slipped through th= e >> > > review. >> > > The manual now matches the implementation. >> > >> > OK, thanks! >> > >> > > >> > > >> > > >> > >> >> > >> Reviewed-by: Palmer Dabbelt >> > >> >> > >> but if the hardware has the old behavior then we'll need to do some= thing >> > >> more complicated to avoid breaking compatibility. >> > >> >> > >> > >> > >> > Signed-off-by: Christoph M=C3=BCllner >> > >> > --- >> > >> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++-- >> > >> > include/opcode/riscv-opc.h | 4 ++-- >> > >> > 2 files changed, 4 insertions(+), 4 deletions(-) >> > >> > >> > >> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d >> > >> b/gas/testsuite/gas/riscv/x-thead-fmv.d >> > >> > index f2bbe010beb..af8ce0c8ee0 100644 >> > >> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d >> > >> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d >> > >> > @@ -7,5 +7,5 @@ >> > >> > Disassembly of section .text: >> > >> > >> > >> > 0+000 : >> > >> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 >> > >> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 >> > >> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 >> > >> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 >> > >> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-op= c.h >> > >> > index 06e3df0f5a6..5420bfac91b 100644 >> > >> > --- a/include/opcode/riscv-opc.h >> > >> > +++ b/include/opcode/riscv-opc.h >> > >> > @@ -2209,9 +2209,9 @@ >> > >> > #define MATCH_TH_FSURW 0x5000700b >> > >> > #define MASK_TH_FSURW 0xf800707f >> > >> > /* Vendor-specific (T-Head) XTheadFmv instructions. */ >> > >> > -#define MATCH_TH_FMV_HW_X 0x6000100b >> > >> > +#define MATCH_TH_FMV_HW_X 0x5000100b >> > >> > #define MASK_TH_FMV_HW_X 0xfff0707f >> > >> > -#define MATCH_TH_FMV_X_HW 0x5000100b >> > >> > +#define MATCH_TH_FMV_X_HW 0x6000100b >> > >> > #define MASK_TH_FMV_X_HW 0xfff0707f >> > >> > /* Vendor-specific (T-Head) XTheadInt instructions. */ >> > >> > #define MATCH_TH_IPOP 0x0050000b >> > >>