From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x31.google.com (mail-oa1-x31.google.com [IPv6:2001:4860:4864:20::31]) by sourceware.org (Postfix) with ESMTPS id 350423858C56 for ; Fri, 14 Oct 2022 01:32:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 350423858C56 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-136b5dd6655so4360334fac.3 for ; Thu, 13 Oct 2022 18:32:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=33FrUkORzNY6BiUshxvh+/6aQFCZ1QhUT6LJgRRPj0g=; b=7/eNX4f8HOpfehc7wwo7UtkQFwG5vjEVcMRxwfZQ7z4OjvBS+p3+OBJiaHMuxN1VDc aTm0Js9XRxQW2EbgX+SZw7PsTP4gwPlv7giJtN0XYLE80qf10NJN1NTQgnIrgodg/2/n Udc4iKnnW11qyaXO4unBe0Tv5ZlqBsN3SBe+4iFzE9R/V4+Vs8SwrJyMeTSBVvRvVSmf eFo2eLtGPWzry0Epz6XQw8yvSe6G8Ha0hj4GWjuBpyg4B+ZtDnSRCUlwWXb8eA1aSlqc 2EWe8lMcQsHgKxvWYxGU/M1SMH6PXJ6N82UxrQaAlrI71XL/c05CzSrL2/CAm7d0C1BS +INQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=33FrUkORzNY6BiUshxvh+/6aQFCZ1QhUT6LJgRRPj0g=; b=ezBr880muiT+wmHBiIr6e/nQXf1BePjrjODEiUn+i5rShM2qABp4PjqSiBL2G/Nb3N HK9gwu6CKWIhoa8v7KlgdqsacRrA52o7gy8OIIN6UWCLENN+2iuMd8rnvVEFVE4C+5GL jgMpdDZty3mCAWUc/biUMxkmoHI8CaShPESgsKdQQ7ahK5gdr4i9Zm0X1gHfrW0jfq+4 seq4PI3z4hYxXy4N4kMgJ5CY+x5LQZsneu0Cu7h14gWV8bc/5eZMbFZ5eQnqUS6Yx2tX nhl9wQLgcjoWEjrb6FcA8Edd2FMzPzOPSedVRXunr+Mjpca5N+vUixhz150+PKdJPWiJ p1XQ== X-Gm-Message-State: ACrzQf31rqkHiO95XVANq1K4P6i/E5BrO+iociCV7Vnp+YuFEbm6TBwL eCX3UYb8IDDlRBsEZW/VV3cDsSFM5OZ0LKEwFZ/3og== X-Google-Smtp-Source: AMsMyM5d/BfZB5817NYRDT9RW/zrnDZikWfS4Y8YRliUa9t4RcldVLqjDaUkFWaXQPTn5YFZcCe3rRNj6B93MFZinCU= X-Received: by 2002:a05:6870:507:b0:130:ae8d:db0e with SMTP id j7-20020a056870050700b00130ae8ddb0emr7228779oao.82.1665711143502; Thu, 13 Oct 2022 18:32:23 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Fri, 14 Oct 2022 09:32:12 +0800 Message-ID: Subject: Re: [PATCH v3 1/2] RISC-V: Fallback for instructions longer than 64b To: Tsukasa OI Cc: Kito Cheng , Palmer Dabbelt , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: In fact we don't really need this change, since so far the parameter length of validate_riscv_insn will only be 2 and 4, https://github.com/bminor/binutils-gdb/blob/master/gas/config/tc-riscv.c#L1349 Nelson On Thu, Oct 6, 2022 at 5:56 PM Tsukasa OI wrote: > > We don't support instructions longer than 64-bits yet. Still, we can > modify validate_riscv_insn function to prevent unexpected behavior by > limiting the "length" of an instruction to 64-bit (or less). > > gas/ChangeLog: > > * config/tc-riscv.c (validate_riscv_insn): Fix function > description comment based on current spec. Limit instruction > length up to 64-bit for now. Make sure that required_bits does > not corrupt even if unsigned long long is longer than 64-bit. > --- > gas/config/tc-riscv.c | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 22385d1baa0..41d6dfc6062 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -1109,7 +1109,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) > > /* For consistency checking, verify that all bits are specified either > by the match/mask part of the instruction definition, or by the > - operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */ > + operand list. The `length` could be the actual instruction length or > + 0 for auto-detection. */ > > static bool > validate_riscv_insn (const struct riscv_opcode *opc, int length) > @@ -1120,11 +1121,13 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) > insn_t required_bits; > > if (length == 0) > - insn_width = 8 * riscv_insn_length (opc->match); > - else > - insn_width = 8 * length; > + length = riscv_insn_length (opc->match); > + /* We don't support instructions longer than 64-bits yet. */ > + if (length > 8) > + length = 8; > + insn_width = 8 * length; > > - required_bits = ~0ULL >> (64 - insn_width); > + required_bits = ((insn_t)~0ULL) >> (64 - insn_width); > > if ((used_bits & opc->match) != (opc->match & required_bits)) > { > -- > 2.34.1 >