From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc2e.google.com (mail-oo1-xc2e.google.com [IPv6:2607:f8b0:4864:20::c2e]) by sourceware.org (Postfix) with ESMTPS id 796593858D37 for ; Fri, 17 Nov 2023 03:18:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 796593858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 796593858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::c2e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700191127; cv=none; b=Au9+t4pdr27pvZFFjJPZJ73ogsZoN2oC8NaY2C46ADIWqVaXCzcndtpZjNYnzKfmYhyjz9zwGubrBOPa0bVe/1f15kuJ061m8IsHkVcGpHyA5jFVIyMr5ww81ZAQOXZNbhNfLPTK3FeQ718ID2ufRmTeBzU5gAihMn+A8ZA5EAE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700191127; c=relaxed/simple; bh=daS7qrcc/H1VjcT5LLhDapd9pYhkoO/b75HzLMFqD+U=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=EM1nwWw0eQSUTpj5+BKosJkzkcPWZM5ZfG2bQX+gJrSZ8Trv4/mn2Zd6/Y9b63ROPFVG2Mwzos/rr51P+4S9BbOXStI6R4o1DgarVv2bqguBpdicaGARmrSKehnwKkRXbRzP1alEvTmL7JWB2Rj/DdsR24Yh7YU67VPmfyj0CVw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oo1-xc2e.google.com with SMTP id 006d021491bc7-58a6ad82b07so763663eaf.2 for ; Thu, 16 Nov 2023 19:18:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1700191124; x=1700795924; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=3h2rQesdlwWJNmO0ZLQm+5Bjw86F8gDhBvJWHUFZiTU=; b=Uc4hDH1oHqyuuM/TZ1AYqeN7jzDhLPMuV2oGwm4kjLW0hW5a2Cslr6SUJ9k9eTJQvp q0cwuiaoGuTOS5dcakJoPnxQJN8vNvWRcjvbqwCJ0QuyYbc3ARwJpyIEtPwBWBVfJGIj 0Rri92gtZBRlxP5u/Ah+/6sv10XwijpmYyMV5bc/OHH7qbySlZJIE3Umaoee8Q3NJjtg f2tQ0w2qMbazVcs67nS+UmC9/HPKGbdEaq8Forj9ryJwyisY04hMF8NO8wXW061Sygv4 QEqYo5Q19U8sYnisTnPWGNWA3Rn5KeAfj/P7o4aAhXC4R0NZohHIT393Ul7iQX8Jr1db gH0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700191124; x=1700795924; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3h2rQesdlwWJNmO0ZLQm+5Bjw86F8gDhBvJWHUFZiTU=; b=vONR+7PneNO4qNSXV+pEpEbR+EZqMMR34V4/Dte1WPzAY9cS9hogF2ZGA05dMgfbwv aLbfv27r1Eqqo1i8khJjXyFtkOexBdtn6w70ErAErwAgkggg5r0udMBvkaNW6g8BLeCL r8B6uIkJGB7AteCzGFpAPLM8pQvQjnUdAHq8/c0uImJ3AI6QV+OsaeQ4l1N6r0Xoz8ks HvVeN/4fg2W/y0HmPaCQ37pS63ibDLg4am780kdgxD5S1JSyEXzNTdppshHBn5sEouWL l/4y2PXIHxACx9vsriE3kO7HqLIGlXfDIHcQqZKvrf88zhYB9ZGfrqFTw1gDWcBCB0Y7 BNjA== X-Gm-Message-State: AOJu0YyyxbXK7vHv4mbv4kuU4H4PdF8skf83BkDOx0QRbnBuo0QyZLoG /Yq35dPQmx/bx1abJMMiRM5IFnJrD7YEM7TV9m7FelzmR1sNz1GF2uxjqA== X-Google-Smtp-Source: AGHT+IGxXyJ+5ZQzzqd/ITaDO09Tk4RfbfptUXRffoJVWE0dPS1gSl8mmbqrUi2lYEcBPsThPgUvvc2SqrvZ+fE2NCA= X-Received: by 2002:a05:6870:84cb:b0:1f4:dd99:afa with SMTP id l11-20020a05687084cb00b001f4dd990afamr20578507oak.8.1700191123673; Thu, 16 Nov 2023 19:18:43 -0800 (PST) MIME-Version: 1.0 References: <20231110071759.1640-1-jinma@linux.alibaba.com> <20231110072224.1735-1-jinma@linux.alibaba.com> In-Reply-To: <20231110072224.1735-1-jinma@linux.alibaba.com> From: Nelson Chu Date: Fri, 17 Nov 2023 11:18:32 +0800 Message-ID: Subject: Re: [PATCH 03/12] RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor extension To: Jin Ma Cc: binutils@sourceware.org, christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com Content-Type: multipart/alternative; boundary="000000000000fa4ea5060a509719" X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000fa4ea5060a509719 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Nov 10, 2023 at 3:22=E2=80=AFPM Jin Ma wr= ote: > T-Head has a range of vendor-specific instructions. > Therefore it makes sense to group them into smaller chunks > in form of vendor extensions. > > This patch adds configuration-setting instructions for the "XTheadVector" > extension. The 'th' prefix and the "XTheadVector" extension are documented > in a PR for the RISC-V toolchain conventions ([1]). > > [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 > > Co-developed-by: Lifang Xia > Co-developed-by: Christoph M=C3=BCllner > > gas/ChangeLog: > > * testsuite/gas/riscv/x-thead-vector.d: New test. > * testsuite/gas/riscv/x-thead-vector.s: New test. > > include/ChangeLog: > > * opcode/riscv-opc.h (MATCH_TH_VSETVL): New. > > opcodes/ChangeLog: > > * riscv-opc.c: Likewise.. > --- > gas/testsuite/gas/riscv/x-thead-vector.d | 12 ++++++++++++ > gas/testsuite/gas/riscv/x-thead-vector.s | 3 +++ > include/opcode/riscv-opc.h | 5 +++++ > opcodes/riscv-opc.c | 4 ++++ > 4 files changed, 24 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d > > diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d > b/gas/testsuite/gas/riscv/x-thead-vector.d > new file mode 100644 > index 00000000000..e509ed0971b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/x-thead-vector.d > @@ -0,0 +1,12 @@ > +#as: -march=3Drv32if_xtheadvector > +#objdump: -dr > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 <.text>: > +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,= mu > +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047 > diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s > b/gas/testsuite/gas/riscv/x-thead-vector.s > index e69de29bb2d..ffea0a6f9f9 100644 > --- a/gas/testsuite/gas/riscv/x-thead-vector.s > +++ b/gas/testsuite/gas/riscv/x-thead-vector.s > @@ -0,0 +1,3 @@ > + th.vsetvl a0, a1, a2 > + th.vsetvli a0, a1, 0 > + th.vsetvli a0, a1, 0x7ff > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index ed29384e825..dc18dd9f04c 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2648,6 +2648,11 @@ > #define MASK_TH_SYNC_IS 0xffffffff > #define MATCH_TH_SYNC_S 0x0190000b > #define MASK_TH_SYNC_S 0xffffffff > +/* Vendor-specific (T-Head) XTheadVector instructions. */ > +#define MATCH_TH_VSETVL 0x80007057 > +#define MASK_TH_VSETVL 0xfe00707f > +#define MATCH_TH_VSETVLI 0x00007057 > +#define MASK_TH_VSETVLI 0x8000707f > Seems like the whole t-head vector instructions will have the same encodings as standard vector ones. Could we just use MATCH/MASK_VSETVL to replace MATCH/MASK_TH_VSETVL, and for all related vendor instructions? Thanks Nelson > /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ > #define MATCH_VT_MASKC 0x607b > #define MASK_VT_MASKC 0xfe00707f > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 72d727cd77e..2fb7cf1e14a 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, > MASK_TH_SYNC_IS, match_opcode, 0}, > {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, > MASK_TH_SYNC_S, match_opcode, 0}, > > +/* Vendor-specific (T-Head) XTheadVector instructions. */ > +{"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_TH_VSETVL, > MASK_TH_VSETVL, match_opcode, 0}, > +{"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc", > MATCH_TH_VSETVLI, MASK_TH_VSETVLI, match_opcode, 0}, > + > /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ > {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, > MASK_VT_MASKC, match_opcode, 0 }, > {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, > MASK_VT_MASKCN, match_opcode, 0 }, > -- > 2.17.1 > > --000000000000fa4ea5060a509719--