From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by sourceware.org (Postfix) with ESMTPS id 9D2D738505F4 for ; Thu, 6 Jun 2024 02:26:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9D2D738505F4 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9D2D738505F4 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::52a ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717640789; cv=none; b=eJ3k4LF/YJ1tyum1PGY5DTnIh37Y4mdTA4H3vSetZrrvpBlbQj7LOCvLftAO+BNnFJsamQ2QkKUX/gdjuLfik3GW6wyf0xvz/NkU6pQQ4NeGKsOXIwSpEjO1JKjI9xIjRWnSjI1D3oqQSRXPWagbH7mnbTGCRtaFK7C7b/LEVuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717640789; c=relaxed/simple; bh=UrLwzfqtm2BN5GdfUE/aOQj9Tx9R6wrmO/tZH7rUqhs=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=DSNvbNZ5w8vtm1rXIplfd6kZYfZMjFDN4sXrxl48dr0gtiviaObTCYWEfjy6Sn4s/aAkwWfTK4ddHs0zpQ5Ew29tks77HXvN/Dss2XnX9euiMN3l39h/rVGd02O4TPvDVkgF6q+IfVvgdE6AIHNM1rjwOmBK1kqFNfmy5sDM9EE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-57a677d3d79so2914323a12.1 for ; Wed, 05 Jun 2024 19:26:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717640784; x=1718245584; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=5SFrdrAEwlGL5P9sNQzelEMdeiV3EM1Cmpd09Z2dJfQ=; b=1NH7zNawYN9LuO9jEDjPiBAcNshDeAe4n7ujxApkbO/m76E5eaukDWEHtQrszkJZql mtBf5IX0QF8UIr5XOSrcaVOhw3DBENIXxJ+qna8+p+KaWvTZx0wPtMPK6Ko6gyp3K/xV Mw1zKxcswuwTBBVbs8TLB5Yoj2tx3f6/yXPtl8MZCVUcR/Nt62o8wl/S62DzMpfZqkbF 8OOrYPqUXUDuZqj4f8gL39kUQZn29f/5uk5PrONmadUqR+QfaWCv4xT4YIPsNq7r9zo/ jKIpAMXucnAItch4lGpyiuUiD7dBG2Tg2BTiwFBewjPu3bg0M1MEGvLxZN3yXx21vfks Bw0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717640784; x=1718245584; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5SFrdrAEwlGL5P9sNQzelEMdeiV3EM1Cmpd09Z2dJfQ=; b=qbKdV34RKGbK6jdAbSP0wJMiYsp8sU+GbvqhDl7xftmqLuofa4Frh/geARtIU68MgI XkaNRBXLDJRoyrQi+hVRsudFrzGERtQFsaJQP9J9GCe51K4kpB3+jGGfbsR/gwrOkdjE VB3DSMkinRT2jEYxF8NyImKogClp5FvILOfKUgTk0n5csrr6uVAQYU5EusS+ZK1TnOye VIIMMcmBoKLv1AIfi0lhzI6iaPN5Wfd16CvZMjqd1TZ3VrcsWUUnQTM3Uu1LmotXDYf0 Sf07WpHP8/22hzxfX6zvSoy9G+vNko9Ksbt27CIRYw3q651knjHXEbQRD/EA1RwC8LK+ 1Bqw== X-Gm-Message-State: AOJu0YyYiK0cEQi4sull3PVWjkiEx4yqQX1aTCGPbuxX09dPKSXNgnOb aMpVvS1QawaDKZokx3oPS+1H7ooCJ6RJX59xVnqD27GJx3HvIIal3T6PE9s3KbZ0i2NJNck1t95 rv7QEHoCD6I8gm1LBdFMHlM3oVGP2bmJMSdh8kg== X-Google-Smtp-Source: AGHT+IG1kc99FuRgbqQzDxrMdOKWqDxdGuEQRarK1+BHNap+GxNRspYDZ0eOopvZzbt8J/z9p/N4MtUP6IDghcxb4B0= X-Received: by 2002:a17:906:16d3:b0:a67:f689:b695 with SMTP id a640c23a62f3a-a6c760a6403mr106207766b.16.1717640783873; Wed, 05 Jun 2024 19:26:23 -0700 (PDT) MIME-Version: 1.0 References: <20240605013613.78830-1-zengxiao@eswincomputing.com> <20240605013613.78830-2-zengxiao@eswincomputing.com> In-Reply-To: <20240605013613.78830-2-zengxiao@eswincomputing.com> From: Nelson Chu Date: Thu, 6 Jun 2024 10:26:12 +0800 Message-ID: Subject: Re: [PING] [PATCH 1/3] RISC-V: Add support for Zfbfmin extension To: Xiao Zeng Cc: binutils@sourceware.org, kito.cheng@gmail.com, palmer@dabbelt.com, zhengyu@eswincomputing.com Content-Type: multipart/alternative; boundary="000000000000c664fc061a2f6807" X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000c664fc061a2f6807 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Jun 5, 2024 at 9:30=E2=80=AFAM Xiao Zeng wrote: > This implements the Zfbfmin extension, as of version 1.0. > > View detailed information in: > < > https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfb= fmin---scalar-bf16-converts > > > > 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and > FMV.H.X instructions as defined in the Zfh extension. > > 2 The Zfhmin extension includes the following instructions from the Zfh > extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: > > > 3 Zfhmin extension depend on 'F'. > > 4 Simply put, just make Zfbfmin dependent on Zfhmin. > > Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and > FMV.H.X instructions an independent extension to achieve precise dependen= cy > relationships for the Zfbfmin. > > 5 For relevant information in gcc, please refer to: > < > https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3D35224ead63732a3550ba4= b1332c06e9dc7999c31 > > > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. > (riscv_multi_subset_supports_ext): Ditto. > > gas/ChangeLog: > > * NEWS: Updated. > * testsuite/gas/riscv/march-help.l: Ditto. > * testsuite/gas/riscv/zfbfmin.d: New test. > * testsuite/gas/riscv/zfbfmin.s: New test. > > include/ChangeLog: > > * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. > (MASK_FCVT_BF16_S): Ditto. > (MATCH_FCVT_S_BF16): Ditto. > (MASK_FCVT_S_BF16): Ditto. > (DECLARE_INSN): New declarations for Zfbfmin. > * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. > > opcodes/ChangeLog: > > * riscv-opc.c: Add Zfbfmin instructions. > --- > bfd/elfxx-riscv.c | 6 ++++++ > gas/NEWS | 2 ++ > gas/testsuite/gas/riscv/march-help.l | 1 + > gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++ > gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++ > include/opcode/riscv-opc.h | 8 ++++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 5 +++++ > 8 files changed, 40 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d > create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index dfacb87eda0..d9709a232e6 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1224,6 +1224,7 @@ static struct riscv_implicit_subset > riscv_implicit_subsets[] =3D > {"zcf", "f", check_implicit_always}, > {"zfa", "f", check_implicit_always}, > {"d", "f", check_implicit_always}, > + {"zfbfmin", "zfhmin", check_implicit_always}, > {"zfh", "zfhmin", check_implicit_always}, > {"zfhmin", "f", check_implicit_always}, > {"f", "zicsr", check_implicit_always}, > @@ -1360,6 +1361,7 @@ static struct riscv_supported_ext > riscv_supported_std_z_ext[] =3D > {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -2561,6 +2563,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t > *rps, > case INSN_CLASS_Q_INX: > return (riscv_subset_supports (rps, "q") > || riscv_subset_supports (rps, "zqinx")); > + case INSN_CLASS_ZFBFMIN: > + return riscv_subset_supports (rps, "zfbfmin"); > Placed before INSN_CLASS_ZFA like the following change? > case INSN_CLASS_ZFH_INX: > return (riscv_subset_supports (rps, "zfh") > || riscv_subset_supports (rps, "zhinx")); > @@ -2827,6 +2831,8 @@ riscv_multi_subset_supports_ext > (riscv_parse_subset_t *rps, > return "zhinxmin"; > else > return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); > + case INSN_CLASS_ZFBFMIN: > + return "zfbfmin"; > case INSN_CLASS_ZFA: > return "zfa"; > case INSN_CLASS_D_AND_ZFA: > diff --git a/gas/NEWS b/gas/NEWS > index e51c3bbba6d..b88c54fc5c3 100644 > --- a/gas/NEWS > +++ b/gas/NEWS > @@ -1,5 +1,7 @@ > -*- text -*- > > +* Add support for RISC-V Zfbfmin extension with version 1.0. > + > Added after "Add support for RISC-V Zcmp extension with version 1.0." > * In x86 Intel syntax undue mnemonic suffixes are now warned about. This > is > a first step towards rejecting their use where unjustified. > > diff --git a/gas/testsuite/gas/riscv/march-help.l > b/gas/testsuite/gas/riscv/march-help.l > index c5754837e05..9deaa841622 100644 > --- a/gas/testsuite/gas/riscv/march-help.l > +++ b/gas/testsuite/gas/riscv/march-help.l > @@ -26,6 +26,7 @@ All available -march extensions for RISC-V: > zalrsc 1.0 > zawrs 1.0 > zfa 1.0 > + zfbfmin 1.0 > zfh 1.0 > zfhmin 1.0 > zfinx 1.0 > diff --git a/gas/testsuite/gas/riscv/zfbfmin.d > b/gas/testsuite/gas/riscv/zfbfmin.d > new file mode 100644 > index 00000000000..7cacc0bd684 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfbfmin.d > @@ -0,0 +1,11 @@ > +#as: -march=3Drv64i_zfbfmin > +#objdump: -d > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1 > +[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne > +[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1 > diff --git a/gas/testsuite/gas/riscv/zfbfmin.s > b/gas/testsuite/gas/riscv/zfbfmin.s > new file mode 100644 > index 00000000000..c9a9af3e394 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfbfmin.s > @@ -0,0 +1,6 @@ > +target: > + # fcvt.bf16.s > + fcvt.bf16.s fa0, fa1 > + fcvt.bf16.s fa0, fa1, rne > + # fcvt.s.bf16 > + fcvt.s.bf16 fa0, fa1 > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index ae14e14d427..26d60bc585e 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2365,6 +2365,11 @@ > #define MASK_WRS_NTO 0xffffffff > #define MATCH_WRS_STO 0x01d00073 > #define MASK_WRS_STO 0xffffffff > +/* Zfbfmin intructions. */ > +#define MATCH_FCVT_BF16_S 0x44800053 > +#define MASK_FCVT_BF16_S 0xfff0007f > +#define MATCH_FCVT_S_BF16 0x40600053 > +#define MASK_FCVT_S_BF16 0xfff0007f > /* Vendor-specific (CORE-V) Xcvmac instructions. */ > #define MATCH_CV_MAC 0x9000302b > #define MASK_CV_MAC 0xfe00707f > @@ -3912,6 +3917,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, > MASK_C_NTL_ALL) > /* Zawrs instructions. */ > DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) > DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) > +/* Zfbfmin instructions. */ > +DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) > +DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) > /* Zvbb/Zvkb instructions. */ > DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) > DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index 5f516a1026e..0e58dbe3d03 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -447,6 +447,7 @@ enum riscv_insn_class > INSN_CLASS_ZFHMIN_AND_D_INX, > INSN_CLASS_ZFHMIN_AND_Q_INX, > INSN_CLASS_ZFA, > + INSN_CLASS_ZFBFMIN, > Likewise, before ZFA > INSN_CLASS_D_AND_ZFA, > INSN_CLASS_Q_AND_ZFA, > INSN_CLASS_ZFH_AND_ZFA, > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 1ef4eaddf4d..9f99aa6c792 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1132,6 +1132,11 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"fltq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLTQ_H, > MASK_FLTQ_H, match_opcode, 0 }, > {"fleq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLEQ_H, > MASK_FLEQ_H, match_opcode, 0 }, > > +/* Zfbfmin instructions. */ > +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", > MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, > +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, > MASK_FCVT_BF16_S, match_opcode, 0 }, > +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, > MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, > 1. MATCH_FCVT_S_BF16|MASK_RM, MASK_FCVT_S_BF16, looks like you put it backwards? 2. The fcvt.s.bf16 with "D,S,m"? 3. Moved between half-precision floating-point instruction subset and single-precision floating-point instruction subset? + > /* Zbb or zbkb instructions. */ > {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, > match_opcode, 0 }, > {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, > match_opcode, 0 }, > -- > 2.17.1 > > --000000000000c664fc061a2f6807--