Generally the OP_CUSTOM_0/1/2/3 are reserved for vendor/custom/non-standard usage. Non-standard extensions that use space that’s reserved for standard extensions are considered to be “non-conforming”. We discourage (but not disallow) non-conforming extensions, since it is highly likely that future standard extensions will reclaim space used by them. However, the t-head vector is kind of different, according to my understanding, it's actually rvv 0.7. Since we don't have plans to support multi-version encodings, and the reasons that t-head released rvv 0.7 are complicated, we recommended them to use vendor/non-standard extensions to solve this problem. Since the patches make sure that t-head vector and standard vector won't be enabled at the same time, the conflicted encodings should work well in current implementation. Anyway, committed. Thanks Nelson On Sat, Nov 18, 2023 at 2:49 PM Jin Ma wrote: > V1 -> V2: > > V2 adopted the review comments of Nelson and modified the > instructions encoding of vendor: Reuse the instruction > encoding of the "V" extension as much as possible and > remove redundant instructions encoding. > > V1: > > T-Head has a range of vendor-specific instructions ([2]). > Therefore it makes sense to group them into smaller chunks > in form of vendor extensions. > > This patch adds the "XTheadVector" extension, a collection of > T-Head-specific vector instructions. The 'th' prefix and the > "XTheadVector" extension are documented in a PR for the RISC-V > toolchain conventions ([1]). > > Here are some things that need to be explained: > The "XTheadVector" extension is not a custom-extension, but > a non-standard non-conforming extension. The encoding space > of the "TheadVector" instructions overlaps with those of > the 'V' extension. This encoding space conflict is not on > purpose, but the result of issues in the past that have > been resolved since. Therefore, the "XTheadVector" extension > and the 'V' extension are in conflict. > > [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 > [2] > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf > > Co-developed-by: Lifang Xia > Co-developed-by: Christoph Müllner > > --- > bfd/elfxx-riscv.c | 17 + > gas/NEWS | 3 + > gas/config/tc-riscv.c | 4 + > gas/doc/c-riscv.texi | 11 + > .../gas/riscv/x-thead-vector-csr-warn.d | 3 + > .../gas/riscv/x-thead-vector-csr-warn.l | 16 + > gas/testsuite/gas/riscv/x-thead-vector-csr.d | 21 + > gas/testsuite/gas/riscv/x-thead-vector-csr.s | 13 + > gas/testsuite/gas/riscv/x-thead-vector-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-vector-fail.l | 2 + > .../gas/riscv/x-thead-vector-zvamo.d | 81 + > .../gas/riscv/x-thead-vector-zvamo.s | 74 + > gas/testsuite/gas/riscv/x-thead-vector.d | 1650 ++++++++++++++++ > gas/testsuite/gas/riscv/x-thead-vector.s | 1726 +++++++++++++++++ > include/opcode/riscv-opc.h | 328 ++++ > include/opcode/riscv.h | 2 + > opcodes/riscv-dis.c | 14 +- > opcodes/riscv-opc.c | 661 +++++++ > 18 files changed, 4627 insertions(+), 2 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s > > -- > 2.17.1 > >