From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x30.google.com (mail-oa1-x30.google.com [IPv6:2001:4860:4864:20::30]) by sourceware.org (Postfix) with ESMTPS id C95E93834DB4 for ; Thu, 23 Nov 2023 02:37:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C95E93834DB4 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C95E93834DB4 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:4860:4864:20::30 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700707067; cv=none; b=OjQoQ5J1h+StdwpU1hZg4JQO2fypIA6rPBLKLcXlcqy/9UIuZbuqS+krYspvuccls/TmaMp5Aza7h9ymnrjJp+perzF3WlU0rBfcczfVsXtf3S+ExIpGJ8bLEeeKvHwotj1JZrBQaWOS48AnRGmaWR+ZmMTuqh6h38jvEOqeKlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700707067; c=relaxed/simple; bh=i9ByQC/jtXRJ+Bxt2TgYY/lvRgut5sqaFnQOfTca+MI=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=EFQKSJNiWgJFieLezN+kAiVLp5rg4nNmzOUmP2JalKpaETxsXw0zBdz32TIBJMoJV2Snd0rQbrHcachzSJpnnKfNSQVARWMbNH51q2KFhPo4g5lRNAkj5LG2L/a1NtfmMaLlaGdQ1nARhhRlntHIxKulhPcq/c3L2czgDRsXOhU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oa1-x30.google.com with SMTP id 586e51a60fabf-1f066fc2a2aso271655fac.0 for ; Wed, 22 Nov 2023 18:37:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1700707063; x=1701311863; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=RC0kavdZrM3hjU6ijLY3iHw1swQo9XkRStwz3fiidt4=; b=L2E6yPaNLRYjKYcXPK46mPeAAdrv3/ytURZQvn4mrV6mtcCVf6XN8ug79hKKxk0KLx aJGRCqV902tgnrAkO/PeouWLXHenVxoWVKmOT6jaiqieG5AnZ5NArmJ2y4tVNEHlA4XT wSYDyHAVNFrjummPArXFnxYYkdl2k0uzZUMRQ/SdXig7o/emPt9kzOc4OYZ3Z6vlm5hO jdur1kyK8ZMarzLQJG27IgifT03QmZgJuQBovCTFJ8PFwEnNfXX3+hojb0Pb70cBx7ap G8ljXrwmqfC7L5zsEQuxCGpGYClK4LkSLJ7Iuw74wVyaYMlwzFe50RKQZdcFQJKz04AT bJrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700707063; x=1701311863; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=RC0kavdZrM3hjU6ijLY3iHw1swQo9XkRStwz3fiidt4=; b=INqG1TbqutDCAlwkIWCDzniZXvssP9nnhzcpRODrcmrp/dzq8fFWouFFG19j4IzD86 Zen2p+oHMtBHe5svRwmcO8illFYBhTGbCbhDqSS34iV1RUDVNL20bGqUophD991HElW5 5BIh7DDLKiQmGd5LkwwQqRvy1dkYP0oNXnKl0fRjMCjAn7pDRNxnHq/LLGm9oPqx9OHz mDuiXIvJh+wuLx9m4Pt0Qvx3NNvewanqahelz26bUX5b/zBcWw8ldD72dqwKkBo92J13 zeQ9WjTa/aWpRqHbScvN8MZ04Uu4EqcOyyZWSOHtkoHW7d/qZ1PKTT2taFDQOo8HXNCB 40/w== X-Gm-Message-State: AOJu0Yzj5A8LBaaY74tsJKklx+LyKdrwmJTUwZ5J67a35mCANCnKgYXY nPNr+7jaBlsxshUvm56cuI/u8WNQg+mniFYU+H/C5YfqyDDcXB2WqBPvDA== X-Google-Smtp-Source: AGHT+IFjBdxkWXMEmCq4Gb0H+ToQGsBL5lFhr2FqRmjKpClskbegVpryP06DrPmIijKxdUWLzXMs3MeC4m0fg/KPzPs= X-Received: by 2002:a05:6870:7e13:b0:1f4:ecdb:fb2 with SMTP id wx19-20020a0568707e1300b001f4ecdb0fb2mr5788060oab.54.1700707063365; Wed, 22 Nov 2023 18:37:43 -0800 (PST) MIME-Version: 1.0 References: <20231118064928.849-1-jinma@linux.alibaba.com> In-Reply-To: <20231118064928.849-1-jinma@linux.alibaba.com> From: Nelson Chu Date: Thu, 23 Nov 2023 10:37:32 +0800 Message-ID: Subject: Re: [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension. To: Jin Ma Cc: binutils@sourceware.org, christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com Content-Type: multipart/alternative; boundary="00000000000061141e060ac8b8b4" X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000061141e060ac8b8b4 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Generally the OP_CUSTOM_0/1/2/3 are reserved for vendor/custom/non-standard usage. Non-standard extensions that use space that=E2=80=99s reserved for = standard extensions are considered to be =E2=80=9Cnon-conforming=E2=80=9D. We disco= urage (but not disallow) non-conforming extensions, since it is highly likely that future standard extensions will reclaim space used by them. However, the t-head vector is kind of different, according to my understanding, it's actually rvv 0.7. Since we don't have plans to support multi-version encodings, and the reasons that t-head released rvv 0.7 are complicated, we recommended them to use vendor/non-standard extensions to solve this problem. Since the patches make sure that t-head vector and standard vector won't be enabled at the same time, the conflicted encodings should work well in current implementation. Anyway, committed. Thanks Nelson On Sat, Nov 18, 2023 at 2:49=E2=80=AFPM Jin Ma wr= ote: > V1 -> V2: > > V2 adopted the review comments of Nelson and modified the > instructions encoding of vendor: Reuse the instruction > encoding of the "V" extension as much as possible and > remove redundant instructions encoding. > > V1: > > T-Head has a range of vendor-specific instructions ([2]). > Therefore it makes sense to group them into smaller chunks > in form of vendor extensions. > > This patch adds the "XTheadVector" extension, a collection of > T-Head-specific vector instructions. The 'th' prefix and the > "XTheadVector" extension are documented in a PR for the RISC-V > toolchain conventions ([1]). > > Here are some things that need to be explained: > The "XTheadVector" extension is not a custom-extension, but > a non-standard non-conforming extension. The encoding space > of the "TheadVector" instructions overlaps with those of > the 'V' extension. This encoding space conflict is not on > purpose, but the result of issues in the past that have > been resolved since. Therefore, the "XTheadVector" extension > and the 'V' extension are in conflict. > > [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 > [2] > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3= .0/xthead-2023-11-10-2.3.0.pdf > > Co-developed-by: Lifang Xia > Co-developed-by: Christoph M=C3=BCllner > > --- > bfd/elfxx-riscv.c | 17 + > gas/NEWS | 3 + > gas/config/tc-riscv.c | 4 + > gas/doc/c-riscv.texi | 11 + > .../gas/riscv/x-thead-vector-csr-warn.d | 3 + > .../gas/riscv/x-thead-vector-csr-warn.l | 16 + > gas/testsuite/gas/riscv/x-thead-vector-csr.d | 21 + > gas/testsuite/gas/riscv/x-thead-vector-csr.s | 13 + > gas/testsuite/gas/riscv/x-thead-vector-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-vector-fail.l | 2 + > .../gas/riscv/x-thead-vector-zvamo.d | 81 + > .../gas/riscv/x-thead-vector-zvamo.s | 74 + > gas/testsuite/gas/riscv/x-thead-vector.d | 1650 ++++++++++++++++ > gas/testsuite/gas/riscv/x-thead-vector.s | 1726 +++++++++++++++++ > include/opcode/riscv-opc.h | 328 ++++ > include/opcode/riscv.h | 2 + > opcodes/riscv-dis.c | 14 +- > opcodes/riscv-opc.c | 661 +++++++ > 18 files changed, 4627 insertions(+), 2 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s > > -- > 2.17.1 > > --00000000000061141e060ac8b8b4--