From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc2f.google.com (mail-oo1-xc2f.google.com [IPv6:2607:f8b0:4864:20::c2f]) by sourceware.org (Postfix) with ESMTPS id CA40B3858D20 for ; Wed, 20 Sep 2023 01:08:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CA40B3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oo1-xc2f.google.com with SMTP id 006d021491bc7-573449a364fso4057032eaf.1 for ; Tue, 19 Sep 2023 18:08:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1695172109; x=1695776909; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=vXns5ITLAbvUVzybNbv3cqJDVjP3Vn7ANNwpOIBHeQ4=; b=nFDhd4Gc7f85CK8oYP9MXFQIf5ebfCjtAJ6LZeOWUpOJyiUoun9eKXxNtb4rgC53MZ wL0sbLLunFUv7h9qBmVE80jaFVKAfMGVMSH/UYKgaSM40BmO7/E/Ly95/vL+VGWKGJrk 14S3KPpJc9rMQ9OSdN2j+yAh0UtHbiBBcxF2d7/ieEUjKida+Xh7GaFHQ23Hzbsr1APq CSuuVCt2QobbO+4g9gGY+wxG2stN0olBhGgpREqsyu4PFWn44I5SqUENaUqXHi83gT25 SIcfvYQ+G1QTG3zBUrodG3wm8ekVgVkonjr/bN4MndfdffIZzCIvusBxf9IfpZ3lE6Wn KcpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695172109; x=1695776909; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=vXns5ITLAbvUVzybNbv3cqJDVjP3Vn7ANNwpOIBHeQ4=; b=wR2R3GbqWx1c7E9dPlXblCUuGplFs5myirX/Erva1vApqr2/1lf3ekDfe8bBB6DeZm akzmC9wRYSX4+Ehym0E4SJXkcljtBIRY9Sd7sezQJkEeyAiVw6qt1Zv0j+8Xqgg4JHbO /EwgrlqUqOqbTXnpHcJgp5JPuw2xlEXKx4ggYacrRLhBRTbQX1HoQWFGRAywTA57xZfh d8O1+qH1CRwjVLYnh+wNPM1EzLl/qgiMHPkZPcHk9F+W0FODcChfwCO3TeGHrxn8Gl82 v2JENo6E41YvJ+XXTiOj9WzNilNkqKuKMYSdXrlgGMuWLOJFerHkTzMhtmb/akYhAT4c 92Dw== X-Gm-Message-State: AOJu0YwWgFVljsVlG5iXjqWJenopMgjyXqCmID+7o/iMC3RnlKIY9tcl 04ZHIhKInFDJmzfGM6inW5j1KVS2VGqauu+IyzPukQ== X-Google-Smtp-Source: AGHT+IGyGSWgJvpgslJaKVKTXQu+TDhsP99J1crVM09WDPetdlzX4qM++r1XLGf9d6RabFVP0ka5IPkfoU4CAUI2IAs= X-Received: by 2002:a05:6870:468f:b0:1ba:9a49:d967 with SMTP id a15-20020a056870468f00b001ba9a49d967mr1264353oap.23.1695172108970; Tue, 19 Sep 2023 18:08:28 -0700 (PDT) MIME-Version: 1.0 References: <20230919070121.1489019-1-ruiu@bluewhale.systems> In-Reply-To: <20230919070121.1489019-1-ruiu@bluewhale.systems> From: Nelson Chu Date: Wed, 20 Sep 2023 09:08:18 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: emit R_RISCV_RELAX for the la pseudo instruction To: Rui Ueyama Cc: binutils@sourceware.org, Rui Ueyama Content-Type: multipart/alternative; boundary="0000000000006384dd0605c003f9" X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000006384dd0605c003f9 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Sep 19, 2023 at 3:03=E2=80=AFPM Rui Ueyama via Binutils < binutils@sourceware.org> wrote: > Some psABIs define a relaxation to turn a GOT load into a PC-relative > address materialization. For example, the AArch64's psABI allows > adrp+ldr to be rewritten to nop+adr to eliminate the memory load. > This patch is part of the effort to make such optimization possible > for RISC-V. > > For RISC-V, we use the la assembly pseudo instruction to load a symbol > address from the GOT. The pseudo instruction is expanded to auipc+ld. > If the address loaded by the instruction pair is actually a > PC-relative link-time constant, we want the linker to rewrite the > instruction pair with auipc+addi. > > We can't rewrite all existing auipc+ld pairs with auipc+addi in the > linker because there might be code that jumps to the middle of the > instruction pair. That should be extremely rare, if ever exists, but > you can at least in theory write a program in assembly that jumps to > the ld instruction of the instruction pair. We need a marker to > identify that an auipc+ld can be safely relaxed (i.e. they are emitted > for la). > Make sense. > This patch is to annotate R_RISCV_GOT_HI20 with R_RISCV_RELAX only > when the relocation is emitted for the la pseudo instruction. The > linker will use it as a signal that the instruction pair can be safely > relaxed. > Currently GNU ld won't do any relaxations for GOT patterns, so we will also need the related updates in the future. Besides, not sure if the new GOT relaxations will break this feature for undefined weak symbol, https://github.com/bminor/binutils-gdb/commit/9d1da81b261a20050ef2ad01a5b4c= 8cf78404222. But fortunately if we just mark the R_RISCV_RELAX for GOT_HI20 in assembler, that shouldn't cause a problem since currently ld will ignore it for now. > Proposal to the RISC-V psABI: > https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/397 > --- > bfd/bfd-in2.h | 1 + > bfd/elfxx-riscv.c | 1 + > gas/config/tc-riscv.c | 3 ++- > gas/testsuite/gas/riscv/la-variants.d | 3 +++ > 4 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h > index 1c4f75ae244..e15641a1d00 100644 > --- a/bfd/bfd-in2.h > +++ b/bfd/bfd-in2.h > @@ -5413,6 +5413,7 @@ number for the SBIC, SBIS, SBI and CBI instructions > */ > BFD_RELOC_RISCV_SUB32, > BFD_RELOC_RISCV_SUB64, > BFD_RELOC_RISCV_GOT_HI20, > + BFD_RELOC_RISCV_GOT_HI20_RELAX, > BFD_RELOC_RISCV_TLS_GOT_HI20, > BFD_RELOC_RISCV_TLS_GD_HI20, > BFD_RELOC_RISCV_JMP, > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 6ed657171f0..71e63e7b789 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -913,6 +913,7 @@ static const struct elf_reloc_map riscv_reloc_map[] = =3D > { BFD_RELOC_RISCV_PCREL_HI20, R_RISCV_PCREL_HI20 }, > { BFD_RELOC_RISCV_JMP, R_RISCV_JAL }, > { BFD_RELOC_RISCV_GOT_HI20, R_RISCV_GOT_HI20 }, > + { BFD_RELOC_RISCV_GOT_HI20_RELAX, R_RISCV_GOT_HI20 }, > { BFD_RELOC_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD32 }, > { BFD_RELOC_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL32 }, > { BFD_RELOC_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPMOD64 }, > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 3b520ad208b..303ae18436c 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -2039,7 +2039,7 @@ macro (struct riscv_cl_insn *ip, expressionS > *imm_expr, > else if ((riscv_opts.pic && mask =3D=3D M_LA) > || mask =3D=3D M_LGA) > pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, > - BFD_RELOC_RISCV_GOT_HI20, > BFD_RELOC_RISCV_PCREL_LO12_I); > + BFD_RELOC_RISCV_GOT_HI20_RELAX, > BFD_RELOC_RISCV_PCREL_LO12_I); > /* Local PIC symbol, or any non-PIC symbol. */ > else > pcrel_load (rd, rd, imm_expr, "addi", > @@ -4244,6 +4244,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg > ATTRIBUTE_UNUSED) > relaxable =3D true; > break; > > + case BFD_RELOC_RISCV_GOT_HI20_RELAX: case BFD_RELOC_RISCV_PCREL_HI20: > case BFD_RELOC_RISCV_PCREL_LO12_S: > case BFD_RELOC_RISCV_PCREL_LO12_I: > In the gas/write.h, there is a special hook called tc_fix_data, which allows backends to attach their own data to the fixup structure. The fixup structure is used to represent the relocation in assembler. Therefore, I suggest that we should add a new flag in the tc_fix_data to represent the relocations which are expanded from the macro, setup the flag in the macro_build function, and then enable to attach the R_RISCV_RELAX for GOT_HI20 if it is expanded from the macro LA/LGA by checking that fag. The advantage of doing this is that we don't need to add a new special bfd relocation for the pseudo LA, and the similar usage in the future also will not need it. Thanks Nelson > diff --git a/gas/testsuite/gas/riscv/la-variants.d > b/gas/testsuite/gas/riscv/la-variants.d > index b1d316983b7..e8ac09c2af2 100644 > --- a/gas/testsuite/gas/riscv/la-variants.d > +++ b/gas/testsuite/gas/riscv/la-variants.d > @@ -21,11 +21,13 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+00000617[ ]+auipc[ ]+a2,0x0 > [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a > +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+(00062603|00063603)[ ]+(lw|ld)[ > ]+a2,0\(a2\).* > [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+00000697[ ]+auipc[ ]+a3,0x0 > [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a > +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+(0006a683|0006b683)[ ]+(lw|ld)[ > ]+a3,0\(a3\).* > [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > @@ -37,6 +39,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+00000797[ ]+auipc[ ]+a5,0x0 > [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a > +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+(0007a783|0007b783)[ ]+(lw|ld)[ > ]+a5,0\(a5\).* > [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > -- > 2.34.1 > > --0000000000006384dd0605c003f9--