* [PATCH 0/4] RISC-V: load/store macro insn handling adjustments
@ 2023-10-30 14:45 Jan Beulich
2023-10-30 14:46 ` [PATCH 1/4] RISC-V: make FLQ/FSQ macro-insns work Jan Beulich
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Jan Beulich @ 2023-10-30 14:45 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu
... plus, really, some bits previously missing from the testsuite.
1: make FLQ/FSQ macro-insns work
2: add F- and D-extension testcases
3: Lx/Sx macro insn tests
4: reduce redundancy in load/store macro insn handling
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] RISC-V: make FLQ/FSQ macro-insns work
2023-10-30 14:45 [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Jan Beulich
@ 2023-10-30 14:46 ` Jan Beulich
2023-10-30 14:46 ` [PATCH 2/4] RISC-V: add F- and D-extension testcases Jan Beulich
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2023-10-30 14:46 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu
When support for the Q extension was added, the libopcodes side of these
macro-insns was properly covered, but no backing support in gas was
added. In new testcases cover not just these, but all Q-extension insns.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2101,6 +2101,11 @@ macro (struct riscv_cl_insn *ip, express
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
+ case M_FLQ:
+ pcrel_load (rd, rs1, imm_expr, "flq",
+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+ break;
+
case M_SB:
pcrel_store (rs2, rs1, imm_expr, "sb",
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
@@ -2131,6 +2136,11 @@ macro (struct riscv_cl_insn *ip, express
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
break;
+ case M_FSQ:
+ pcrel_store (rs2, rs1, imm_expr, "fsq",
+ BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+ break;
+
case M_CALL:
riscv_call (rd, rs1, imm_expr, *imm_reloc);
break;
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-q-insns-32.d
@@ -0,0 +1,120 @@
+#as: -march=rv32iq
+#name: Q extension (32-bit)
+#objdump: -dwrMnumeric
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <Q>:
+[ ]+[0-9a-f]+:[ ]+26002fd3[ ]+fabs\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+27ffa053[ ]+fabs\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fd3[ ]+fadd\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff053[ ]+fadd\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+07f07053[ ]+fadd\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06000053[ ]+fadd\.q[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+06001053[ ]+fadd\.q[ ]+f0,f0,f0,rtz
+[ ]+[0-9a-f]+:[ ]+06002053[ ]+fadd\.q[ ]+f0,f0,f0,rdn
+[ ]+[0-9a-f]+:[ ]+06003053[ ]+fadd\.q[ ]+f0,f0,f0,rup
+[ ]+[0-9a-f]+:[ ]+06004053[ ]+fadd\.q[ ]+f0,f0,f0,rmm
+[ ]+[0-9a-f]+:[ ]+e6001fd3[ ]+fclass\.q[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e60f9053[ ]+fclass\.q[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+42307fd3[ ]+fcvt\.d\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+423ff053[ ]+fcvt\.d\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+42300053[ ]+fcvt\.d\.q[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+46100fd3[ ]+fcvt\.q\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+461f8053[ ]+fcvt\.q\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+46000fd3[ ]+fcvt\.q\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+460f8053[ ]+fcvt\.q\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+d6000fd3[ ]+fcvt\.q\.w[ ]+f31,x0
+[ ]+[0-9a-f]+:[ ]+d60f8053[ ]+fcvt\.q\.w[ ]+f0,x31
+[ ]+[0-9a-f]+:[ ]+d6100053[ ]+fcvt\.q\.wu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+40307fd3[ ]+fcvt\.s\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+403ff053[ ]+fcvt\.s\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+40300053[ ]+fcvt\.s\.q[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c6007fd3[ ]+fcvt\.w\.q[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+c60ff053[ ]+fcvt\.w\.q[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+c6000053[ ]+fcvt\.w\.q[ ]+x0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c6107053[ ]+fcvt\.wu\.q[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+1e007fd3[ ]+fdiv\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+1e0ff053[ ]+fdiv\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+1ff07053[ ]+fdiv\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+1e000053[ ]+fdiv\.q[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+a6002fd3[ ]+feq\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a60fa053[ ]+feq\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a7f02053[ ]+feq\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a6000fd3[ ]+fle\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a7f00053[ ]+fle\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a60f8053[ ]+fle\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a6001fd3[ ]+flt\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a7f01053[ ]+flt\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a60f9053[ ]+flt\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a6000fd3[ ]+fle\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a60f8053[ ]+fle\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a7f00053[ ]+fle\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00004f87[ ]+flq[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+7ff04007[ ]+flq[ ]+f0,2047\(x0\) # 7ff( <.*>)?
+[ ]+[0-9a-f]+:[ ]+80004007[ ]+flq[ ]+f0,-2048\(x0\) # fffff800( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fc007[ ]+flq[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+qvar
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fc007[ ]+flq[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+a6001fd3[ ]+flt\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a60f9053[ ]+flt\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a7f01053[ ]+flt\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fc3[ ]+fmadd\.q[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff043[ ]+fmadd\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f07043[ ]+fmadd\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe007043[ ]+fmadd\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06000043[ ]+fmadd\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+2e001fd3[ ]+fmax\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2e0f9053[ ]+fmax\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2ff01053[ ]+fmax\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+2e000fd3[ ]+fmin\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2e0f8053[ ]+fmin\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2ff00053[ ]+fmin\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fc7[ ]+fmsub\.q[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff047[ ]+fmsub\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f07047[ ]+fmsub\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe007047[ ]+fmsub\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06000047[ ]+fmsub\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+16007fd3[ ]+fmul\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+160ff053[ ]+fmul\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+17f07053[ ]+fmul\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+16000053[ ]+fmul\.q[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+26000fd3[ ]+fmv\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+27ff8053[ ]+fmv\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+26001fd3[ ]+fneg\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+27ff9053[ ]+fneg\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fcf[ ]+fnmadd\.q[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff04f[ ]+fnmadd\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f0704f[ ]+fnmadd\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe00704f[ ]+fnmadd\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0600004f[ ]+fnmadd\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+0600704b[ ]+fnmsub\.q[ ]+f0,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff04b[ ]+fnmsub\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f0704b[ ]+fnmsub\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe00704b[ ]+fnmsub\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0600004b[ ]+fnmsub\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+26100fd3[ ]+fsgnj\.q[ ]+f31,f0,f1
+[ ]+[0-9a-f]+:[ ]+260f8053[ ]+fsgnj\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+27f00053[ ]+fsgnj\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+26009053[ ]+fsgnjn\.q[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+2600a053[ ]+fsgnjx\.q[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+01f04027[ ]+fsq[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+00004fa7[ ]+fsq[ ]+f0,31\(x0\) # 1f( <.*>)?
+[ ]+[0-9a-f]+:[ ]+fe004027[ ]+fsq[ ]+f0,-32\(x0\) # ffffffe0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fc027[ ]+fsq[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+qvar
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fc027[ ]+fsq[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+5e007fd3[ ]+fsqrt\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+5e0ff053[ ]+fsqrt\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+5e000053[ ]+fsqrt\.q[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+0e007fd3[ ]+fsub\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+0e0ff053[ ]+fsub\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+0ff07053[ ]+fsub\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0e000053[ ]+fsub\.q[ ]+f0,f0,f0,rne
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-q-insns-32.s
@@ -0,0 +1,128 @@
+Q:
+ fabs.q f31, f0
+ fabs.q f0, f31
+
+ fadd.q f31, f0, f0
+ fadd.q f0, f31, f0
+ fadd.q f0, f0, f31
+ fadd.q f0, f0, f0, rne
+ fadd.q f0, f0, f0, rtz
+ fadd.q f0, f0, f0, rdn
+ fadd.q f0, f0, f0, rup
+ fadd.q f0, f0, f0, rmm
+
+ fclass.q x31, f0
+ fclass.q x0, f31
+
+ fcvt.d.q f31, f0
+ fcvt.d.q f0, f31
+ fcvt.d.q f0, f0, rne
+ fcvt.q.d f31, f0
+ fcvt.q.d f0, f31
+ fcvt.q.s f31, f0
+ fcvt.q.s f0, f31
+ fcvt.q.w f31, x0
+ fcvt.q.w f0, x31
+ fcvt.q.wu f0, x0
+ fcvt.s.q f31, f0
+ fcvt.s.q f0, f31
+ fcvt.s.q f0, f0, rne
+ fcvt.w.q x31, f0
+ fcvt.w.q x0, f31
+ fcvt.w.q x0, f0, rne
+ fcvt.wu.q x0, f0
+
+ fdiv.q f31, f0, f0
+ fdiv.q f0, f31, f0
+ fdiv.q f0, f0, f31
+ fdiv.q f0, f0, f0, rne
+
+ feq.q x31, f0, f0
+ feq.q x0, f31, f0
+ feq.q x0, f0, f31
+
+ fge.q x31, f0, f0
+ fge.q x0, f31, f0
+ fge.q x0, f0, f31
+
+ fgt.q x31, f0, f0
+ fgt.q x0, f31, f0
+ fgt.q x0, f0, f31
+
+ fle.q x31, f0, f0
+ fle.q x0, f31, f0
+ fle.q x0, f0, f31
+
+ flq f31, (x0)
+ flq f0, 0x7ff(x0)
+ flq f0, -0x800(x0)
+ flq f0, (x31)
+ flq f0, qvar, x31
+
+ flt.q x31, f0, f0
+ flt.q x0, f31, f0
+ flt.q x0, f0, f31
+
+ fmadd.q f31, f0, f0, f0
+ fmadd.q f0, f31, f0, f0
+ fmadd.q f0, f0, f31, f0
+ fmadd.q f0, f0, f0, f31
+ fmadd.q f0, f0, f0, f0, rne
+
+ fmax.q f31, f0, f0
+ fmax.q f0, f31, f0
+ fmax.q f0, f0, f31
+
+ fmin.q f31, f0, f0
+ fmin.q f0, f31, f0
+ fmin.q f0, f0, f31
+
+ fmsub.q f31, f0, f0, f0
+ fmsub.q f0, f31, f0, f0
+ fmsub.q f0, f0, f31, f0
+ fmsub.q f0, f0, f0, f31
+ fmsub.q f0, f0, f0, f0, rne
+
+ fmul.q f31, f0, f0
+ fmul.q f0, f31, f0
+ fmul.q f0, f0, f31
+ fmul.q f0, f0, f0, rne
+
+ fmv.q f31, f0
+ fmv.q f0, f31
+
+ fneg.q f31, f0
+ fneg.q f0, f31
+
+ fnmadd.q f31, f0, f0, f0
+ fnmadd.q f0, f31, f0, f0
+ fnmadd.q f0, f0, f31, f0
+ fnmadd.q f0, f0, f0, f31
+ fnmadd.q f0, f0, f0, f0, rne
+
+ fnmsub.q f0, f0, f0, f0
+ fnmsub.q f0, f31, f0, f0
+ fnmsub.q f0, f0, f31, f0
+ fnmsub.q f0, f0, f0, f31
+ fnmsub.q f0, f0, f0, f0, rne
+
+ fsgnj.q f31, f0, f1
+ fsgnj.q f0, f31, f0
+ fsgnj.q f0, f0, f31
+ fsgnjn.q f0, f1, f0
+ fsgnjx.q f0, f1, f0
+
+ fsq f31, (x0)
+ fsq f0, 0x1f(x0)
+ fsq f0, -0x20(x0)
+ fsq f0, (x31)
+ fsq f0, qvar, x31
+
+ fsqrt.q f31, f0
+ fsqrt.q f0, f31
+ fsqrt.q f0, f0, rne
+
+ fsub.q f31, f0, f0
+ fsub.q f0, f31, f0
+ fsub.q f0, f0, f31
+ fsub.q f0, f0, f0, rne
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-q-insns-64.d
@@ -0,0 +1,125 @@
+#as: -march=rv64iq
+#name: Q extension (64-bit)
+#objdump: -dwrMnumeric
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <Q>:
+[ ]+[0-9a-f]+:[ ]+26002fd3[ ]+fabs\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+27ffa053[ ]+fabs\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fd3[ ]+fadd\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff053[ ]+fadd\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+07f07053[ ]+fadd\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06000053[ ]+fadd\.q[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+06001053[ ]+fadd\.q[ ]+f0,f0,f0,rtz
+[ ]+[0-9a-f]+:[ ]+06002053[ ]+fadd\.q[ ]+f0,f0,f0,rdn
+[ ]+[0-9a-f]+:[ ]+06003053[ ]+fadd\.q[ ]+f0,f0,f0,rup
+[ ]+[0-9a-f]+:[ ]+06004053[ ]+fadd\.q[ ]+f0,f0,f0,rmm
+[ ]+[0-9a-f]+:[ ]+e6001fd3[ ]+fclass\.q[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e60f9053[ ]+fclass\.q[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+42307fd3[ ]+fcvt\.d\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+423ff053[ ]+fcvt\.d\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+42300053[ ]+fcvt\.d\.q[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c6207053[ ]+fcvt\.l\.q[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+c6200053[ ]+fcvt\.l\.q[ ]+x0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c6307053[ ]+fcvt\.lu\.q[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+46100fd3[ ]+fcvt\.q\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+461f8053[ ]+fcvt\.q\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+d6200053[ ]+fcvt\.q\.l[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+d6300053[ ]+fcvt\.q\.lu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+46000fd3[ ]+fcvt\.q\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+460f8053[ ]+fcvt\.q\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+d6000fd3[ ]+fcvt\.q\.w[ ]+f31,x0
+[ ]+[0-9a-f]+:[ ]+d60f8053[ ]+fcvt\.q\.w[ ]+f0,x31
+[ ]+[0-9a-f]+:[ ]+d6100053[ ]+fcvt\.q\.wu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+40307fd3[ ]+fcvt\.s\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+403ff053[ ]+fcvt\.s\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+40300053[ ]+fcvt\.s\.q[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c6007fd3[ ]+fcvt\.w\.q[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+c60ff053[ ]+fcvt\.w\.q[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+c6000053[ ]+fcvt\.w\.q[ ]+x0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c6107053[ ]+fcvt\.wu\.q[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+1e007fd3[ ]+fdiv\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+1e0ff053[ ]+fdiv\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+1ff07053[ ]+fdiv\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+1e000053[ ]+fdiv\.q[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+a6002fd3[ ]+feq\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a60fa053[ ]+feq\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a7f02053[ ]+feq\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a6000fd3[ ]+fle\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a7f00053[ ]+fle\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a60f8053[ ]+fle\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a6001fd3[ ]+flt\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a7f01053[ ]+flt\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a60f9053[ ]+flt\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a6000fd3[ ]+fle\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a60f8053[ ]+fle\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a7f00053[ ]+fle\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00004f87[ ]+flq[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+7ff04007[ ]+flq[ ]+f0,2047\(x0\) # 7ff( <.*>)?
+[ ]+[0-9a-f]+:[ ]+80004007[ ]+flq[ ]+f0,-2048\(x0\) # f+800( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fc007[ ]+flq[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+qvar
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fc007[ ]+flq[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+a6001fd3[ ]+flt\.q[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a60f9053[ ]+flt\.q[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a7f01053[ ]+flt\.q[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fc3[ ]+fmadd\.q[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff043[ ]+fmadd\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f07043[ ]+fmadd\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe007043[ ]+fmadd\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06000043[ ]+fmadd\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+2e001fd3[ ]+fmax\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2e0f9053[ ]+fmax\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2ff01053[ ]+fmax\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+2e000fd3[ ]+fmin\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2e0f8053[ ]+fmin\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2ff00053[ ]+fmin\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fc7[ ]+fmsub\.q[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff047[ ]+fmsub\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f07047[ ]+fmsub\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe007047[ ]+fmsub\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+06000047[ ]+fmsub\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+16007fd3[ ]+fmul\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+160ff053[ ]+fmul\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+17f07053[ ]+fmul\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+16000053[ ]+fmul\.q[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+26000fd3[ ]+fmv\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+27ff8053[ ]+fmv\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+26001fd3[ ]+fneg\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+27ff9053[ ]+fneg\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+06007fcf[ ]+fnmadd\.q[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff04f[ ]+fnmadd\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f0704f[ ]+fnmadd\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe00704f[ ]+fnmadd\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0600004f[ ]+fnmadd\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+0600704b[ ]+fnmsub\.q[ ]+f0,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+060ff04b[ ]+fnmsub\.q[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+07f0704b[ ]+fnmsub\.q[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fe00704b[ ]+fnmsub\.q[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0600004b[ ]+fnmsub\.q[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+26100fd3[ ]+fsgnj\.q[ ]+f31,f0,f1
+[ ]+[0-9a-f]+:[ ]+260f8053[ ]+fsgnj\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+27f00053[ ]+fsgnj\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+26009053[ ]+fsgnjn\.q[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+2600a053[ ]+fsgnjx\.q[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+01f04027[ ]+fsq[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+00004fa7[ ]+fsq[ ]+f0,31\(x0\) # 1f( <.*>)?
+[ ]+[0-9a-f]+:[ ]+fe004027[ ]+fsq[ ]+f0,-32\(x0\) # f+e0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fc027[ ]+fsq[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+qvar
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fc027[ ]+fsq[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+5e007fd3[ ]+fsqrt\.q[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+5e0ff053[ ]+fsqrt\.q[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+5e000053[ ]+fsqrt\.q[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+0e007fd3[ ]+fsub\.q[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+0e0ff053[ ]+fsub\.q[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+0ff07053[ ]+fsub\.q[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0e000053[ ]+fsub\.q[ ]+f0,f0,f0,rne
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-q-insns-64.s
@@ -0,0 +1,133 @@
+Q:
+ fabs.q f31, f0
+ fabs.q f0, f31
+
+ fadd.q f31, f0, f0
+ fadd.q f0, f31, f0
+ fadd.q f0, f0, f31
+ fadd.q f0, f0, f0, rne
+ fadd.q f0, f0, f0, rtz
+ fadd.q f0, f0, f0, rdn
+ fadd.q f0, f0, f0, rup
+ fadd.q f0, f0, f0, rmm
+
+ fclass.q x31, f0
+ fclass.q x0, f31
+
+ fcvt.d.q f31, f0
+ fcvt.d.q f0, f31
+ fcvt.d.q f0, f0, rne
+ fcvt.l.q x0, f0
+ fcvt.l.q x0, f0, rne
+ fcvt.lu.q x0, f0
+ fcvt.q.d f31, f0
+ fcvt.q.d f0, f31
+ fcvt.q.l f0, x0
+ fcvt.q.lu f0, x0
+ fcvt.q.s f31, f0
+ fcvt.q.s f0, f31
+ fcvt.q.w f31, x0
+ fcvt.q.w f0, x31
+ fcvt.q.wu f0, x0
+ fcvt.s.q f31, f0
+ fcvt.s.q f0, f31
+ fcvt.s.q f0, f0, rne
+ fcvt.w.q x31, f0
+ fcvt.w.q x0, f31
+ fcvt.w.q x0, f0, rne
+ fcvt.wu.q x0, f0
+
+ fdiv.q f31, f0, f0
+ fdiv.q f0, f31, f0
+ fdiv.q f0, f0, f31
+ fdiv.q f0, f0, f0, rne
+
+ feq.q x31, f0, f0
+ feq.q x0, f31, f0
+ feq.q x0, f0, f31
+
+ fge.q x31, f0, f0
+ fge.q x0, f31, f0
+ fge.q x0, f0, f31
+
+ fgt.q x31, f0, f0
+ fgt.q x0, f31, f0
+ fgt.q x0, f0, f31
+
+ fle.q x31, f0, f0
+ fle.q x0, f31, f0
+ fle.q x0, f0, f31
+
+ flq f31, (x0)
+ flq f0, 0x7ff(x0)
+ flq f0, -0x800(x0)
+ flq f0, (x31)
+ flq f0, qvar, x31
+
+ flt.q x31, f0, f0
+ flt.q x0, f31, f0
+ flt.q x0, f0, f31
+
+ fmadd.q f31, f0, f0, f0
+ fmadd.q f0, f31, f0, f0
+ fmadd.q f0, f0, f31, f0
+ fmadd.q f0, f0, f0, f31
+ fmadd.q f0, f0, f0, f0, rne
+
+ fmax.q f31, f0, f0
+ fmax.q f0, f31, f0
+ fmax.q f0, f0, f31
+
+ fmin.q f31, f0, f0
+ fmin.q f0, f31, f0
+ fmin.q f0, f0, f31
+
+ fmsub.q f31, f0, f0, f0
+ fmsub.q f0, f31, f0, f0
+ fmsub.q f0, f0, f31, f0
+ fmsub.q f0, f0, f0, f31
+ fmsub.q f0, f0, f0, f0, rne
+
+ fmul.q f31, f0, f0
+ fmul.q f0, f31, f0
+ fmul.q f0, f0, f31
+ fmul.q f0, f0, f0, rne
+
+ fmv.q f31, f0
+ fmv.q f0, f31
+
+ fneg.q f31, f0
+ fneg.q f0, f31
+
+ fnmadd.q f31, f0, f0, f0
+ fnmadd.q f0, f31, f0, f0
+ fnmadd.q f0, f0, f31, f0
+ fnmadd.q f0, f0, f0, f31
+ fnmadd.q f0, f0, f0, f0, rne
+
+ fnmsub.q f0, f0, f0, f0
+ fnmsub.q f0, f31, f0, f0
+ fnmsub.q f0, f0, f31, f0
+ fnmsub.q f0, f0, f0, f31
+ fnmsub.q f0, f0, f0, f0, rne
+
+ fsgnj.q f31, f0, f1
+ fsgnj.q f0, f31, f0
+ fsgnj.q f0, f0, f31
+ fsgnjn.q f0, f1, f0
+ fsgnjx.q f0, f1, f0
+
+ fsq f31, (x0)
+ fsq f0, 0x1f(x0)
+ fsq f0, -0x20(x0)
+ fsq f0, (x31)
+ fsq f0, qvar, x31
+
+ fsqrt.q f31, f0
+ fsqrt.q f0, f31
+ fsqrt.q f0, f0, rne
+
+ fsub.q f31, f0, f0
+ fsub.q f0, f31, f0
+ fsub.q f0, f0, f31
+ fsub.q f0, f0, f0, rne
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/4] RISC-V: add F- and D-extension testcases
2023-10-30 14:45 [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Jan Beulich
2023-10-30 14:46 ` [PATCH 1/4] RISC-V: make FLQ/FSQ macro-insns work Jan Beulich
@ 2023-10-30 14:46 ` Jan Beulich
2023-10-30 14:47 ` [PATCH 3/4] RISC-V: Lx/Sx macro insn tests Jan Beulich
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2023-10-30 14:46 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu
Make sure future changes won't regress any of this. Also cover the FLH
and FSH macro insns of the Zfh extension.
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-d-insns-32.d
@@ -0,0 +1,128 @@
+#as: -march=rv32icd
+#name: D extension (32-bit)
+#objdump: -dwrMnumeric
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <D>:
+[ ]+[0-9a-f]+:[ ]+22002fd3[ ]+fabs\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+23ffa053[ ]+fabs\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fd3[ ]+fadd\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff053[ ]+fadd\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+03f07053[ ]+fadd\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02000053[ ]+fadd\.d[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+02001053[ ]+fadd\.d[ ]+f0,f0,f0,rtz
+[ ]+[0-9a-f]+:[ ]+02002053[ ]+fadd\.d[ ]+f0,f0,f0,rdn
+[ ]+[0-9a-f]+:[ ]+02003053[ ]+fadd\.d[ ]+f0,f0,f0,rup
+[ ]+[0-9a-f]+:[ ]+02004053[ ]+fadd\.d[ ]+f0,f0,f0,rmm
+[ ]+[0-9a-f]+:[ ]+e2001fd3[ ]+fclass\.d[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e20f9053[ ]+fclass\.d[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+42000fd3[ ]+fcvt\.d\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+420f8053[ ]+fcvt\.d\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+d2000053[ ]+fcvt\.d\.w[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+d2100053[ ]+fcvt\.d\.wu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+40107fd3[ ]+fcvt\.s\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+401ff053[ ]+fcvt\.s\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+40100053[ ]+fcvt\.s\.d[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c2007053[ ]+fcvt\.w\.d[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+c2107053[ ]+fcvt\.wu\.d[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+1a007fd3[ ]+fdiv\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+1a0ff053[ ]+fdiv\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+1bf07053[ ]+fdiv\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+1a000053[ ]+fdiv\.d[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+a2002fd3[ ]+feq\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a20fa053[ ]+feq\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a3f02053[ ]+feq\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a2000fd3[ ]+fle\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a3f00053[ ]+fle\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a20f8053[ ]+fle\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a2001fd3[ ]+flt\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a3f01053[ ]+flt\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a20f9053[ ]+flt\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+00003f87[ ]+fld[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+7ff03007[ ]+fld[ ]+f0,2047\(x0\) # 7ff( <.*>)?
+[ ]+[0-9a-f]+:[ ]+80003007[ ]+fld[ ]+f0,-2048\(x0\) # fffff800( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fb007[ ]+fld[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+dval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fb007[ ]+fld[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+201c[ ]+fld[ ]+f15,0\(x8\)
+[ ]+[0-9a-f]+:[ ]+3c00[ ]+fld[ ]+f8,56\(x8\)
+[ ]+[0-9a-f]+:[ ]+2060[ ]+fld[ ]+f8,192\(x8\)
+[ ]+[0-9a-f]+:[ ]+2380[ ]+fld[ ]+f8,0\(x15\)
+[ ]+[0-9a-f]+:[ ]+2f82[ ]+fld[ ]+f31,0\(x2\)
+[ ]+[0-9a-f]+:[ ]+2062[ ]+fld[ ]+f0,24\(x2\)
+[ ]+[0-9a-f]+:[ ]+3002[ ]+fld[ ]+f0,32\(x2\)
+[ ]+[0-9a-f]+:[ ]+201e[ ]+fld[ ]+f0,448\(x2\)
+[ ]+[0-9a-f]+:[ ]+a2000fd3[ ]+fle\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a20f8053[ ]+fle\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a3f00053[ ]+fle\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a2001fd3[ ]+flt\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a20f9053[ ]+flt\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a3f01053[ ]+flt\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fc3[ ]+fmadd\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff043[ ]+fmadd\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f07043[ ]+fmadd\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa007043[ ]+fmadd\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02000043[ ]+fmadd\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+2a001fd3[ ]+fmax\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2a0f9053[ ]+fmax\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2bf01053[ ]+fmax\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+2a000fd3[ ]+fmin\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2a0f8053[ ]+fmin\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2bf00053[ ]+fmin\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fc7[ ]+fmsub\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff047[ ]+fmsub\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f07047[ ]+fmsub\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa007047[ ]+fmsub\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02000047[ ]+fmsub\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+12007fd3[ ]+fmul\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+120ff053[ ]+fmul\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+13f07053[ ]+fmul\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+12000053[ ]+fmul\.d[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+22000fd3[ ]+fmv\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+23ff8053[ ]+fmv\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+22001fd3[ ]+fneg\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+23ff9053[ ]+fneg\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fcf[ ]+fnmadd\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff04f[ ]+fnmadd\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f0704f[ ]+fnmadd\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa00704f[ ]+fnmadd\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0200004f[ ]+fnmadd\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+02007fcb[ ]+fnmsub\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff04b[ ]+fnmsub\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f0704b[ ]+fnmsub\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa00704b[ ]+fnmsub\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0200004b[ ]+fnmsub\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+01f03027[ ]+fsd[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+00003fa7[ ]+fsd[ ]+f0,31\(x0\) # 1f( <.*>)?
+[ ]+[0-9a-f]+:[ ]+fe003027[ ]+fsd[ ]+f0,-32\(x0\) # ffffffe0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fb027[ ]+fsd[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+dval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fb027[ ]+fsd[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+a01c[ ]+fsd[ ]+f15,0\(x8\)
+[ ]+[0-9a-f]+:[ ]+bc00[ ]+fsd[ ]+f8,56\(x8\)
+[ ]+[0-9a-f]+:[ ]+a060[ ]+fsd[ ]+f8,192\(x8\)
+[ ]+[0-9a-f]+:[ ]+a380[ ]+fsd[ ]+f8,0\(x15\)
+[ ]+[0-9a-f]+:[ ]+a07e[ ]+fsd[ ]+f31,0\(x2\)
+[ ]+[0-9a-f]+:[ ]+ac02[ ]+fsd[ ]+f0,24\(x2\)
+[ ]+[0-9a-f]+:[ ]+b002[ ]+fsd[ ]+f0,32\(x2\)
+[ ]+[0-9a-f]+:[ ]+a382[ ]+fsd[ ]+f0,448\(x2\)
+[ ]+[0-9a-f]+:[ ]+22100fd3[ ]+fsgnj\.d[ ]+f31,f0,f1
+[ ]+[0-9a-f]+:[ ]+220f8053[ ]+fsgnj\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+23f00053[ ]+fsgnj\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+22009053[ ]+fsgnjn\.d[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+2200a053[ ]+fsgnjx\.d[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+5a007fd3[ ]+fsqrt\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+5a0ff053[ ]+fsqrt\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+5a000053[ ]+fsqrt\.d[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+0a007fd3[ ]+fsub\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+0a0ff053[ ]+fsub\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+0bf07053[ ]+fsub\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0a000053[ ]+fsub\.d[ ]+f0,f0,f0,rne
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-d-insns-32.s
@@ -0,0 +1,140 @@
+D:
+ fabs.d f31, f0
+ fabs.d f0, f31
+
+ fadd.d f31, f0, f0
+ fadd.d f0, f31, f0
+ fadd.d f0, f0, f31
+ fadd.d f0, f0, f0, rne
+ fadd.d f0, f0, f0, rtz
+ fadd.d f0, f0, f0, rdn
+ fadd.d f0, f0, f0, rup
+ fadd.d f0, f0, f0, rmm
+
+ fclass.d x31, f0
+ fclass.d x0, f31
+
+ fcvt.d.s f31, f0
+ fcvt.d.s f0, f31
+ fcvt.d.w f0, x0
+ fcvt.d.wu f0, x0
+ fcvt.s.d f31, f0
+ fcvt.s.d f0, f31
+ fcvt.s.d f0, f0, rne
+ fcvt.w.d x0, f0
+ fcvt.wu.d x0, f0
+
+ fdiv.d f31, f0, f0
+ fdiv.d f0, f31, f0
+ fdiv.d f0, f0, f31
+ fdiv.d f0, f0, f0, rne
+
+ feq.d x31, f0, f0
+ feq.d x0, f31, f0
+ feq.d x0, f0, f31
+
+ fge.d x31, f0, f0
+ fge.d x0, f31, f0
+ fge.d x0, f0, f31
+
+ fgt.d x31, f0, f0
+ fgt.d x0, f31, f0
+ fgt.d x0, f0, f31
+
+ fld f31, (x0)
+ fld f0, 0x7ff(x0)
+ fld f0, -0x800(x0)
+ fld f0, (x31)
+ fld f0, dval, x31
+
+ fld f15, (x8)
+ fld f8, 0x38(x8)
+ fld f8, 0xc0(x8)
+ fld f8, (x15)
+
+ fld f31, (sp)
+ fld f0, 0x18(sp)
+ fld f0, 0x20(sp)
+ fld f0, 0x1c0(sp)
+
+ fle.d x31, f0, f0
+ fle.d x0, f31, f0
+ fle.d x0, f0, f31
+
+ flt.d x31, f0, f0
+ flt.d x0, f31, f0
+ flt.d x0, f0, f31
+
+ fmadd.d f31, f0, f0, f0
+ fmadd.d f0, f31, f0, f0
+ fmadd.d f0, f0, f31, f0
+ fmadd.d f0, f0, f0, f31
+ fmadd.d f0, f0, f0, f0, rne
+
+ fmax.d f31, f0, f0
+ fmax.d f0, f31, f0
+ fmax.d f0, f0, f31
+
+ fmin.d f31, f0, f0
+ fmin.d f0, f31, f0
+ fmin.d f0, f0, f31
+
+ fmsub.d f31, f0, f0, f0
+ fmsub.d f0, f31, f0, f0
+ fmsub.d f0, f0, f31, f0
+ fmsub.d f0, f0, f0, f31
+ fmsub.d f0, f0, f0, f0, rne
+
+ fmul.d f31, f0, f0
+ fmul.d f0, f31, f0
+ fmul.d f0, f0, f31
+ fmul.d f0, f0, f0, rne
+
+ fmv.d f31, f0
+ fmv.d f0, f31
+
+ fneg.d f31, f0
+ fneg.d f0, f31
+
+ fnmadd.d f31, f0, f0, f0
+ fnmadd.d f0, f31, f0, f0
+ fnmadd.d f0, f0, f31, f0
+ fnmadd.d f0, f0, f0, f31
+ fnmadd.d f0, f0, f0, f0, rne
+
+ fnmsub.d f31, f0, f0, f0
+ fnmsub.d f0, f31, f0, f0
+ fnmsub.d f0, f0, f31, f0
+ fnmsub.d f0, f0, f0, f31
+ fnmsub.d f0, f0, f0, f0, rne
+
+ fsd f31, (x0)
+ fsd f0, 0x1f(x0)
+ fsd f0, -0x20(x0)
+ fsd f0, (x31)
+ fsd f0, dval, x31
+
+ fsd f15, (x8)
+ fsd f8, 0x38(x8)
+ fsd f8, 0xc0(x8)
+ fsd f8, (x15)
+
+ fsd f31, (sp)
+ fsd f0, 0x18(sp)
+ fsd f0, 0x20(sp)
+ fsd f0, 0x1c0(sp)
+
+ fsgnj.d f31, f0, f1
+ fsgnj.d f0, f31, f0
+ fsgnj.d f0, f0, f31
+ fsgnjn.d f0, f1, f0
+ fsgnjx.d f0, f1, f0
+
+ fsqrt.d f31, f0
+ fsqrt.d f0, f31
+ fsqrt.d f0, f0, rne
+
+ fsub.d f31, f0, f0
+ fsub.d f0, f31, f0
+ fsub.d f0, f0, f31
+ fsub.d f0, f0, f0, rne
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-d-insns-64.d
@@ -0,0 +1,119 @@
+#as: -march=rv64id
+#name: D extension (64-bit)
+#objdump: -dwrMnumeric
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <D>:
+[ ]+[0-9a-f]+:[ ]+22002fd3[ ]+fabs\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+23ffa053[ ]+fabs\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fd3[ ]+fadd\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff053[ ]+fadd\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+03f07053[ ]+fadd\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02000053[ ]+fadd\.d[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+02001053[ ]+fadd\.d[ ]+f0,f0,f0,rtz
+[ ]+[0-9a-f]+:[ ]+02002053[ ]+fadd\.d[ ]+f0,f0,f0,rdn
+[ ]+[0-9a-f]+:[ ]+02003053[ ]+fadd\.d[ ]+f0,f0,f0,rup
+[ ]+[0-9a-f]+:[ ]+02004053[ ]+fadd\.d[ ]+f0,f0,f0,rmm
+[ ]+[0-9a-f]+:[ ]+e2001fd3[ ]+fclass\.d[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e20f9053[ ]+fclass\.d[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+d2207053[ ]+fcvt\.d\.l[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+d2200053[ ]+fcvt\.d\.l[ ]+f0,x0,rne
+[ ]+[0-9a-f]+:[ ]+d2307053[ ]+fcvt\.d\.lu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+42000fd3[ ]+fcvt\.d\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+420f8053[ ]+fcvt\.d\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+d2000053[ ]+fcvt\.d\.w[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+d2100053[ ]+fcvt\.d\.wu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+c2207053[ ]+fcvt\.l\.d[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+c2307053[ ]+fcvt\.lu\.d[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+40107fd3[ ]+fcvt\.s\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+401ff053[ ]+fcvt\.s\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+40100053[ ]+fcvt\.s\.d[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c2007053[ ]+fcvt\.w\.d[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+c2107053[ ]+fcvt\.wu\.d[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+1a007fd3[ ]+fdiv\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+1a0ff053[ ]+fdiv\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+1bf07053[ ]+fdiv\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+1a000053[ ]+fdiv\.d[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+a2002fd3[ ]+feq\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a20fa053[ ]+feq\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a3f02053[ ]+feq\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a2000fd3[ ]+fle\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a3f00053[ ]+fle\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a20f8053[ ]+fle\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a2001fd3[ ]+flt\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a3f01053[ ]+flt\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a20f9053[ ]+flt\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+00003f87[ ]+fld[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+7ff03007[ ]+fld[ ]+f0,2047\(x0\) # 7ff( <.*>)?
+[ ]+[0-9a-f]+:[ ]+80003007[ ]+fld[ ]+f0,-2048\(x0\) # f+800( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fb007[ ]+fld[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+dval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fb007[ ]+fld[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+a2000fd3[ ]+fle\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a20f8053[ ]+fle\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a3f00053[ ]+fle\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a2001fd3[ ]+flt\.d[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a20f9053[ ]+flt\.d[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a3f01053[ ]+flt\.d[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fc3[ ]+fmadd\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff043[ ]+fmadd\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f07043[ ]+fmadd\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa007043[ ]+fmadd\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02000043[ ]+fmadd\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+2a001fd3[ ]+fmax\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2a0f9053[ ]+fmax\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2bf01053[ ]+fmax\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+2a000fd3[ ]+fmin\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+2a0f8053[ ]+fmin\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+2bf00053[ ]+fmin\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fc7[ ]+fmsub\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff047[ ]+fmsub\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f07047[ ]+fmsub\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa007047[ ]+fmsub\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+02000047[ ]+fmsub\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+12007fd3[ ]+fmul\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+120ff053[ ]+fmul\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+13f07053[ ]+fmul\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+12000053[ ]+fmul\.d[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+22000fd3[ ]+fmv\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+23ff8053[ ]+fmv\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+f2000053[ ]+fmv\.d\.x[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+e2000053[ ]+fmv\.x\.d[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+22001fd3[ ]+fneg\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+23ff9053[ ]+fneg\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+02007fcf[ ]+fnmadd\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff04f[ ]+fnmadd\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f0704f[ ]+fnmadd\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa00704f[ ]+fnmadd\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0200004f[ ]+fnmadd\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+02007fcb[ ]+fnmsub\.d[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+020ff04b[ ]+fnmsub\.d[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+03f0704b[ ]+fnmsub\.d[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+fa00704b[ ]+fnmsub\.d[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0200004b[ ]+fnmsub\.d[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+01f03027[ ]+fsd[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+00003fa7[ ]+fsd[ ]+f0,31\(x0\) # 1f( <.*>)?
+[ ]+[0-9a-f]+:[ ]+fe003027[ ]+fsd[ ]+f0,-32\(x0\) # f+e0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fb027[ ]+fsd[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+dval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fb027[ ]+fsd[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+22100fd3[ ]+fsgnj\.d[ ]+f31,f0,f1
+[ ]+[0-9a-f]+:[ ]+220f8053[ ]+fsgnj\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+23f00053[ ]+fsgnj\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+22009053[ ]+fsgnjn\.d[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+2200a053[ ]+fsgnjx\.d[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+5a007fd3[ ]+fsqrt\.d[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+5a0ff053[ ]+fsqrt\.d[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+5a000053[ ]+fsqrt\.d[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+0a007fd3[ ]+fsub\.d[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+0a0ff053[ ]+fsub\.d[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+0bf07053[ ]+fsub\.d[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0a000053[ ]+fsub\.d[ ]+f0,f0,f0,rne
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-d-insns-64.s
@@ -0,0 +1,128 @@
+D:
+ fabs.d f31, f0
+ fabs.d f0, f31
+
+ fadd.d f31, f0, f0
+ fadd.d f0, f31, f0
+ fadd.d f0, f0, f31
+ fadd.d f0, f0, f0, rne
+ fadd.d f0, f0, f0, rtz
+ fadd.d f0, f0, f0, rdn
+ fadd.d f0, f0, f0, rup
+ fadd.d f0, f0, f0, rmm
+
+ fclass.d x31, f0
+ fclass.d x0, f31
+
+ fcvt.d.l f0, x0
+ fcvt.d.l f0, x0, rne
+ fcvt.d.lu f0, x0
+ fcvt.d.s f31, f0
+ fcvt.d.s f0, f31
+ fcvt.d.w f0, x0
+ fcvt.d.wu f0, x0
+ fcvt.l.d x0, f0
+ fcvt.lu.d x0, f0
+ fcvt.s.d f31, f0
+ fcvt.s.d f0, f31
+ fcvt.s.d f0, f0, rne
+ fcvt.w.d x0, f0
+ fcvt.wu.d x0, f0
+
+ fdiv.d f31, f0, f0
+ fdiv.d f0, f31, f0
+ fdiv.d f0, f0, f31
+ fdiv.d f0, f0, f0, rne
+
+ feq.d x31, f0, f0
+ feq.d x0, f31, f0
+ feq.d x0, f0, f31
+
+ fge.d x31, f0, f0
+ fge.d x0, f31, f0
+ fge.d x0, f0, f31
+
+ fgt.d x31, f0, f0
+ fgt.d x0, f31, f0
+ fgt.d x0, f0, f31
+
+ fld f31, (x0)
+ fld f0, 0x7ff(x0)
+ fld f0, -0x800(x0)
+ fld f0, (x31)
+ fld f0, dval, x31
+
+ fle.d x31, f0, f0
+ fle.d x0, f31, f0
+ fle.d x0, f0, f31
+
+ flt.d x31, f0, f0
+ flt.d x0, f31, f0
+ flt.d x0, f0, f31
+
+ fmadd.d f31, f0, f0, f0
+ fmadd.d f0, f31, f0, f0
+ fmadd.d f0, f0, f31, f0
+ fmadd.d f0, f0, f0, f31
+ fmadd.d f0, f0, f0, f0, rne
+
+ fmax.d f31, f0, f0
+ fmax.d f0, f31, f0
+ fmax.d f0, f0, f31
+
+ fmin.d f31, f0, f0
+ fmin.d f0, f31, f0
+ fmin.d f0, f0, f31
+
+ fmsub.d f31, f0, f0, f0
+ fmsub.d f0, f31, f0, f0
+ fmsub.d f0, f0, f31, f0
+ fmsub.d f0, f0, f0, f31
+ fmsub.d f0, f0, f0, f0, rne
+
+ fmul.d f31, f0, f0
+ fmul.d f0, f31, f0
+ fmul.d f0, f0, f31
+ fmul.d f0, f0, f0, rne
+
+ fmv.d f31, f0
+ fmv.d f0, f31
+
+ fmv.d.x f0, x0
+ fmv.x.d x0, f0
+
+ fneg.d f31, f0
+ fneg.d f0, f31
+
+ fnmadd.d f31, f0, f0, f0
+ fnmadd.d f0, f31, f0, f0
+ fnmadd.d f0, f0, f31, f0
+ fnmadd.d f0, f0, f0, f31
+ fnmadd.d f0, f0, f0, f0, rne
+
+ fnmsub.d f31, f0, f0, f0
+ fnmsub.d f0, f31, f0, f0
+ fnmsub.d f0, f0, f31, f0
+ fnmsub.d f0, f0, f0, f31
+ fnmsub.d f0, f0, f0, f0, rne
+
+ fsd f31, (x0)
+ fsd f0, 0x1f(x0)
+ fsd f0, -0x20(x0)
+ fsd f0, (x31)
+ fsd f0, dval, x31
+
+ fsgnj.d f31, f0, f1
+ fsgnj.d f0, f31, f0
+ fsgnj.d f0, f0, f31
+ fsgnjn.d f0, f1, f0
+ fsgnjx.d f0, f1, f0
+
+ fsqrt.d f31, f0
+ fsqrt.d f0, f31
+ fsqrt.d f0, f0, rne
+
+ fsub.d f31, f0, f0
+ fsub.d f0, f31, f0
+ fsub.d f0, f0, f31
+ fsub.d f0, f0, f0, rne
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-f-insns-32.d
@@ -0,0 +1,145 @@
+#as: -march=rv32icf
+#name: F extension (32-bit)
+#objdump: -dwrMnumeric
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <F>:
+[ ]+[0-9a-f]+:[ ]+20002fd3[ ]+fabs\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+21ffa053[ ]+fabs\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+00007fd3[ ]+fadd\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff053[ ]+fadd\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+01f07053[ ]+fadd\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00000053[ ]+fadd\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+00001053[ ]+fadd\.s[ ]+f0,f0,f0,rtz
+[ ]+[0-9a-f]+:[ ]+00002053[ ]+fadd\.s[ ]+f0,f0,f0,rdn
+[ ]+[0-9a-f]+:[ ]+00003053[ ]+fadd\.s[ ]+f0,f0,f0,rup
+[ ]+[0-9a-f]+:[ ]+00004053[ ]+fadd\.s[ ]+f0,f0,f0,rmm
+[ ]+[0-9a-f]+:[ ]+e0001fd3[ ]+fclass\.s[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e00f9053[ ]+fclass\.s[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+d0007fd3[ ]+fcvt\.s\.w[ ]+f31,x0
+[ ]+[0-9a-f]+:[ ]+d00ff053[ ]+fcvt\.s\.w[ ]+f0,x31
+[ ]+[0-9a-f]+:[ ]+d0000053[ ]+fcvt\.s\.w[ ]+f0,x0,rne
+[ ]+[0-9a-f]+:[ ]+d0107053[ ]+fcvt\.s\.wu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+c0007fd3[ ]+fcvt\.w\.s[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+c00ff053[ ]+fcvt\.w\.s[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+c0000053[ ]+fcvt\.w\.s[ ]+x0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c0107053[ ]+fcvt\.wu\.s[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+18007fd3[ ]+fdiv\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+180ff053[ ]+fdiv\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+19f07053[ ]+fdiv\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+18000053[ ]+fdiv\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+a0002fd3[ ]+feq\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a00fa053[ ]+feq\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a1f02053[ ]+feq\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a0000fd3[ ]+fle\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a1f00053[ ]+fle\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a00f8053[ ]+fle\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a0001fd3[ ]+flt\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a1f01053[ ]+flt\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a00f9053[ ]+flt\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a0000fd3[ ]+fle\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a00f8053[ ]+fle\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a1f00053[ ]+fle\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a0001fd3[ ]+flt\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a00f9053[ ]+flt\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a1f01053[ ]+flt\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00002f87[ ]+flw[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+7ff02007[ ]+flw[ ]+f0,2047\(x0\) # 7ff( <.*>)?
+[ ]+[0-9a-f]+:[ ]+80002007[ ]+flw[ ]+f0,-2048\(x0\) # fffff800( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fa007[ ]+flw[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+sval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fa007[ ]+flw[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+601c[ ]+flw[ ]+f15,0\(x8\)
+[ ]+[0-9a-f]+:[ ]+6040[ ]+flw[ ]+f8,4\(x8\)
+[ ]+[0-9a-f]+:[ ]+7c00[ ]+flw[ ]+f8,56\(x8\)
+[ ]+[0-9a-f]+:[ ]+6020[ ]+flw[ ]+f8,64\(x8\)
+[ ]+[0-9a-f]+:[ ]+6380[ ]+flw[ ]+f8,0\(x15\)
+[ ]+[0-9a-f]+:[ ]+6f82[ ]+flw[ ]+f31,0\(x2\)
+[ ]+[0-9a-f]+:[ ]+6072[ ]+flw[ ]+f0,28\(x2\)
+[ ]+[0-9a-f]+:[ ]+7002[ ]+flw[ ]+f0,32\(x2\)
+[ ]+[0-9a-f]+:[ ]+600e[ ]+flw[ ]+f0,192\(x2\)
+[ ]+[0-9a-f]+:[ ]+00007fc3[ ]+fmadd\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff043[ ]+fmadd\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f07043[ ]+fmadd\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f8007043[ ]+fmadd\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00000043[ ]+fmadd\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+28001fd3[ ]+fmax\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+280f9053[ ]+fmax\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+29f01053[ ]+fmax\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+28000fd3[ ]+fmin\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+280f8053[ ]+fmin\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+29f00053[ ]+fmin\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00007fc7[ ]+fmsub\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff047[ ]+fmsub\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f07047[ ]+fmsub\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f8007047[ ]+fmsub\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00000047[ ]+fmsub\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+10007fd3[ ]+fmul\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+100ff053[ ]+fmul\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+11f07053[ ]+fmul\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+10000053[ ]+fmul\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+20000fd3[ ]+fmv\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+21ff8053[ ]+fmv\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+f0000fd3[ ]+fmv\.w\.x[ ]+f31,x0
+[ ]+[0-9a-f]+:[ ]+f00f8053[ ]+fmv\.w\.x[ ]+f0,x31
+[ ]+[0-9a-f]+:[ ]+e0000fd3[ ]+fmv\.x\.w[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e00f8053[ ]+fmv\.x\.w[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+20001fd3[ ]+fneg\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+21ff9053[ ]+fneg\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+00007fcf[ ]+fnmadd\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff04f[ ]+fnmadd\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f0704f[ ]+fnmadd\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f800704f[ ]+fnmadd\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0000004f[ ]+fnmadd\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+00007fcb[ ]+fnmsub\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff04b[ ]+fnmsub\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f0704b[ ]+fnmsub\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f800704b[ ]+fnmsub\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0000004b[ ]+fnmsub\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+00302ff3[ ]+frcsr[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00102ff3[ ]+frflags[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00202ff3[ ]+frrm[ ]+x31
+[ ]+[0-9a-f]+:[ ]+003f9073[ ]+fscsr[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00309ff3[ ]+fscsr[ ]+x31,x1
+[ ]+[0-9a-f]+:[ ]+003f90f3[ ]+fscsr[ ]+x1,x31
+[ ]+[0-9a-f]+:[ ]+001f9073[ ]+fsflags[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00109ff3[ ]+fsflags[ ]+x31,x1
+[ ]+[0-9a-f]+:[ ]+001f90f3[ ]+fsflags[ ]+x1,x31
+[ ]+[0-9a-f]+:[ ]+20100fd3[ ]+fsgnj\.s[ ]+f31,f0,f1
+[ ]+[0-9a-f]+:[ ]+200f8053[ ]+fsgnj\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+21f00053[ ]+fsgnj\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+20009053[ ]+fsgnjn\.s[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+2000a053[ ]+fsgnjx\.s[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+58007fd3[ ]+fsqrt\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+580ff053[ ]+fsqrt\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+58000053[ ]+fsqrt\.s[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+002f9073[ ]+fsrm[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00209ff3[ ]+fsrm[ ]+x31,x1
+[ ]+[0-9a-f]+:[ ]+002f90f3[ ]+fsrm[ ]+x1,x31
+[ ]+[0-9a-f]+:[ ]+08007fd3[ ]+fsub\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+080ff053[ ]+fsub\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+09f07053[ ]+fsub\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+08000053[ ]+fsub\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+01f02027[ ]+fsw[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+00002fa7[ ]+fsw[ ]+f0,31\(x0\) # 1f( <.*>)?
+[ ]+[0-9a-f]+:[ ]+fe002027[ ]+fsw[ ]+f0,-32\(x0\) # ffffffe0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fa027[ ]+fsw[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+sval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fa027[ ]+fsw[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+e01c[ ]+fsw[ ]+f15,0\(x8\)
+[ ]+[0-9a-f]+:[ ]+e040[ ]+fsw[ ]+f8,4\(x8\)
+[ ]+[0-9a-f]+:[ ]+fc00[ ]+fsw[ ]+f8,56\(x8\)
+[ ]+[0-9a-f]+:[ ]+e020[ ]+fsw[ ]+f8,64\(x8\)
+[ ]+[0-9a-f]+:[ ]+e380[ ]+fsw[ ]+f8,0\(x15\)
+[ ]+[0-9a-f]+:[ ]+e07e[ ]+fsw[ ]+f31,0\(x2\)
+[ ]+[0-9a-f]+:[ ]+ee02[ ]+fsw[ ]+f0,28\(x2\)
+[ ]+[0-9a-f]+:[ ]+f002[ ]+fsw[ ]+f0,32\(x2\)
+[ ]+[0-9a-f]+:[ ]+e182[ ]+fsw[ ]+f0,192\(x2\)
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-f-insns-32.s
@@ -0,0 +1,162 @@
+F:
+ fabs.s f31, f0
+ fabs.s f0, f31
+
+ fadd.s f31, f0, f0
+ fadd.s f0, f31, f0
+ fadd.s f0, f0, f31
+ fadd.s f0, f0, f0, rne
+ fadd.s f0, f0, f0, rtz
+ fadd.s f0, f0, f0, rdn
+ fadd.s f0, f0, f0, rup
+ fadd.s f0, f0, f0, rmm
+
+ fclass.s x31, f0
+ fclass.s x0, f31
+
+ fcvt.s.w f31, x0
+ fcvt.s.w f0, x31
+ fcvt.s.w f0, x0, rne
+ fcvt.s.wu f0, x0
+ fcvt.w.s x31, f0
+ fcvt.w.s x0, f31
+ fcvt.w.s x0, f0, rne
+ fcvt.wu.s x0, f0
+
+ fdiv.s f31, f0, f0
+ fdiv.s f0, f31, f0
+ fdiv.s f0, f0, f31
+ fdiv.s f0, f0, f0, rne
+
+ feq.s x31, f0, f0
+ feq.s x0, f31, f0
+ feq.s x0, f0, f31
+
+ fge.s x31, f0, f0
+ fge.s x0, f31, f0
+ fge.s x0, f0, f31
+
+ fgt.s x31, f0, f0
+ fgt.s x0, f31, f0
+ fgt.s x0, f0, f31
+
+ fle.s x31, f0, f0
+ fle.s x0, f31, f0
+ fle.s x0, f0, f31
+
+ flt.s x31, f0, f0
+ flt.s x0, f31, f0
+ flt.s x0, f0, f31
+
+ flw f31, (x0)
+ flw f0, 0x7ff(x0)
+ flw f0, -0x800(x0)
+ flw f0, (x31)
+ flw f0, sval, x31
+
+ flw f15, (x8)
+ flw f8, 4(x8)
+ flw f8, 0x38(x8)
+ flw f8, 0x40(x8)
+ flw f8, (x15)
+
+ flw f31, (sp)
+ flw f0, 0x1c(sp)
+ flw f0, 0x20(sp)
+ flw f0, 0xc0(sp)
+
+ fmadd.s f31, f0, f0, f0
+ fmadd.s f0, f31, f0, f0
+ fmadd.s f0, f0, f31, f0
+ fmadd.s f0, f0, f0, f31
+ fmadd.s f0, f0, f0, f0, rne
+
+ fmax.s f31, f0, f0
+ fmax.s f0, f31, f0
+ fmax.s f0, f0, f31
+
+ fmin.s f31, f0, f0
+ fmin.s f0, f31, f0
+ fmin.s f0, f0, f31
+
+ fmsub.s f31, f0, f0, f0
+ fmsub.s f0, f31, f0, f0
+ fmsub.s f0, f0, f31, f0
+ fmsub.s f0, f0, f0, f31
+ fmsub.s f0, f0, f0, f0, rne
+
+ fmul.s f31, f0, f0
+ fmul.s f0, f31, f0
+ fmul.s f0, f0, f31
+ fmul.s f0, f0, f0, rne
+
+ fmv.s f31, f0
+ fmv.s f0, f31
+
+ fmv.s.x f31, x0
+ fmv.s.x f0, x31
+ fmv.x.s x31, f0
+ fmv.x.s x0, f31
+
+ fneg.s f31, f0
+ fneg.s f0, f31
+
+ fnmadd.s f31, f0, f0, f0
+ fnmadd.s f0, f31, f0, f0
+ fnmadd.s f0, f0, f31, f0
+ fnmadd.s f0, f0, f0, f31
+ fnmadd.s f0, f0, f0, f0, rne
+
+ fnmsub.s f31, f0, f0, f0
+ fnmsub.s f0, f31, f0, f0
+ fnmsub.s f0, f0, f31, f0
+ fnmsub.s f0, f0, f0, f31
+ fnmsub.s f0, f0, f0, f0, rne
+
+ frcsr x31
+ frflags x31
+ frrm x31
+
+ fscsr x31
+ fscsr x31, x1
+ fscsr x1, x31
+
+ fsflags x31
+ fsflags x31, x1
+ fsflags x1, x31
+
+ fsgnj.s f31, f0, f1
+ fsgnj.s f0, f31, f0
+ fsgnj.s f0, f0, f31
+ fsgnjn.s f0, f1, f0
+ fsgnjx.s f0, f1, f0
+
+ fsqrt.s f31, f0
+ fsqrt.s f0, f31
+ fsqrt.s f0, f0, rne
+
+ fsrm x31
+ fsrm x31, x1
+ fsrm x1, x31
+
+ fsub.s f31, f0, f0
+ fsub.s f0, f31, f0
+ fsub.s f0, f0, f31
+ fsub.s f0, f0, f0, rne
+
+ fsw f31, (x0)
+ fsw f0, 0x1f(x0)
+ fsw f0, -0x20(x0)
+ fsw f0, (x31)
+ fsw f0, sval, x31
+
+ fsw f15, (x8)
+ fsw f8, 4(x8)
+ fsw f8, 0x38(x8)
+ fsw f8, 0x40(x8)
+ fsw f8, (x15)
+
+ fsw f31, (sp)
+ fsw f0, 0x1c(sp)
+ fsw f0, 0x20(sp)
+ fsw f0, 0xc0(sp)
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-f-insns-64.d
@@ -0,0 +1,131 @@
+#as: -march=rv64if
+#name: F extension (64-bit)
+#objdump: -dwrMnumeric
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <F>:
+[ ]+[0-9a-f]+:[ ]+20002fd3[ ]+fabs\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+21ffa053[ ]+fabs\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+00007fd3[ ]+fadd\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff053[ ]+fadd\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+01f07053[ ]+fadd\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00000053[ ]+fadd\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+00001053[ ]+fadd\.s[ ]+f0,f0,f0,rtz
+[ ]+[0-9a-f]+:[ ]+00002053[ ]+fadd\.s[ ]+f0,f0,f0,rdn
+[ ]+[0-9a-f]+:[ ]+00003053[ ]+fadd\.s[ ]+f0,f0,f0,rup
+[ ]+[0-9a-f]+:[ ]+00004053[ ]+fadd\.s[ ]+f0,f0,f0,rmm
+[ ]+[0-9a-f]+:[ ]+e0001fd3[ ]+fclass\.s[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e00f9053[ ]+fclass\.s[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+c0207053[ ]+fcvt\.l\.s[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+c0307053[ ]+fcvt\.lu\.s[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+d0207053[ ]+fcvt\.s\.l[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+d0307053[ ]+fcvt\.s\.lu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+d0007fd3[ ]+fcvt\.s\.w[ ]+f31,x0
+[ ]+[0-9a-f]+:[ ]+d00ff053[ ]+fcvt\.s\.w[ ]+f0,x31
+[ ]+[0-9a-f]+:[ ]+d0000053[ ]+fcvt\.s\.w[ ]+f0,x0,rne
+[ ]+[0-9a-f]+:[ ]+d0107053[ ]+fcvt\.s\.wu[ ]+f0,x0
+[ ]+[0-9a-f]+:[ ]+c0007fd3[ ]+fcvt\.w\.s[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+c00ff053[ ]+fcvt\.w\.s[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+c0000053[ ]+fcvt\.w\.s[ ]+x0,f0,rne
+[ ]+[0-9a-f]+:[ ]+c0107053[ ]+fcvt\.wu\.s[ ]+x0,f0
+[ ]+[0-9a-f]+:[ ]+18007fd3[ ]+fdiv\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+180ff053[ ]+fdiv\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+19f07053[ ]+fdiv\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+18000053[ ]+fdiv\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+a0002fd3[ ]+feq\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a00fa053[ ]+feq\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a1f02053[ ]+feq\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a0000fd3[ ]+fle\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a1f00053[ ]+fle\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a00f8053[ ]+fle\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a0001fd3[ ]+flt\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a1f01053[ ]+flt\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a00f9053[ ]+flt\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a0000fd3[ ]+fle\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a00f8053[ ]+fle\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a1f00053[ ]+fle\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+a0001fd3[ ]+flt\.s[ ]+x31,f0,f0
+[ ]+[0-9a-f]+:[ ]+a00f9053[ ]+flt\.s[ ]+x0,f31,f0
+[ ]+[0-9a-f]+:[ ]+a1f01053[ ]+flt\.s[ ]+x0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00002f87[ ]+flw[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+7ff02007[ ]+flw[ ]+f0,2047\(x0\) # 7ff( <.*>)?
+[ ]+[0-9a-f]+:[ ]+80002007[ ]+flw[ ]+f0,-2048\(x0\) # f+800( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fa007[ ]+flw[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+sval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fa007[ ]+flw[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00007fc3[ ]+fmadd\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff043[ ]+fmadd\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f07043[ ]+fmadd\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f8007043[ ]+fmadd\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00000043[ ]+fmadd\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+28001fd3[ ]+fmax\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+280f9053[ ]+fmax\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+29f01053[ ]+fmax\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+28000fd3[ ]+fmin\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+280f8053[ ]+fmin\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+29f00053[ ]+fmin\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00007fc7[ ]+fmsub\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff047[ ]+fmsub\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f07047[ ]+fmsub\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f8007047[ ]+fmsub\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+00000047[ ]+fmsub\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+10007fd3[ ]+fmul\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+100ff053[ ]+fmul\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+11f07053[ ]+fmul\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+10000053[ ]+fmul\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+20000fd3[ ]+fmv\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+21ff8053[ ]+fmv\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+f0000fd3[ ]+fmv\.w\.x[ ]+f31,x0
+[ ]+[0-9a-f]+:[ ]+f00f8053[ ]+fmv\.w\.x[ ]+f0,x31
+[ ]+[0-9a-f]+:[ ]+e0000fd3[ ]+fmv\.x\.w[ ]+x31,f0
+[ ]+[0-9a-f]+:[ ]+e00f8053[ ]+fmv\.x\.w[ ]+x0,f31
+[ ]+[0-9a-f]+:[ ]+20001fd3[ ]+fneg\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+21ff9053[ ]+fneg\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+00007fcf[ ]+fnmadd\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff04f[ ]+fnmadd\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f0704f[ ]+fnmadd\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f800704f[ ]+fnmadd\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0000004f[ ]+fnmadd\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+00007fcb[ ]+fnmsub\.s[ ]+f31,f0,f0,f0
+[ ]+[0-9a-f]+:[ ]+000ff04b[ ]+fnmsub\.s[ ]+f0,f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+01f0704b[ ]+fnmsub\.s[ ]+f0,f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+f800704b[ ]+fnmsub\.s[ ]+f0,f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+0000004b[ ]+fnmsub\.s[ ]+f0,f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+00302ff3[ ]+frcsr[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00102ff3[ ]+frflags[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00202ff3[ ]+frrm[ ]+x31
+[ ]+[0-9a-f]+:[ ]+003f9073[ ]+fscsr[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00309ff3[ ]+fscsr[ ]+x31,x1
+[ ]+[0-9a-f]+:[ ]+003f90f3[ ]+fscsr[ ]+x1,x31
+[ ]+[0-9a-f]+:[ ]+001f9073[ ]+fsflags[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00109ff3[ ]+fsflags[ ]+x31,x1
+[ ]+[0-9a-f]+:[ ]+001f90f3[ ]+fsflags[ ]+x1,x31
+[ ]+[0-9a-f]+:[ ]+20100fd3[ ]+fsgnj\.s[ ]+f31,f0,f1
+[ ]+[0-9a-f]+:[ ]+200f8053[ ]+fsgnj\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+21f00053[ ]+fsgnj\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+20009053[ ]+fsgnjn\.s[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+2000a053[ ]+fsgnjx\.s[ ]+f0,f1,f0
+[ ]+[0-9a-f]+:[ ]+58007fd3[ ]+fsqrt\.s[ ]+f31,f0
+[ ]+[0-9a-f]+:[ ]+580ff053[ ]+fsqrt\.s[ ]+f0,f31
+[ ]+[0-9a-f]+:[ ]+58000053[ ]+fsqrt\.s[ ]+f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+002f9073[ ]+fsrm[ ]+x31
+[ ]+[0-9a-f]+:[ ]+00209ff3[ ]+fsrm[ ]+x31,x1
+[ ]+[0-9a-f]+:[ ]+002f90f3[ ]+fsrm[ ]+x1,x31
+[ ]+[0-9a-f]+:[ ]+08007fd3[ ]+fsub\.s[ ]+f31,f0,f0
+[ ]+[0-9a-f]+:[ ]+080ff053[ ]+fsub\.s[ ]+f0,f31,f0
+[ ]+[0-9a-f]+:[ ]+09f07053[ ]+fsub\.s[ ]+f0,f0,f31
+[ ]+[0-9a-f]+:[ ]+08000053[ ]+fsub\.s[ ]+f0,f0,f0,rne
+[ ]+[0-9a-f]+:[ ]+01f02027[ ]+fsw[ ]+f31,0\(x0\) # 0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+00002fa7[ ]+fsw[ ]+f0,31\(x0\) # 1f( <.*>)?
+[ ]+[0-9a-f]+:[ ]+fe002027[ ]+fsw[ ]+f0,-32\(x0\) # f+e0( <.*>)?
+[ ]+[0-9a-f]+:[ ]+000fa027[ ]+fsw[ ]+f0,0\(x31\)
+[ ]+[0-9a-f]+:[ ]+00000f97[ ]+auipc[ ]+x31,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+sval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+000fa027[ ]+fsw[ ]+f0,0\(x31\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fp-f-insns-64.s
@@ -0,0 +1,144 @@
+F:
+ fabs.s f31, f0
+ fabs.s f0, f31
+
+ fadd.s f31, f0, f0
+ fadd.s f0, f31, f0
+ fadd.s f0, f0, f31
+ fadd.s f0, f0, f0, rne
+ fadd.s f0, f0, f0, rtz
+ fadd.s f0, f0, f0, rdn
+ fadd.s f0, f0, f0, rup
+ fadd.s f0, f0, f0, rmm
+
+ fclass.s x31, f0
+ fclass.s x0, f31
+
+ fcvt.l.s x0, f0
+ fcvt.lu.s x0, f0
+ fcvt.s.l f0, x0
+ fcvt.s.lu f0, x0
+ fcvt.s.w f31, x0
+ fcvt.s.w f0, x31
+ fcvt.s.w f0, x0, rne
+ fcvt.s.wu f0, x0
+ fcvt.w.s x31, f0
+ fcvt.w.s x0, f31
+ fcvt.w.s x0, f0, rne
+ fcvt.wu.s x0, f0
+
+ fdiv.s f31, f0, f0
+ fdiv.s f0, f31, f0
+ fdiv.s f0, f0, f31
+ fdiv.s f0, f0, f0, rne
+
+ feq.s x31, f0, f0
+ feq.s x0, f31, f0
+ feq.s x0, f0, f31
+
+ fge.s x31, f0, f0
+ fge.s x0, f31, f0
+ fge.s x0, f0, f31
+
+ fgt.s x31, f0, f0
+ fgt.s x0, f31, f0
+ fgt.s x0, f0, f31
+
+ fle.s x31, f0, f0
+ fle.s x0, f31, f0
+ fle.s x0, f0, f31
+
+ flt.s x31, f0, f0
+ flt.s x0, f31, f0
+ flt.s x0, f0, f31
+
+ flw f31, (x0)
+ flw f0, 0x7ff(x0)
+ flw f0, -0x800(x0)
+ flw f0, (x31)
+ flw f0, sval, x31
+
+ fmadd.s f31, f0, f0, f0
+ fmadd.s f0, f31, f0, f0
+ fmadd.s f0, f0, f31, f0
+ fmadd.s f0, f0, f0, f31
+ fmadd.s f0, f0, f0, f0, rne
+
+ fmax.s f31, f0, f0
+ fmax.s f0, f31, f0
+ fmax.s f0, f0, f31
+
+ fmin.s f31, f0, f0
+ fmin.s f0, f31, f0
+ fmin.s f0, f0, f31
+
+ fmsub.s f31, f0, f0, f0
+ fmsub.s f0, f31, f0, f0
+ fmsub.s f0, f0, f31, f0
+ fmsub.s f0, f0, f0, f31
+ fmsub.s f0, f0, f0, f0, rne
+
+ fmul.s f31, f0, f0
+ fmul.s f0, f31, f0
+ fmul.s f0, f0, f31
+ fmul.s f0, f0, f0, rne
+
+ fmv.s f31, f0
+ fmv.s f0, f31
+
+ fmv.s.x f31, x0
+ fmv.s.x f0, x31
+ fmv.x.s x31, f0
+ fmv.x.s x0, f31
+
+ fneg.s f31, f0
+ fneg.s f0, f31
+
+ fnmadd.s f31, f0, f0, f0
+ fnmadd.s f0, f31, f0, f0
+ fnmadd.s f0, f0, f31, f0
+ fnmadd.s f0, f0, f0, f31
+ fnmadd.s f0, f0, f0, f0, rne
+
+ fnmsub.s f31, f0, f0, f0
+ fnmsub.s f0, f31, f0, f0
+ fnmsub.s f0, f0, f31, f0
+ fnmsub.s f0, f0, f0, f31
+ fnmsub.s f0, f0, f0, f0, rne
+
+ frcsr x31
+ frflags x31
+ frrm x31
+
+ fscsr x31
+ fscsr x31, x1
+ fscsr x1, x31
+
+ fsflags x31
+ fsflags x31, x1
+ fsflags x1, x31
+
+ fsgnj.s f31, f0, f1
+ fsgnj.s f0, f31, f0
+ fsgnj.s f0, f0, f31
+ fsgnjn.s f0, f1, f0
+ fsgnjx.s f0, f1, f0
+
+ fsqrt.s f31, f0
+ fsqrt.s f0, f31
+ fsqrt.s f0, f0, rne
+
+ fsrm x31
+ fsrm x31, x1
+ fsrm x1, x31
+
+ fsub.s f31, f0, f0
+ fsub.s f0, f31, f0
+ fsub.s f0, f0, f31
+ fsub.s f0, f0, f0, rne
+
+ fsw f31, (x0)
+ fsw f0, 0x1f(x0)
+ fsw f0, -0x20(x0)
+ fsw f0, (x31)
+ fsw f0, sval, x31
--- a/gas/testsuite/gas/riscv/fp-zfh-insns.d
+++ b/gas/testsuite/gas/riscv/fp-zfh-insns.d
@@ -9,7 +9,19 @@ Disassembly of section .text:
0+000 <.text>:
[ ]+[0-9a-f]+:[ ]+00059507[ ]+flh[ ]+fa0,0\(a1\)
+[ ]+[0-9a-f]+:[ ]+00000297[ ]+auipc[ ]+t0,0x0
+[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+hval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00029507[ ]+flh[ ]+fa0,0\(t0\) # [0-9a-f]+( <.*>)?
+[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ].*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
[ ]+[0-9a-f]+:[ ]+00a59027[ ]+fsh[ ]+fa0,0\(a1\)
+[ ]+[0-9a-f]+:[ ]+00000297[ ]+auipc[ ]+t0,0x0
+[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+hval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00a29027[ ]+fsh[ ]+fa0,0\(t0\) # [0-9a-f]+( <.*>)?
+[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ].*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
[ ]+[0-9a-f]+:[ ]+24b58553[ ]+fmv.h[ ]+fa0,fa1
[ ]+[0-9a-f]+:[ ]+24b59553[ ]+fneg.h[ ]+fa0,fa1
[ ]+[0-9a-f]+:[ ]+24b5a553[ ]+fabs.h[ ]+fa0,fa1
--- a/gas/testsuite/gas/riscv/fp-zfh-insns.s
+++ b/gas/testsuite/gas/riscv/fp-zfh-insns.s
@@ -1,5 +1,7 @@
flh fa0, 0(a1)
+ flh fa0, hval, t0
fsh fa0, 0(a1)
+ fsh fa0, hval, t0
fmv.h fa0, fa1
fneg.h fa0, fa1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] RISC-V: Lx/Sx macro insn tests
2023-10-30 14:45 [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Jan Beulich
2023-10-30 14:46 ` [PATCH 1/4] RISC-V: make FLQ/FSQ macro-insns work Jan Beulich
2023-10-30 14:46 ` [PATCH 2/4] RISC-V: add F- and D-extension testcases Jan Beulich
@ 2023-10-30 14:47 ` Jan Beulich
2023-10-30 14:47 ` [PATCH 4/4] RISC-V: reduce redundancy in load/store macro insn handling Jan Beulich
2023-10-31 2:03 ` [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Nelson Chu
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2023-10-30 14:47 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu
Make sure these (continue to) work as intended.
--- /dev/null
+++ b/gas/testsuite/gas/riscv/l-s-macro.d
@@ -0,0 +1,56 @@
+#as: -march=rv64i
+#name: Lx/Sx macro insns
+#objdump: -dwr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <L>:
+[ ]+[0-9a-f]+:[ ]+00000517[ ]+auipc[ ]+a0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+bval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00050503[ ]+lb[ ]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000517[ ]+auipc[ ]+a0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+bval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00054503[ ]+lbu[ ]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000517[ ]+auipc[ ]+a0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+hval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00051503[ ]+lh[ ]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000517[ ]+auipc[ ]+a0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+hval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00055503[ ]+lhu[ ]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000517[ ]+auipc[ ]+a0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+wval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00052503[ ]+lw[ ]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000517[ ]+auipc[ ]+a0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+wval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00056503[ ]+lwu[ ]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000517[ ]+auipc[ ]+a0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+dval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00053503[ ]+ld[ ]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+
+[0-9a-f]+ <S>:
+[ ]+[0-9a-f]+:[ ]+00000297[ ]+auipc[ ]+t0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+bval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00a28023[ ]+sb[ ]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000297[ ]+auipc[ ]+t0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+hval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00a29023[ ]+sh[ ]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000297[ ]+auipc[ ]+t0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+wval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00a2a023[ ]+sw[ ]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00000297[ ]+auipc[ ]+t0,0x0[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_HI20[ ]+dval
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
+[ ]+[0-9a-f]+:[ ]+00a2b023[ ]+sd[ ]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_S[ ]+.*
+[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX.*
--- /dev/null
+++ b/gas/testsuite/gas/riscv/l-s-macro.s
@@ -0,0 +1,14 @@
+L:
+ lb a0, bval
+ lbu a0, bval
+ lh a0, hval
+ lhu a0, hval
+ lw a0, wval
+ lwu a0, wval
+ ld a0, dval
+
+S:
+ sb a0, bval, t0
+ sh a0, hval, t0
+ sw a0, wval, t0
+ sd a0, dval, t0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/4] RISC-V: reduce redundancy in load/store macro insn handling
2023-10-30 14:45 [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Jan Beulich
` (2 preceding siblings ...)
2023-10-30 14:47 ` [PATCH 3/4] RISC-V: Lx/Sx macro insn tests Jan Beulich
@ 2023-10-30 14:47 ` Jan Beulich
2023-10-31 2:03 ` [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Nelson Chu
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2023-10-30 14:47 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu
Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and
FS{H,W,D,Q} the sole difference between the handling is the insn
mnemonic passed to the common handling functions. The intended mnemonic,
however, can easily be retrieved. Furthermore leverags that Sx and FSx
are then handled identically, too, and hence their cases can also be
folded.
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2056,88 +2056,18 @@ macro (struct riscv_cl_insn *ip, express
BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
- case M_LB:
- pcrel_load (rd, rd, imm_expr, "lb",
+ case M_Lx:
+ pcrel_load (rd, rd, imm_expr, ip->insn_mo->name,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
- case M_LBU:
- pcrel_load (rd, rd, imm_expr, "lbu",
+ case M_FLx:
+ pcrel_load (rd, rs1, imm_expr, ip->insn_mo->name,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
- case M_LH:
- pcrel_load (rd, rd, imm_expr, "lh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LHU:
- pcrel_load (rd, rd, imm_expr, "lhu",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LW:
- pcrel_load (rd, rd, imm_expr, "lw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LWU:
- pcrel_load (rd, rd, imm_expr, "lwu",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LD:
- pcrel_load (rd, rd, imm_expr, "ld",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_FLW:
- pcrel_load (rd, rs1, imm_expr, "flw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_FLD:
- pcrel_load (rd, rs1, imm_expr, "fld",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_FLQ:
- pcrel_load (rd, rs1, imm_expr, "flq",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_SB:
- pcrel_store (rs2, rs1, imm_expr, "sb",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_SH:
- pcrel_store (rs2, rs1, imm_expr, "sh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_SW:
- pcrel_store (rs2, rs1, imm_expr, "sw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_SD:
- pcrel_store (rs2, rs1, imm_expr, "sd",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_FSW:
- pcrel_store (rs2, rs1, imm_expr, "fsw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_FSD:
- pcrel_store (rs2, rs1, imm_expr, "fsd",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_FSQ:
- pcrel_store (rs2, rs1, imm_expr, "fsq",
+ case M_Sx_FSx:
+ pcrel_store (rs2, rs1, imm_expr, ip->insn_mo->name,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
break;
@@ -2165,15 +2095,6 @@ macro (struct riscv_cl_insn *ip, express
vector_macro (ip);
break;
- case M_FLH:
- pcrel_load (rd, rs1, imm_expr, "flh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
- case M_FSH:
- pcrel_store (rs2, rs1, imm_expr, "fsh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
default:
as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
break;
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -538,23 +538,9 @@ enum
M_LGA,
M_LA_TLS_GD,
M_LA_TLS_IE,
- M_LB,
- M_LBU,
- M_LH,
- M_LHU,
- M_LW,
- M_LWU,
- M_LD,
- M_SB,
- M_SH,
- M_SW,
- M_SD,
- M_FLW,
- M_FLD,
- M_FLQ,
- M_FSW,
- M_FSD,
- M_FSQ,
+ M_Lx,
+ M_FLx,
+ M_Sx_FSx,
M_CALL,
M_J,
M_LI,
@@ -563,8 +549,6 @@ enum
M_SEXTB,
M_SEXTH,
M_VMSGE,
- M_FLH,
- M_FSH,
M_NUM_MACROS
};
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -462,20 +462,20 @@ const struct riscv_opcode riscv_opcodes[
{"sub", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
{"sub", 0, INSN_CLASS_I, "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 },
{"lb", 0, INSN_CLASS_I, "d,o(s)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_LB, match_never, INSN_MACRO },
+{"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lbu", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_1_BYTE },
{"lbu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"lbu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LBU, match_never, INSN_MACRO },
+{"lbu", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LH, MASK_C_LH, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE },
{"lh", 0, INSN_CLASS_I, "d,o(s)", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"lh", 0, INSN_CLASS_I, "d,A", 0, (int) M_LH, match_never, INSN_MACRO },
+{"lh", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lhu", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE },
{"lhu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LHU, match_never, INSN_MACRO },
+{"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lw", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
+{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"not", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_NOT, MASK_C_NOT, match_opcode, INSN_ALIAS },
{"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
{"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
@@ -498,14 +498,14 @@ const struct riscv_opcode riscv_opcodes[
{"sgtu", 0, INSN_CLASS_I, "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS },
{"sb", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_SB, MASK_C_SB, match_opcode, INSN_DREF|INSN_1_BYTE|INSN_ALIAS },
{"sb", 0, INSN_CLASS_I, "t,q(s)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"sb", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO },
+{"sb", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"sh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_SH, MASK_C_SH, match_opcode, INSN_DREF|INSN_2_BYTE|INSN_ALIAS },
{"sh", 0, INSN_CLASS_I, "t,q(s)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO },
+{"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"sw", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO },
+{"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
@@ -524,15 +524,15 @@ const struct riscv_opcode riscv_opcodes[
{"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
{"xor", 0, INSN_CLASS_I, "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 },
{"lwu", 64, INSN_CLASS_I, "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_LWU, match_never, INSN_MACRO },
+{"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"ld", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"ld", 64, INSN_CLASS_I, "d,o(s)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"ld", 64, INSN_CLASS_I, "d,A", 0, (int) M_LD, match_never, INSN_MACRO },
+{"ld", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"sd", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
+{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
{"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS },
{"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
@@ -663,9 +663,9 @@ const struct riscv_opcode riscv_opcodes[
/* Half-precision floating-point instruction subset. */
{"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO },
+{"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsh", 0, INSN_CLASS_ZFHMIN, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO },
+{"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.x.h", 0, INSN_CLASS_ZFHMIN, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
{"fmv.h.x", 0, INSN_CLASS_ZFHMIN, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
{"fmv.h", 0, INSN_CLASS_ZFH_INX, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
@@ -746,11 +746,11 @@ const struct riscv_opcode riscv_opcodes[
{"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO },
+{"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsw", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO },
+{"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
@@ -808,11 +808,11 @@ const struct riscv_opcode riscv_opcodes[
{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO },
+{"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsd", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
+{"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
@@ -867,9 +867,9 @@ const struct riscv_opcode riscv_opcodes[
/* Quad-precision floating-point instruction subset. */
{"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
-{"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO },
+{"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
-{"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
+{"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] RISC-V: load/store macro insn handling adjustments
2023-10-30 14:45 [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Jan Beulich
` (3 preceding siblings ...)
2023-10-30 14:47 ` [PATCH 4/4] RISC-V: reduce redundancy in load/store macro insn handling Jan Beulich
@ 2023-10-31 2:03 ` Nelson Chu
4 siblings, 0 replies; 6+ messages in thread
From: Nelson Chu @ 2023-10-31 2:03 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson
[-- Attachment #1: Type: text/plain, Size: 358 bytes --]
All LGTM, thanks ;)
Nelson
On Mon, Oct 30, 2023 at 10:45 PM Jan Beulich <jbeulich@suse.com> wrote:
> ... plus, really, some bits previously missing from the testsuite.
>
> 1: make FLQ/FSQ macro-insns work
> 2: add F- and D-extension testcases
> 3: Lx/Sx macro insn tests
> 4: reduce redundancy in load/store macro insn handling
>
> Jan
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-10-31 2:03 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-10-30 14:45 [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Jan Beulich
2023-10-30 14:46 ` [PATCH 1/4] RISC-V: make FLQ/FSQ macro-insns work Jan Beulich
2023-10-30 14:46 ` [PATCH 2/4] RISC-V: add F- and D-extension testcases Jan Beulich
2023-10-30 14:47 ` [PATCH 3/4] RISC-V: Lx/Sx macro insn tests Jan Beulich
2023-10-30 14:47 ` [PATCH 4/4] RISC-V: reduce redundancy in load/store macro insn handling Jan Beulich
2023-10-31 2:03 ` [PATCH 0/4] RISC-V: load/store macro insn handling adjustments Nelson Chu
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