[PATCH 0/3] RISC-V: alias insn adjustments

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* [PATCH 0/3] RISC-V: alias insn adjustments
@ 2022-09-13 12:59 Jan Beulich
  2022-09-13 13:02 ` [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling Jan Beulich
                   ` (6 more replies)
  0 siblings, 7 replies; 29+ messages in thread
From: Jan Beulich @ 2022-09-13 12:59 UTC (permalink / raw)
  To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

1: re-arrange opcode table for consistent alias handling
2: drop stray INSN_ALIAS flags
3: add alias for SLLI.UW

In particular the 3rd patch may want considering to be at least slightly
RFC.

Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
@ 2022-09-13 13:02 ` Jan Beulich
  2022-09-15  2:30   ` Nelson Chu
  2022-09-13 13:03 ` [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags Jan Beulich
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 29+ messages in thread
From: Jan Beulich @ 2022-09-13 13:02 UTC (permalink / raw)
  To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

For disassembly to pick up aliases in favor of underlying insns (helping
readability in the common case), the aliases need to come ahead of the
"base" insns. Slightly more code movement is needed because of insns
with the same name needing to stay next to each other.

Note that the "rorw" alias entry also has the missing INSN_ALIAS added
here.

Clone a few testcases to exercise -Mno-aliases some more, better
covering the differences between the default and that disassembly mode.

--- a/gas/testsuite/gas/riscv/b-ext.d
+++ b/gas/testsuite/gas/riscv/b-ext.d
@@ -23,8 +23,8 @@ Disassembly of section .text:
 [ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
 [ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
 [ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
-[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
-[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+3c:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
+[ 	]+40:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
 [ 	]+44:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
 [ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
 [ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
@@ -33,19 +33,19 @@ Disassembly of section .text:
 [ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
 [ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
 [ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclri[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bseti[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+68059513[ 	]+binvi[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+4805d513[ 	]+bexti[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclr[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bset[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bset[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+68059513[ 	]+binv[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binv[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4805d513[ 	]+bext[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bext[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bset[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binv[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bext[ 	]+a0,a1,0x1f
--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -23,8 +23,8 @@ Disassembly of section .text:
 [ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
 [ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
 [ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
-[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
-[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+3c:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
+[ 	]+40:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
 [ 	]+44:[ 	]+6b855513[ 	]+rev8[ 	]+a0,a0
 [ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
 [ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
@@ -38,35 +38,35 @@ Disassembly of section .text:
 [ 	]+6c:[ 	]+6025151b[ 	]+cpopw[ 	]+a0,a0
 [ 	]+70:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
 [ 	]+74:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
-[ 	]+78:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
-[ 	]+7c:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+78:[ 	]+6025d51b[ 	]+rorw[ 	]+a0,a1,0x2
+[ 	]+7c:[ 	]+6025d51b[ 	]+rorw[ 	]+a0,a1,0x2
 [ 	]+80:[ 	]+20c5a53b[ 	]+sh1add.uw[ 	]+a0,a1,a2
 [ 	]+84:[ 	]+20c5c53b[ 	]+sh2add.uw[ 	]+a0,a1,a2
 [ 	]+88:[ 	]+20c5e53b[ 	]+sh3add.uw[ 	]+a0,a1,a2
 [ 	]+8c:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
 [ 	]+90:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
 [ 	]+94:[ 	]+0825951b[ 	]+slli.uw[ 	]+a0,a1,0x2
-[ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclri[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bseti[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+68059513[ 	]+binvi[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+4805d513[ 	]+bexti[ 	]+a0,a1,0x0
-[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+4bf59513[ 	]+bclri[ 	]+a0,a1,0x3f
-[ 	]+[0-9a-f]+:[ 	]+2bf59513[ 	]+bseti[ 	]+a0,a1,0x3f
-[ 	]+[0-9a-f]+:[ 	]+6bf59513[ 	]+binvi[ 	]+a0,a1,0x3f
-[ 	]+[0-9a-f]+:[ 	]+4bf5d513[ 	]+bexti[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclr[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bset[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bset[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+68059513[ 	]+binv[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binv[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4805d513[ 	]+bext[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bext[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4bf59513[ 	]+bclr[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+2bf59513[ 	]+bset[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+6bf59513[ 	]+binv[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+4bf5d513[ 	]+bext[ 	]+a0,a1,0x3f
 [ 	]+[0-9a-f]+:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
-[ 	]+[0-9a-f]+:[ 	]+4bf59513[ 	]+bclri[ 	]+a0,a1,0x3f
-[ 	]+[0-9a-f]+:[ 	]+2bf59513[ 	]+bseti[ 	]+a0,a1,0x3f
-[ 	]+[0-9a-f]+:[ 	]+6bf59513[ 	]+binvi[ 	]+a0,a1,0x3f
-[ 	]+[0-9a-f]+:[ 	]+4bf5d513[ 	]+bexti[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bset[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binv[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bext[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4bf59513[ 	]+bclr[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+2bf59513[ 	]+bset[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+6bf59513[ 	]+binv[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+4bf5d513[ 	]+bext[ 	]+a0,a1,0x3f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext-64-na.d
@@ -0,0 +1,72 @@
+#as: -march=rv64i_zba_zbb_zbc_zbs
+#source: b-ext-64.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60451513[ 	]+sext\.b[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+60551513[ 	]+sext\.h[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+0805453b[ 	]+zext\.h[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6b855513[ 	]+rev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+28755513[ 	]+orc\.b[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6005151b[ 	]+clzw[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+6015151b[ 	]+ctzw[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+6025151b[ 	]+cpopw[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+20c5a53b[ 	]+sh1add\.uw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c5c53b[ 	]+sh2add\.uw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c5e53b[ 	]+sh3add\.uw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5853b[ 	]+add\.uw[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0805853b[ 	]+add\.uw[ 	]+a0,a1,zero
+[ 	]+[0-9a-f]+:[ 	]+0825951b[ 	]+slli\.uw[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclri[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bseti[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+68059513[ 	]+binvi[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4805d513[ 	]+bexti[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4bf59513[ 	]+bclri[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+2bf59513[ 	]+bseti[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+6bf59513[ 	]+binvi[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+4bf5d513[ 	]+bexti[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4bf59513[ 	]+bclri[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+2bf59513[ 	]+bseti[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+6bf59513[ 	]+binvi[ 	]+a0,a1,0x3f
+[ 	]+[0-9a-f]+:[ 	]+4bf5d513[ 	]+bexti[ 	]+a0,a1,0x3f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext-na.d
@@ -0,0 +1,51 @@
+#as: -march=rv32i_zba_zbb_zbc_zbs
+#source: b-ext.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60451513[ 	]+sext\.b[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+60551513[ 	]+sext\.h[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+08054533[ 	]+zext\.h[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+28755513[ 	]+orc\.b[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclri[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bseti[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+68059513[ 	]+binvi[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+4805d513[ 	]+bexti[ 	]+a0,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
+[ 	]+[0-9a-f]+:[ 	]+49f5d513[ 	]+bexti[ 	]+a0,a1,0x1f
--- a/gas/testsuite/gas/riscv/c-zero-imm.d
+++ b/gas/testsuite/gas/riscv/c-zero-imm.d
@@ -9,14 +9,14 @@ Disassembly of section .text:
 0+000 <.text>:
 [ 	]+0:[ 	]+4501[ 	]+li[ 	]+a0,0
 [ 	]+2:[ 	]+4581[ 	]+li[ 	]+a1,0
-[ 	]+4:[ 	]+8a01[ 	]+andi[ 	]+a2,a2,0
-[ 	]+6:[ 	]+8a81[ 	]+andi[ 	]+a3,a3,0
+[ 	]+4:[ 	]+8a01[ 	]+and[ 	]+a2,a2,0
+[ 	]+6:[ 	]+8a81[ 	]+and[ 	]+a3,a3,0
 [ 	]+8:[ 	]+0001[ 	]+nop
 [ 	]+a:[ 	]+873a[ 	]+mv[ 	]+a4,a4
-[ 	]+c:[ 	]+0781[ 	]+addi[ 	]+a5,a5,0
-[ 	]+e:[ 	]+00051513[ 	]+slli[ 	]+a0,a0,0x0
-[ 	]+12:[ 	]+0005d593[ 	]+srli[ 	]+a1,a1,0x0
-[ 	]+16:[ 	]+40065613[ 	]+srai[ 	]+a2,a2,0x0
+[ 	]+c:[ 	]+0781[ 	]+add[ 	]+a5,a5,0
+[ 	]+e:[ 	]+00051513[ 	]+sll[ 	]+a0,a0,0x0
+[ 	]+12:[ 	]+0005d593[ 	]+srl[ 	]+a1,a1,0x0
+[ 	]+16:[ 	]+40065613[ 	]+sra[ 	]+a2,a2,0x0
 [ 	]+1a:[ 	]+0682[ 	]+c.slli64[ 	]+a3
 [ 	]+1c:[ 	]+8301[ 	]+c.srli64[ 	]+a4
 [ 	]+1e:[ 	]+8781[ 	]+c.srai64[ 	]+a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/c-zero-imm-na.d
@@ -0,0 +1,24 @@
+#as:
+#source: c-zero-imm.s
+#objdump: -dr -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+4501[ 	]+c\.li[ 	]+a0,0
+[ 	]+[0-9a-f]+:[ 	]+4581[ 	]+c\.li[ 	]+a1,0
+[ 	]+[0-9a-f]+:[ 	]+8a01[ 	]+c\.andi[ 	]+a2,0
+[ 	]+[0-9a-f]+:[ 	]+8a81[ 	]+c\.andi[ 	]+a3,0
+[ 	]+[0-9a-f]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
+[ 	]+[0-9a-f]+:[ 	]+873a[ 	]+c\.mv[ 	]+a4,a4
+[ 	]+[0-9a-f]+:[ 	]+0781[ 	]+c\.addi[ 	]+a5,0
+[ 	]+[0-9a-f]+:[ 	]+00051513[ 	]+slli[ 	]+a0,a0,0x0
+[ 	]+[0-9a-f]+:[ 	]+0005d593[ 	]+srli[ 	]+a1,a1,0x0
+[ 	]+[0-9a-f]+:[ 	]+40065613[ 	]+srai[ 	]+a2,a2,0x0
+[ 	]+[0-9a-f]+:[ 	]+0682[ 	]+c\.slli64[ 	]+a3
+[ 	]+[0-9a-f]+:[ 	]+8301[ 	]+c\.srli64[ 	]+a4
+[ 	]+[0-9a-f]+:[ 	]+8781[ 	]+c\.srai64[ 	]+a5
+#...
--- a/gas/testsuite/gas/riscv/c-zero-reg.d
+++ b/gas/testsuite/gas/riscv/c-zero-reg.d
@@ -14,7 +14,7 @@ Disassembly of section .text:
 [ 	]+8:[ 	]+9006[ 	]+c.add[ 	]+zero,ra
 [ 	]+a:[ 	]+00500013[ 	]+li[ 	]+zero,5
 [ 	]+e:[ 	]+00006037[ 	]+lui[ 	]+zero,0x6
-[ 	]+12:[ 	]+00701013[ 	]+slli[ 	]+zero,zero,0x7
+[ 	]+12:[ 	]+00701013[ 	]+sll[ 	]+zero,zero,0x7
 [ 	]+16:[ 	]+00008013[ 	]+mv[ 	]+zero,ra
 [ 	]+1a:[ 	]+00100033[ 	]+add[ 	]+zero,zero,ra
 #...
--- a/gas/testsuite/gas/riscv/csr-insns-pseudo.d
+++ b/gas/testsuite/gas/riscv/csr-insns-pseudo.d
@@ -12,9 +12,9 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+00029073[ 	]+csrw[ 	]+ustatus,t0
 [ 	]+[0-9a-f]+:[ 	]+0002a073[ 	]+csrs[ 	]+ustatus,t0
 [ 	]+[0-9a-f]+:[ 	]+0002b073[ 	]+csrc[ 	]+ustatus,t0
-[ 	]+[0-9a-f]+:[ 	]+000fd073[ 	]+csrwi[ 	]+ustatus,31
-[ 	]+[0-9a-f]+:[ 	]+000fe073[ 	]+csrsi[ 	]+ustatus,31
-[ 	]+[0-9a-f]+:[ 	]+000ff073[ 	]+csrci[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000fd073[ 	]+csrw[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000fe073[ 	]+csrs[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000ff073[ 	]+csrc[ 	]+ustatus,31
 [ 	]+[0-9a-f]+:[ 	]+c00022f3[ 	]+rdcycle[ 	]+t0
 [ 	]+[0-9a-f]+:[ 	]+c01022f3[ 	]+rdtime[ 	]+t0
 [ 	]+[0-9a-f]+:[ 	]+c02022f3[ 	]+rdinstret[ 	]+t0
--- a/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d
+++ b/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d
@@ -12,9 +12,9 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+00029073[ 	]+csrw[ 	]+ustatus,t0
 [ 	]+[0-9a-f]+:[ 	]+0002a073[ 	]+csrs[ 	]+ustatus,t0
 [ 	]+[0-9a-f]+:[ 	]+0002b073[ 	]+csrc[ 	]+ustatus,t0
-[ 	]+[0-9a-f]+:[ 	]+000fd073[ 	]+csrwi[ 	]+ustatus,31
-[ 	]+[0-9a-f]+:[ 	]+000fe073[ 	]+csrsi[ 	]+ustatus,31
-[ 	]+[0-9a-f]+:[ 	]+000ff073[ 	]+csrci[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000fd073[ 	]+csrw[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000fe073[ 	]+csrs[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000ff073[ 	]+csrc[ 	]+ustatus,31
 [ 	]+[0-9a-f]+:[ 	]+c00022f3[ 	]+rdcycle[ 	]+t0
 [ 	]+[0-9a-f]+:[ 	]+c01022f3[ 	]+rdtime[ 	]+t0
 [ 	]+[0-9a-f]+:[ 	]+c02022f3[ 	]+rdinstret[ 	]+t0
--- a/gas/testsuite/gas/riscv/ext-32.d
+++ b/gas/testsuite/gas/riscv/ext-32.d
@@ -9,31 +9,31 @@ Disassembly of section .text:
 
 0+000 <target>:
 [ 	]+0:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
-[ 	]+4:[ 	]+01051513[ 	]+slli[ 	]+a0,a0,0x10
-[ 	]+8:[ 	]+01055513[ 	]+srli[ 	]+a0,a0,0x10
-[ 	]+c:[ 	]+01851513[ 	]+slli[ 	]+a0,a0,0x18
-[ 	]+10:[ 	]+41855513[ 	]+srai[ 	]+a0,a0,0x18
-[ 	]+14:[ 	]+01051513[ 	]+slli[ 	]+a0,a0,0x10
-[ 	]+18:[ 	]+41055513[ 	]+srai[ 	]+a0,a0,0x10
+[ 	]+4:[ 	]+01051513[ 	]+sll[ 	]+a0,a0,0x10
+[ 	]+8:[ 	]+01055513[ 	]+srl[ 	]+a0,a0,0x10
+[ 	]+c:[ 	]+01851513[ 	]+sll[ 	]+a0,a0,0x18
+[ 	]+10:[ 	]+41855513[ 	]+sra[ 	]+a0,a0,0x18
+[ 	]+14:[ 	]+01051513[ 	]+sll[ 	]+a0,a0,0x10
+[ 	]+18:[ 	]+41055513[ 	]+sra[ 	]+a0,a0,0x10
 [ 	]+1c:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
-[ 	]+20:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
-[ 	]+24:[ 	]+0105d593[ 	]+srli[ 	]+a1,a1,0x10
-[ 	]+28:[ 	]+01861593[ 	]+slli[ 	]+a1,a2,0x18
-[ 	]+2c:[ 	]+4185d593[ 	]+srai[ 	]+a1,a1,0x18
-[ 	]+30:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
-[ 	]+34:[ 	]+4105d593[ 	]+srai[ 	]+a1,a1,0x10
+[ 	]+20:[ 	]+01061593[ 	]+sll[ 	]+a1,a2,0x10
+[ 	]+24:[ 	]+0105d593[ 	]+srl[ 	]+a1,a1,0x10
+[ 	]+28:[ 	]+01861593[ 	]+sll[ 	]+a1,a2,0x18
+[ 	]+2c:[ 	]+4185d593[ 	]+sra[ 	]+a1,a1,0x18
+[ 	]+30:[ 	]+01061593[ 	]+sll[ 	]+a1,a2,0x10
+[ 	]+34:[ 	]+4105d593[ 	]+sra[ 	]+a1,a1,0x10
 [ 	]+38:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
-[ 	]+3c:[ 	]+0542[ 	]+slli[ 	]+a0,a0,0x10
-[ 	]+3e:[ 	]+8141[ 	]+srli[ 	]+a0,a0,0x10
-[ 	]+40:[ 	]+0562[ 	]+slli[ 	]+a0,a0,0x18
-[ 	]+42:[ 	]+8561[ 	]+srai[ 	]+a0,a0,0x18
-[ 	]+44:[ 	]+0542[ 	]+slli[ 	]+a0,a0,0x10
-[ 	]+46:[ 	]+8541[ 	]+srai[ 	]+a0,a0,0x10
+[ 	]+3c:[ 	]+0542[ 	]+sll[ 	]+a0,a0,0x10
+[ 	]+3e:[ 	]+8141[ 	]+srl[ 	]+a0,a0,0x10
+[ 	]+40:[ 	]+0562[ 	]+sll[ 	]+a0,a0,0x18
+[ 	]+42:[ 	]+8561[ 	]+sra[ 	]+a0,a0,0x18
+[ 	]+44:[ 	]+0542[ 	]+sll[ 	]+a0,a0,0x10
+[ 	]+46:[ 	]+8541[ 	]+sra[ 	]+a0,a0,0x10
 [ 	]+48:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
-[ 	]+4c:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
-[ 	]+50:[ 	]+81c1[ 	]+srli[ 	]+a1,a1,0x10
-[ 	]+52:[ 	]+01861593[ 	]+slli[ 	]+a1,a2,0x18
-[ 	]+56:[ 	]+85e1[ 	]+srai[ 	]+a1,a1,0x18
-[ 	]+58:[ 	]+01061593[ 	]+slli[ 	]+a1,a2,0x10
-[ 	]+5c:[ 	]+85c1[ 	]+srai[ 	]+a1,a1,0x10
+[ 	]+4c:[ 	]+01061593[ 	]+sll[ 	]+a1,a2,0x10
+[ 	]+50:[ 	]+81c1[ 	]+srl[ 	]+a1,a1,0x10
+[ 	]+52:[ 	]+01861593[ 	]+sll[ 	]+a1,a2,0x18
+[ 	]+56:[ 	]+85e1[ 	]+sra[ 	]+a1,a1,0x18
+[ 	]+58:[ 	]+01061593[ 	]+sll[ 	]+a1,a2,0x10
+[ 	]+5c:[ 	]+85c1[ 	]+sra[ 	]+a1,a1,0x10
 #...
--- a/gas/testsuite/gas/riscv/ext-64.d
+++ b/gas/testsuite/gas/riscv/ext-64.d
@@ -9,43 +9,43 @@ Disassembly of section .text:
 
 0+000 <target>:
 [ 	]+0:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
-[ 	]+4:[ 	]+03051513[ 	]+slli[ 	]+a0,a0,0x30
-[ 	]+8:[ 	]+03055513[ 	]+srli[ 	]+a0,a0,0x30
-[ 	]+c:[ 	]+03851513[ 	]+slli[ 	]+a0,a0,0x38
-[ 	]+10:[ 	]+43855513[ 	]+srai[ 	]+a0,a0,0x38
-[ 	]+14:[ 	]+03051513[ 	]+slli[ 	]+a0,a0,0x30
-[ 	]+18:[ 	]+43055513[ 	]+srai[ 	]+a0,a0,0x30
+[ 	]+4:[ 	]+03051513[ 	]+sll[ 	]+a0,a0,0x30
+[ 	]+8:[ 	]+03055513[ 	]+srl[ 	]+a0,a0,0x30
+[ 	]+c:[ 	]+03851513[ 	]+sll[ 	]+a0,a0,0x38
+[ 	]+10:[ 	]+43855513[ 	]+sra[ 	]+a0,a0,0x38
+[ 	]+14:[ 	]+03051513[ 	]+sll[ 	]+a0,a0,0x30
+[ 	]+18:[ 	]+43055513[ 	]+sra[ 	]+a0,a0,0x30
 [ 	]+1c:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
-[ 	]+20:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
-[ 	]+24:[ 	]+0305d593[ 	]+srli[ 	]+a1,a1,0x30
-[ 	]+28:[ 	]+03861593[ 	]+slli[ 	]+a1,a2,0x38
-[ 	]+2c:[ 	]+4385d593[ 	]+srai[ 	]+a1,a1,0x38
-[ 	]+30:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
-[ 	]+34:[ 	]+4305d593[ 	]+srai[ 	]+a1,a1,0x30
-[ 	]+38:[ 	]+02051513[ 	]+slli[ 	]+a0,a0,0x20
-[ 	]+3c:[ 	]+02055513[ 	]+srli[ 	]+a0,a0,0x20
+[ 	]+20:[ 	]+03061593[ 	]+sll[ 	]+a1,a2,0x30
+[ 	]+24:[ 	]+0305d593[ 	]+srl[ 	]+a1,a1,0x30
+[ 	]+28:[ 	]+03861593[ 	]+sll[ 	]+a1,a2,0x38
+[ 	]+2c:[ 	]+4385d593[ 	]+sra[ 	]+a1,a1,0x38
+[ 	]+30:[ 	]+03061593[ 	]+sll[ 	]+a1,a2,0x30
+[ 	]+34:[ 	]+4305d593[ 	]+sra[ 	]+a1,a1,0x30
+[ 	]+38:[ 	]+02051513[ 	]+sll[ 	]+a0,a0,0x20
+[ 	]+3c:[ 	]+02055513[ 	]+srl[ 	]+a0,a0,0x20
 [ 	]+40:[ 	]+0005051b[ 	]+sext.w[ 	]+a0,a0
-[ 	]+44:[ 	]+02061593[ 	]+slli[ 	]+a1,a2,0x20
-[ 	]+48:[ 	]+0205d593[ 	]+srli[ 	]+a1,a1,0x20
+[ 	]+44:[ 	]+02061593[ 	]+sll[ 	]+a1,a2,0x20
+[ 	]+48:[ 	]+0205d593[ 	]+srl[ 	]+a1,a1,0x20
 [ 	]+4c:[ 	]+0006059b[ 	]+sext.w[ 	]+a1,a2
 [ 	]+50:[ 	]+0ff57513[ 	]+zext.b[ 	]+a0,a0
-[ 	]+54:[ 	]+1542[ 	]+slli[ 	]+a0,a0,0x30
-[ 	]+56:[ 	]+9141[ 	]+srli[ 	]+a0,a0,0x30
-[ 	]+58:[ 	]+1562[ 	]+slli[ 	]+a0,a0,0x38
-[ 	]+5a:[ 	]+9561[ 	]+srai[ 	]+a0,a0,0x38
-[ 	]+5c:[ 	]+1542[ 	]+slli[ 	]+a0,a0,0x30
-[ 	]+5e:[ 	]+9541[ 	]+srai[ 	]+a0,a0,0x30
+[ 	]+54:[ 	]+1542[ 	]+sll[ 	]+a0,a0,0x30
+[ 	]+56:[ 	]+9141[ 	]+srl[ 	]+a0,a0,0x30
+[ 	]+58:[ 	]+1562[ 	]+sll[ 	]+a0,a0,0x38
+[ 	]+5a:[ 	]+9561[ 	]+sra[ 	]+a0,a0,0x38
+[ 	]+5c:[ 	]+1542[ 	]+sll[ 	]+a0,a0,0x30
+[ 	]+5e:[ 	]+9541[ 	]+sra[ 	]+a0,a0,0x30
 [ 	]+60:[ 	]+0ff67593[ 	]+zext.b[ 	]+a1,a2
-[ 	]+64:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
-[ 	]+68:[ 	]+91c1[ 	]+srli[ 	]+a1,a1,0x30
-[ 	]+6a:[ 	]+03861593[ 	]+slli[ 	]+a1,a2,0x38
-[ 	]+6e:[ 	]+95e1[ 	]+srai[ 	]+a1,a1,0x38
-[ 	]+70:[ 	]+03061593[ 	]+slli[ 	]+a1,a2,0x30
-[ 	]+74:[ 	]+95c1[ 	]+srai[ 	]+a1,a1,0x30
-[ 	]+76:[ 	]+1502[ 	]+slli[ 	]+a0,a0,0x20
-[ 	]+78:[ 	]+9101[ 	]+srli[ 	]+a0,a0,0x20
+[ 	]+64:[ 	]+03061593[ 	]+sll[ 	]+a1,a2,0x30
+[ 	]+68:[ 	]+91c1[ 	]+srl[ 	]+a1,a1,0x30
+[ 	]+6a:[ 	]+03861593[ 	]+sll[ 	]+a1,a2,0x38
+[ 	]+6e:[ 	]+95e1[ 	]+sra[ 	]+a1,a1,0x38
+[ 	]+70:[ 	]+03061593[ 	]+sll[ 	]+a1,a2,0x30
+[ 	]+74:[ 	]+95c1[ 	]+sra[ 	]+a1,a1,0x30
+[ 	]+76:[ 	]+1502[ 	]+sll[ 	]+a0,a0,0x20
+[ 	]+78:[ 	]+9101[ 	]+srl[ 	]+a0,a0,0x20
 [ 	]+7a:[ 	]+2501[ 	]+sext.w[ 	]+a0,a0
-[ 	]+7c:[ 	]+02061593[ 	]+slli[ 	]+a1,a2,0x20
-[ 	]+80:[ 	]+9181[ 	]+srli[ 	]+a1,a1,0x20
+[ 	]+7c:[ 	]+02061593[ 	]+sll[ 	]+a1,a2,0x20
+[ 	]+80:[ 	]+9181[ 	]+srl[ 	]+a1,a1,0x20
 [ 	]+82:[ 	]+0006059b[ 	]+sext.w[ 	]+a1,a2
 #...
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
 
 0+000 <target>:
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
-[^:]+:[ 	]+00d58513[ 	]+addi[ 	]+a0,a1,13
+[^:]+:[ 	]+00d58513[ 	]+add[ 	]+a0,a1,13
 [^:]+:[ 	]+00a58567[ 	]+jalr[ 	]+a0,10\(a1\)
 [^:]+:[ 	]+00458503[ 	]+lb[ 	]+a0,4\(a1\)
 [^:]+:[ 	]+feb508e3[ 	]+beq[ 	]+a0,a1,0 \<target\>
@@ -22,8 +22,8 @@ Disassembly of section .text:
 [^:]+:[ 	]+fddff56f[ 	]+jal[ 	]+a0,0 \<target\>
 [^:]+: R_RISCV_JAL[	]+target
 [^:]+:[ 	]+852e[ 	]+mv[ 	]+a0,a1
-[^:]+:[ 	]+0511[ 	]+addi[ 	]+a0,a0,4 # .*
-[^:]+:[ 	]+002c[ 	]+addi[ 	]+a1,sp,8
+[^:]+:[ 	]+0511[ 	]+add[ 	]+a0,a0,4 # .*
+[^:]+:[ 	]+002c[ 	]+add[ 	]+a1,sp,8
 [^:]+:[ 	]+c0aa[ 	]+sw[ 	]+a0,64\(sp\)
 [^:]+:[ 	]+41a8[ 	]+lw[ 	]+a0,64\(a1\)
 [^:]+:[ 	]+c1a8[ 	]+sw[ 	]+a0,64\(a1\)
@@ -32,7 +32,7 @@ Disassembly of section .text:
 [^:]+:[ 	]+b7e9[ 	]+j[ 	]+0 \<target\>
 [^:]+: R_RISCV_RVC_JUMP[	]+target
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
-[^:]+:[ 	]+00d58513[ 	]+addi[ 	]+a0,a1,13
+[^:]+:[ 	]+00d58513[ 	]+add[ 	]+a0,a1,13
 [^:]+:[ 	]+00a58567[ 	]+jalr[ 	]+a0,10\(a1\)
 [^:]+:[ 	]+00458503[ 	]+lb[ 	]+a0,4\(a1\)
 [^:]+:[ 	]+fab50ce3[ 	]+beq[ 	]+a0,a1,0 \<target\>
@@ -46,8 +46,8 @@ Disassembly of section .text:
 [^:]+:[ 	]+fa5ff56f[ 	]+jal[ 	]+a0,0 \<target\>
 [^:]+: R_RISCV_JAL[	]+target
 [^:]+:[ 	]+852e[ 	]+mv[ 	]+a0,a1
-[^:]+:[ 	]+0511[ 	]+addi[ 	]+a0,a0,4 # .*
-[^:]+:[ 	]+002c[ 	]+addi[ 	]+a1,sp,8
+[^:]+:[ 	]+0511[ 	]+add[ 	]+a0,a0,4 # .*
+[^:]+:[ 	]+002c[ 	]+add[ 	]+a1,sp,8
 [^:]+:[ 	]+c0aa[ 	]+sw[ 	]+a0,64\(sp\)
 [^:]+:[ 	]+41a8[ 	]+lw[ 	]+a0,64\(a1\)
 [^:]+:[ 	]+c1a8[ 	]+sw[ 	]+a0,64\(a1\)
--- /dev/null
+++ b/gas/testsuite/gas/riscv/insn-na.d
@@ -0,0 +1,69 @@
+#as: -march=rv32ifcv
+#source: insn.s
+#objdump: -dw -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00d58513[ 	]+addi[ 	]+a0,a1,13
+[^:]+:[ 	]+00a58567[ 	]+jalr[ 	]+a0,10\(a1\)
+[^:]+:[ 	]+00458503[ 	]+lb[ 	]+a0,4\(a1\)
+[^:]+:[ 	]+feb508e3[ 	]+beq[ 	]+a0,a1,0 \<target\>
+[^:]+:[ 	]+feb506e3[ 	]+beq[ 	]+a0,a1,0 \<target\>
+[^:]+:[ 	]+00a58223[ 	]+sb[ 	]+a0,4\(a1\)
+[^:]+:[ 	]+00fff537[ 	]+lui[ 	]+a0,0xfff
+[^:]+:[ 	]+fe1ff56f[ 	]+jal[ 	]+a0,0 \<target\>
+[^:]+:[ 	]+fddff56f[ 	]+jal[ 	]+a0,0 \<target\>
+[^:]+:[ 	]+852e[ 	]+c\.mv[ 	]+a0,a1
+[^:]+:[ 	]+0511[ 	]+c\.addi[ 	]+a0,4 # .*
+[^:]+:[ 	]+002c[ 	]+c\.addi4spn[ 	]+a1,sp,8
+[^:]+:[ 	]+c0aa[ 	]+c\.swsp[ 	]+a0,64\(sp\)
+[^:]+:[ 	]+41a8[ 	]+c\.lw[ 	]+a0,64\(a1\)
+[^:]+:[ 	]+c1a8[ 	]+c\.sw[ 	]+a0,64\(a1\)
+[^:]+:[ 	]+d5f1[ 	]+c\.beqz[ 	]+a1,0 \<target\>
+[^:]+:[ 	]+b7e9[ 	]+c\.j[ 	]+0 \<target\>
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00d58513[ 	]+addi[ 	]+a0,a1,13
+[^:]+:[ 	]+00a58567[ 	]+jalr[ 	]+a0,10\(a1\)
+[^:]+:[ 	]+00458503[ 	]+lb[ 	]+a0,4\(a1\)
+[^:]+:[ 	]+fab50ce3[ 	]+beq[ 	]+a0,a1,0 \<target\>
+[^:]+:[ 	]+fab50ae3[ 	]+beq[ 	]+a0,a1,0 \<target\>
+[^:]+:[ 	]+00a58223[ 	]+sb[ 	]+a0,4\(a1\)
+[^:]+:[ 	]+00fff537[ 	]+lui[ 	]+a0,0xfff
+[^:]+:[ 	]+fa9ff56f[ 	]+jal[ 	]+a0,0 \<target\>
+[^:]+:[ 	]+fa5ff56f[ 	]+jal[ 	]+a0,0 \<target\>
+[^:]+:[ 	]+852e[ 	]+c\.mv[ 	]+a0,a1
+[^:]+:[ 	]+0511[ 	]+c\.addi[ 	]+a0,4 # .*
+[^:]+:[ 	]+002c[ 	]+c\.addi4spn[ 	]+a1,sp,8
+[^:]+:[ 	]+c0aa[ 	]+c\.swsp[ 	]+a0,64\(sp\)
+[^:]+:[ 	]+41a8[ 	]+c\.lw[ 	]+a0,64\(a1\)
+[^:]+:[ 	]+c1a8[ 	]+c\.sw[ 	]+a0,64\(a1\)
+[^:]+:[ 	]+8d6d[ 	]+c\.and[ 	]+a0,a1
+[^:]+:[ 	]+d9c9[ 	]+c\.beqz[ 	]+a1,0 \<target\>
+[^:]+:[ 	]+bf41[ 	]+c\.j[ 	]+0 \<target\>
+[^:]+:[ 	]+68c58543[ 	]+fmadd\.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd\.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd\.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd\.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd\.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+68c58543[ 	]+fmadd\.s[ 	]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
+[^:]+:[ 	]+022180d7[ 	]+vadd\.vv[ 	]+v1,v2,v3
+[^:]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
+[^:]+:[ 	]+00000013[ 	]+addi[ 	]+zero,zero,0
+[^:]+:[ 	]+001f 0000 0000[ 	].*
+[^:]+:[ 	]+0000003f 00000000[ 	].*
+[^:]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
+[^:]+:[ 	]+00000013[ 	]+addi[ 	]+zero,zero,0
+[^:]+:[ 	]+001f 0000 0000[ 	].*
+[^:]+:[ 	]+0000003f 00000000[ 	].*
--- a/gas/testsuite/gas/riscv/k-ext-64.d
+++ b/gas/testsuite/gas/riscv/k-ext-64.d
@@ -10,10 +10,10 @@ Disassembly of section .text:
 0+000 <target>:
 [ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d51b[ 	]+rorw[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
--- a/gas/testsuite/gas/riscv/k-ext.d
+++ b/gas/testsuite/gas/riscv/k-ext.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 0+000 <target>:
 [ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
--- a/gas/testsuite/gas/riscv/li32.d
+++ b/gas/testsuite/gas/riscv/li32.d
@@ -8,10 +8,10 @@ Disassembly of section .text:
 
 0+000 <target>:
 [^:]+:[ 	]+6521[ 	]+lui[ 	]+a0,0x8
-[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1 # .*
+[^:]+:[ 	]+0505[ 	]+add[ 	]+a0,a0,1 # .*
 [^:]+:[ 	]+6509[ 	]+lui[ 	]+a0,0x2
-[^:]+:[ 	]+f0150513[ 	]+addi[ 	]+a0,a0,-255 # .*
+[^:]+:[ 	]+f0150513[ 	]+add[ 	]+a0,a0,-255 # .*
 [^:]+:[ 	]+12345537[ 	]+lui[ 	]+a0,0x12345
-[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1 # .*
+[^:]+:[ 	]+0505[ 	]+add[ 	]+a0,a0,1 # .*
 [^:]+:[ 	]+f2345537[ 	]+lui[ 	]+a0,0xf2345
-[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1 # .*
+[^:]+:[ 	]+0505[ 	]+add[ 	]+a0,a0,1 # .*
--- a/gas/testsuite/gas/riscv/li64.d
+++ b/gas/testsuite/gas/riscv/li64.d
@@ -8,37 +8,37 @@ Disassembly of section .text:
 
 0000000000000000 <target>:
 [^:]+:[ 	]+6521[ 	]+lui[ 	]+a0,0x8
-[^:]+:[ 	]+2505[ 	]+addiw[ 	]+a0,a0,1 # .*
+[^:]+:[ 	]+2505[ 	]+addw[ 	]+a0,a0,1 # .*
 [^:]+:[ 	]+6509[ 	]+lui[ 	]+a0,0x2
-[^:]+:[ 	]+f015051b[ 	]+addiw[ 	]+a0,a0,-255 # .*
+[^:]+:[ 	]+f015051b[ 	]+addw[ 	]+a0,a0,-255 # .*
 [^:]+:[ 	]+12345537[ 	]+lui[ 	]+a0,0x12345
-[^:]+:[ 	]+2505[ 	]+addiw[ 	]+a0,a0,1 # .*
+[^:]+:[ 	]+2505[ 	]+addw[ 	]+a0,a0,1 # .*
 [^:]+:[ 	]+000f2537[ 	]+lui[ 	]+a0,0xf2
-[^:]+:[ 	]+3455051b[ 	]+addiw[ 	]+a0,a0,837 # .*
-[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
-[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+3455051b[ 	]+addw[ 	]+a0,a0,837 # .*
+[^:]+:[ 	]+0532[ 	]+sll[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+add[ 	]+a0,a0,1
 [^:]+:[ 	]+00f12537[ 	]+lui[ 	]+a0,0xf12
-[^:]+:[ 	]+3455051b[ 	]+addiw[ 	]+a0,a0,837 # .*
-[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
-[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+3455051b[ 	]+addw[ 	]+a0,a0,837 # .*
+[^:]+:[ 	]+0532[ 	]+sll[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+add[ 	]+a0,a0,1
 [^:]+:[ 	]+ff010537[ 	]+lui[ 	]+a0,0xff010
-[^:]+:[ 	]+f015051b[ 	]+addiw[ 	]+a0,a0,-255 # .*
-[^:]+:[ 	]+054e[ 	]+slli[ 	]+a0,a0,0x13
-[^:]+:[ 	]+80150513[ 	]+addi[ 	]+a0,a0,-2047
-[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
-[^:]+:[ 	]+f0150513[ 	]+addi[ 	]+a0,a0,-255
-[^:]+:[ 	]+0010051b[ 	]+addiw[ 	]+a0,zero,1
-[^:]+:[ 	]+151a[ 	]+slli[ 	]+a0,a0,0x26
-[^:]+:[ 	]+1565[ 	]+addi[ 	]+a0,a0,-7
-[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
-[^:]+:[ 	]+34550513[ 	]+addi[ 	]+a0,a0,837
-[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
-[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+f015051b[ 	]+addw[ 	]+a0,a0,-255 # .*
+[^:]+:[ 	]+054e[ 	]+sll[ 	]+a0,a0,0x13
+[^:]+:[ 	]+80150513[ 	]+add[ 	]+a0,a0,-2047
+[^:]+:[ 	]+0536[ 	]+sll[ 	]+a0,a0,0xd
+[^:]+:[ 	]+f0150513[ 	]+add[ 	]+a0,a0,-255
+[^:]+:[ 	]+0010051b[ 	]+addw[ 	]+a0,zero,1
+[^:]+:[ 	]+151a[ 	]+sll[ 	]+a0,a0,0x26
+[^:]+:[ 	]+1565[ 	]+add[ 	]+a0,a0,-7
+[^:]+:[ 	]+0536[ 	]+sll[ 	]+a0,a0,0xd
+[^:]+:[ 	]+34550513[ 	]+add[ 	]+a0,a0,837
+[^:]+:[ 	]+0532[ 	]+sll[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+add[ 	]+a0,a0,1
 [^:]+:[ 	]+01fc4537[ 	]+lui[ 	]+a0,0x1fc4
-[^:]+:[ 	]+c915051b[ 	]+addiw[ 	]+a0,a0,-879 # .*
-[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
-[^:]+:[ 	]+1565[ 	]+addi[ 	]+a0,a0,-7
-[^:]+:[ 	]+0536[ 	]+slli[ 	]+a0,a0,0xd
-[^:]+:[ 	]+34550513[ 	]+addi[ 	]+a0,a0,837
-[^:]+:[ 	]+0532[ 	]+slli[ 	]+a0,a0,0xc
-[^:]+:[ 	]+0505[ 	]+addi[ 	]+a0,a0,1
+[^:]+:[ 	]+c915051b[ 	]+addw[ 	]+a0,a0,-879 # .*
+[^:]+:[ 	]+0536[ 	]+sll[ 	]+a0,a0,0xd
+[^:]+:[ 	]+1565[ 	]+add[ 	]+a0,a0,-7
+[^:]+:[ 	]+0536[ 	]+sll[ 	]+a0,a0,0xd
+[^:]+:[ 	]+34550513[ 	]+add[ 	]+a0,a0,837
+[^:]+:[ 	]+0532[ 	]+sll[ 	]+a0,a0,0xc
+[^:]+:[ 	]+0505[ 	]+add[ 	]+a0,a0,1
--- a/gas/testsuite/gas/riscv/lla32.d
+++ b/gas/testsuite/gas/riscv/lla32.d
@@ -10,10 +10,10 @@ Disassembly of section .text:
    0:	00100513          	li	a0,1
    4:	00001537          	lui	a0,0x1
    8:	00001537          	lui	a0,0x1
-   c:	00150513          	addi	a0,a0,1 # 1001 <c>
+   c:	00150513          	add	a0,a0,1 # 1001 <c>
   10:	00001537          	lui	a0,0x1
-  14:	fff50513          	addi	a0,a0,-1 # fff <d>
+  14:	fff50513          	add	a0,a0,-1 # fff <d>
   18:	80000537          	lui	a0,0x80000
-  1c:	fff50513          	addi	a0,a0,-1 # 7fffffff <h\+0x80000000>
+  1c:	fff50513          	add	a0,a0,-1 # 7fffffff <h\+0x80000000>
   20:	00000513          	li	a0,0
   24:	fff00513          	li	a0,-1
--- a/gas/testsuite/gas/riscv/lla64.d
+++ b/gas/testsuite/gas/riscv/lla64.d
@@ -7,14 +7,14 @@
 Disassembly of section .text:
 
 0+000 <.text>:
-   0:	0010051b          	addiw	a0,zero,1
+   0:	0010051b          	addw	a0,zero,1
    4:	00001537          	lui	a0,0x1
    8:	00001537          	lui	a0,0x1
-   c:	0015051b          	addiw	a0,a0,1 # .*
+   c:	0015051b          	addw	a0,a0,1 # .*
   10:	00001537          	lui	a0,0x1
-  14:	fff5051b          	addiw	a0,a0,-1 # .*
+  14:	fff5051b          	addw	a0,a0,-1 # .*
   18:	80000537          	lui	a0,0x80000
-  1c:	fff5051b          	addiw	a0,a0,-1 # .*
+  1c:	fff5051b          	addw	a0,a0,-1 # .*
   20:	0000051b          	sext.w	a0,zero
-  24:	fff0051b          	addiw	a0,zero,-1
+  24:	fff0051b          	addw	a0,zero,-1
   28:	80000537          	lui	a0,0x80000
--- a/gas/testsuite/gas/riscv/zbkb-32.d
+++ b/gas/testsuite/gas/riscv/zbkb-32.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 0+000 <target>:
 [ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
--- a/gas/testsuite/gas/riscv/zbkb-64.d
+++ b/gas/testsuite/gas/riscv/zbkb-64.d
@@ -10,10 +10,10 @@ Disassembly of section .text:
 0+000 <target>:
 [ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+ror[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
-[ 	]+[0-9a-f]+:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+6025d51b[ 	]+rorw[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
--- a/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d
+++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
 .*:[ 	]+[0-9a-f]+[ 	]+(lw|ld)[ 	]+.*<(_GLOBAL_OFFSET_TABLE_.*|__DATA_BEGIN__.*|.*)>
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
+.*:[ 	]+[0-9a-f]+[ 	]+addi?[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
 .*:[ 	]+[0-9a-f]+[ 	]+jalr[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
--- a/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d
+++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d
@@ -13,7 +13,7 @@ Disassembly of section .text:
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
 .*:[ 	]+[0-9a-f]+[ 	]+(lw|ld)[ 	]+.*<(__DATA_BEGIN__.*|.*)>
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
+.*:[ 	]+[0-9a-f]+[ 	]+addi?[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
 .*:[ 	]+[0-9a-f]+[ 	]+jalr[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
--- a/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d
+++ b/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
 #...
 0+[0-9a-f]+ <bar>:
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
+.*:[ 	]+[0-9a-f]+[ 	]+addi?[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+.*
 .*:[ 	]+[0-9a-f]+[ 	]+(lw|ld)[ 	]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
 #...
--- a/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d
+++ b/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d
@@ -10,6 +10,6 @@ Disassembly of section .text:
 
 [0-9a-f]+ <_start>:
 .*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+a1.*
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a0,gp.*<data_a>
-.*:[ 	]+[0-9a-f]+[ 	]+addi[ 	]+a1,a1.*<data_b>
+.*:[ 	]+[0-9a-f]+[ 	]+addi?[ 	]+a0,gp.*<data_a>
+.*:[ 	]+[0-9a-f]+[ 	]+addi?[ 	]+a1,a1.*<data_b>
 #pass
--- a/ld/testsuite/ld-riscv-elf/weakref32.d
+++ b/ld/testsuite/ld-riscv-elf/weakref32.d
@@ -9,12 +9,12 @@ Disassembly of section \.text:
 90000004:	02078663          	beqz	a5,90000030 <_start\+0x30>
 90000008:	00000793          	li	a5,0
 9000000c:	02078263          	beqz	a5,90000030 <_start\+0x30>
-90000010:	ff010113          	addi	sp,sp,-16
+90000010:	ff010113          	addi?	sp,sp,-16
 90000014:	00112623          	sw	ra,12\(sp\)
 90000018:	00000097          	auipc	ra,0x0
 9000001c:	000000e7          	jalr	zero # 0 <_start\-0x90000000>
 90000020:	00c12083          	lw	ra,12\(sp\)
-90000024:	01010113          	addi	sp,sp,16
+90000024:	01010113          	addi?	sp,sp,16
 90000028:	00000317          	auipc	t1,0x0
 9000002c:	00000067          	jr	zero # 0 <_start\-0x90000000>
 90000030:	00008067          	ret
--- a/ld/testsuite/ld-riscv-elf/weakref64.d
+++ b/ld/testsuite/ld-riscv-elf/weakref64.d
@@ -9,12 +9,12 @@ Disassembly of section \.text:
     90000004:	02078663          	beqz	a5,90000030 <_start\+0x30>
     90000008:	00000793          	li	a5,0
     9000000c:	02078263          	beqz	a5,90000030 <_start\+0x30>
-    90000010:	ff010113          	addi	sp,sp,-16
+    90000010:	ff010113          	addi?	sp,sp,-16
     90000014:	00113423          	sd	ra,8\(sp\)
     90000018:	00000097          	auipc	ra,0x0
     9000001c:	000000e7          	jalr	zero # 0 <_start\-0x90000000>
     90000020:	00813083          	ld	ra,8\(sp\)
-    90000024:	01010113          	addi	sp,sp,16
+    90000024:	01010113          	addi?	sp,sp,16
     90000028:	00000317          	auipc	t1,0x0
     9000002c:	00000067          	jr	zero # 0 <_start\-0x90000000>
     90000030:	00008067          	ret
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
 {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
 {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
 {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
+{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
 {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
 {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
-{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
 {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
 {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
 {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
@@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
 {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
 {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
 {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
-{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
-{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
 {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
 {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
 {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
 {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
 {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
+{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
+{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
 {"beqz",        0, INSN_CLASS_C, "Cs,Cp",     MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
 {"beqz",        0, INSN_CLASS_I, "s,p",       MATCH_BEQ, MASK_BEQ|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
 {"beq",         0, INSN_CLASS_C, "Cs,Cz,Cp",  MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
@@ -337,13 +337,6 @@ const struct riscv_opcode riscv_opcodes[
 {"bnez",        0, INSN_CLASS_I, "s,p",       MATCH_BNE, MASK_BNE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
 {"bne",         0, INSN_CLASS_C, "Cs,Cz,Cp",  MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
 {"bne",         0, INSN_CLASS_I, "s,t,p",     MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
-{"addi",        0, INSN_CLASS_C, "Ct,Cc,CK",  MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
-{"addi",        0, INSN_CLASS_C, "d,CU,Cj",   MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
-{"addi",        0, INSN_CLASS_C, "d,CU,z",    MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
-{"addi",        0, INSN_CLASS_C, "Cc,Cc,CL",  MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
-{"addi",        0, INSN_CLASS_C, "d,Cz,Co",   MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
-{"addi",        0, INSN_CLASS_C, "d,CV,z",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
-{"addi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
 {"add",         0, INSN_CLASS_C, "d,CU,CV",   MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
 {"add",         0, INSN_CLASS_C, "d,CV,CU",   MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
 {"add",         0, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
@@ -353,26 +346,33 @@ const struct riscv_opcode riscv_opcodes[
 {"add",         0, INSN_CLASS_I, "d,s,t",     MATCH_ADD, MASK_ADD, match_opcode, 0 },
 {"add",         0, INSN_CLASS_I, "d,s,t,1",   MATCH_ADD, MASK_ADD, match_opcode, 0 },
 {"add",         0, INSN_CLASS_I, "d,s,j",     MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
+{"addi",        0, INSN_CLASS_C, "Ct,Cc,CK",  MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
+{"addi",        0, INSN_CLASS_C, "d,CU,Cj",   MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
+{"addi",        0, INSN_CLASS_C, "d,CU,z",    MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
+{"addi",        0, INSN_CLASS_C, "Cc,Cc,CL",  MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
+{"addi",        0, INSN_CLASS_C, "d,Cz,Co",   MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
+{"addi",        0, INSN_CLASS_C, "d,CV,z",    MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
+{"addi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
 {"la",          0, INSN_CLASS_I, "d,B",       0, (int) M_LA, match_never, INSN_MACRO },
 {"lla",         0, INSN_CLASS_I, "d,B",       0, (int) M_LLA, match_never, INSN_MACRO },
 {"la.tls.gd",   0, INSN_CLASS_I, "d,A",       0, (int) M_LA_TLS_GD, match_never, INSN_MACRO },
 {"la.tls.ie",   0, INSN_CLASS_I, "d,A",       0, (int) M_LA_TLS_IE, match_never, INSN_MACRO },
 {"neg",         0, INSN_CLASS_I, "d,t",       MATCH_SUB, MASK_SUB|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0  */
-{"slli",        0, INSN_CLASS_C, "d,CU,C>",   MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
-{"slli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
 {"sll",         0, INSN_CLASS_C, "d,CU,C>",   MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
 {"sll",         0, INSN_CLASS_I, "d,s,t",     MATCH_SLL, MASK_SLL, match_opcode, 0 },
 {"sll",         0, INSN_CLASS_I, "d,s,>",     MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
-{"srli",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
-{"srli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
+{"slli",        0, INSN_CLASS_C, "d,CU,C>",   MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
+{"slli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
 {"srl",         0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
 {"srl",         0, INSN_CLASS_I, "d,s,t",     MATCH_SRL, MASK_SRL, match_opcode, 0 },
 {"srl",         0, INSN_CLASS_I, "d,s,>",     MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
-{"srai",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
-{"srai",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
+{"srli",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
+{"srli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
 {"sra",         0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
 {"sra",         0, INSN_CLASS_I, "d,s,t",     MATCH_SRA, MASK_SRA, match_opcode, 0 },
 {"sra",         0, INSN_CLASS_I, "d,s,>",     MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
+{"srai",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
+{"srai",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
 {"sub",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
 {"sub",         0, INSN_CLASS_I, "d,s,t",     MATCH_SUB, MASK_SUB, match_opcode, 0 },
 {"lb",          0, INSN_CLASS_I, "d,o(s)",    MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE },
@@ -391,11 +391,11 @@ const struct riscv_opcode riscv_opcodes[
 {"prefetch.i",  0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
 {"prefetch.r",  0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
 {"prefetch.w",  0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
-{"ori",         0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, 0 },
+{"or",          0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
 {"or",          0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
 {"or",          0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
 {"or",          0, INSN_CLASS_I, "d,s,t",     MATCH_OR, MASK_OR, match_opcode, 0 },
-{"or",          0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
+{"ori",         0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, 0 },
 {"auipc",       0, INSN_CLASS_I, "d,u",       MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
 {"seqz",        0, INSN_CLASS_I, "d,s",       MATCH_SLTIU|ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
 {"snez",        0, INSN_CLASS_I, "d,t",       MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
@@ -430,11 +430,11 @@ const struct riscv_opcode riscv_opcodes[
 {"rdtimeh",    32, INSN_CLASS_I, "d",         MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
 {"ecall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
 {"scall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
-{"xori",        0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, 0 },
+{"xor",         0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_I, "d,s,t",     MATCH_XOR, MASK_XOR, match_opcode, 0 },
-{"xor",         0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
+{"xori",        0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, 0 },
 {"lwu",        64, INSN_CLASS_I, "d,o(s)",    MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE },
 {"lwu",        64, INSN_CLASS_I, "d,A",       0, (int) M_LWU, match_never, INSN_MACRO },
 {"ld",         64, INSN_CLASS_C, "d,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
@@ -447,23 +447,23 @@ const struct riscv_opcode riscv_opcodes[
 {"sd",         64, INSN_CLASS_I, "t,A,s",     0, (int) M_SD, match_never, INSN_MACRO },
 {"sext.w",     64, INSN_CLASS_C, "d,CU",      MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
 {"sext.w",     64, INSN_CLASS_I, "d,s",       MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS },
-{"addiw",      64, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
-{"addiw",      64, INSN_CLASS_I, "d,s,j",     MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 },
 {"addw",       64, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
 {"addw",       64, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
 {"addw",       64, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
 {"addw",       64, INSN_CLASS_I, "d,s,t",     MATCH_ADDW, MASK_ADDW, match_opcode, 0 },
 {"addw",       64, INSN_CLASS_I, "d,s,j",     MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS },
+{"addiw",      64, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
+{"addiw",      64, INSN_CLASS_I, "d,s,j",     MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 },
 {"negw",       64, INSN_CLASS_I, "d,t",       MATCH_SUBW, MASK_SUBW|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0  */
-{"slliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 },
 {"sllw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SLLW, MASK_SLLW, match_opcode, 0 },
 {"sllw",       64, INSN_CLASS_I, "d,s,<",     MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS },
-{"srliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 },
+{"slliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 },
 {"srlw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SRLW, MASK_SRLW, match_opcode, 0 },
 {"srlw",       64, INSN_CLASS_I, "d,s,<",     MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS },
-{"sraiw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 },
+{"srliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 },
 {"sraw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SRAW, MASK_SRAW, match_opcode, 0 },
 {"sraw",       64, INSN_CLASS_I, "d,s,<",     MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS },
+{"sraiw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 },
 {"subw",       64, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS },
 {"subw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SUBW, MASK_SUBW, match_opcode, 0 },
 
@@ -885,24 +885,24 @@ const struct riscv_opcode riscv_opcodes[
 
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR,"d,E",      MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
-{"csrwi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
-{"csrsi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS },
-{"csrci",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR,"E,s",      MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
+{"csrwi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
 {"csrs",       0, INSN_CLASS_ZICSR,"E,s",      MATCH_CSRRS, MASK_CSRRS|MASK_RD, match_opcode, INSN_ALIAS },
 {"csrs",       0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS },
+{"csrsi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS },
 {"csrc",       0, INSN_CLASS_ZICSR,"E,s",      MATCH_CSRRC, MASK_CSRRC|MASK_RD, match_opcode, INSN_ALIAS },
 {"csrc",       0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS },
-{"csrrwi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
-{"csrrsi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
-{"csrrci",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
+{"csrci",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS },
 {"csrrw",      0, INSN_CLASS_ZICSR,"d,E,s",    MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 },
 {"csrrw",      0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS },
+{"csrrwi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
 {"csrrs",      0, INSN_CLASS_ZICSR,"d,E,s",    MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 },
 {"csrrs",      0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS },
+{"csrrsi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
 {"csrrc",      0, INSN_CLASS_ZICSR,"d,E,s",    MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 },
 {"csrrc",      0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS },
+{"csrrci",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
 {"uret",       0, INSN_CLASS_I,    "",         MATCH_URET, MASK_URET, match_opcode, 0 },
 {"sret",       0, INSN_CLASS_I,    "",         MATCH_SRET, MASK_SRET, match_opcode, 0 },
 {"hret",       0, INSN_CLASS_I,    "",         MATCH_HRET, MASK_HRET, match_opcode, 0 },
@@ -951,15 +951,15 @@ const struct riscv_opcode riscv_opcodes[
 {"orn",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
 {"xnor",       0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
 {"rol",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
-{"rori",       0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
 {"ror",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
 {"ror",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+{"rori",       0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
 {"rev8",      32, INSN_CLASS_ZBB_OR_ZBKB,  "d,s",   MATCH_GREVI | MATCH_SHAMT_REV8_32, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
 {"rev8",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s",   MATCH_GREVI | MATCH_SHAMT_REV8_64, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
 {"rolw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
-{"roriw",     64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
 {"rorw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
-{"rorw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"rorw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
+{"roriw",     64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
 
 /* Zba instructions.  */
 {"sh1add",     0, INSN_CLASS_ZBA,  "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
@@ -979,18 +979,18 @@ const struct riscv_opcode riscv_opcodes[
 {"clmulr",     0, INSN_CLASS_ZBC,  "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
 
 /* Zbs instructions.  */
-{"bclri",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
-{"bseti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
-{"binvi",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
-{"bexti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
 {"bclr",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
 {"bclr",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
+{"bclri",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
 {"bset",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BSET, MASK_BSET, match_opcode, 0 },
 {"bset",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
+{"bseti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
 {"binv",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BINV, MASK_BINV, match_opcode, 0 },
 {"binv",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
+{"binvi",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
 {"bext",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
 {"bext",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
+{"bexti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
 
 /* Zbkx instructions.  */
 {"xperm4",     0, INSN_CLASS_ZBKX,  "d,s,t",  MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },


^ permalink raw reply	[flat|nested] 29+ messages in thread

* [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags
  2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
  2022-09-13 13:02 ` [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling Jan Beulich
@ 2022-09-13 13:03 ` Jan Beulich
  2022-09-15  2:43   ` Nelson Chu
  2022-09-13 13:04 ` [PATCH 3/3] RISC-V: add alias for SLLI.UW Jan Beulich
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 29+ messages in thread
From: Jan Beulich @ 2022-09-13 13:03 UTC (permalink / raw)
  To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but
presently they aren't. This fixes disassembly of these insns with
-Mno-aliases. 

--- /dev/null
+++ b/gas/testsuite/gas/riscv/fence-tso-na.d
@@ -0,0 +1,12 @@
+#as: -march=rv32ic
+#source: fence-tso.s
+#objdump: -dr -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+8330000f[ 	]+fence.tso
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32-na.d
@@ -0,0 +1,23 @@
+#as: -march=rv32i_zbkb
+#source: zbkb-32.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+68755513[ 	]+brev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+08f51513[ 	]+zip[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+08f55513[ 	]+unzip[ 	]+a0,a0
+#pass
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -421,7 +421,7 @@ const struct riscv_opcode riscv_opcodes[
 {"fence",       0, INSN_CLASS_I, "",          MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
 {"fence",       0, INSN_CLASS_I, "P,Q",       MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
 {"fence.i",     0, INSN_CLASS_ZIFENCEI, "",   MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
-{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, INSN_ALIAS },
+{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 },
 {"rdcycle",     0, INSN_CLASS_I, "d",         MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
 {"rdinstret",   0, INSN_CLASS_I, "d",         MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
 {"rdtime",      0, INSN_CLASS_I, "d",         MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
@@ -942,8 +942,8 @@ const struct riscv_opcode riscv_opcodes[
 {"cpopw",     64, INSN_CLASS_ZBB,  "d,s",   MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
 {"brev8",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
 {"brev8",     64, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
-{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
 {"pack",       0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
 {"packh",      0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
 {"packw",     64, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },


^ permalink raw reply	[flat|nested] 29+ messages in thread

* [PATCH 3/3] RISC-V: add alias for SLLI.UW
  2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
  2022-09-13 13:02 ` [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling Jan Beulich
  2022-09-13 13:03 ` [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags Jan Beulich
@ 2022-09-13 13:04 ` Jan Beulich
  2022-09-13 14:54 ` [PATCH 0/3] RISC-V: alias insn adjustments Tsukasa OI
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 29+ messages in thread
From: Jan Beulich @ 2022-09-13 13:04 UTC (permalink / raw)
  To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

Like e.g. SLLI's SLL alias, this insn would - for consistency - better
also have a SLL.UW alias, even if the spec doesn't mandate one (yet).

--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -45,7 +45,7 @@ Disassembly of section .text:
 [ 	]+88:[ 	]+20c5e53b[ 	]+sh3add.uw[ 	]+a0,a1,a2
 [ 	]+8c:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
 [ 	]+90:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
-[ 	]+94:[ 	]+0825951b[ 	]+slli.uw[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+0825951b[ 	]+sll\.uw[ 	]+a0,a1,0x2
 [ 	]+[0-9a-f]+:[ 	]+48059513[ 	]+bclr[ 	]+a0,a1,0x0
 [ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+28059513[ 	]+bset[ 	]+a0,a1,0x0
@@ -62,6 +62,7 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0835951b[ 	]+sll\.uw[ 	]+a0,a1,0x3
 [ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclr[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bset[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binv[ 	]+a0,a1,0x1f
--- a/gas/testsuite/gas/riscv/b-ext-64.s
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -54,6 +54,7 @@ target:
 	binv    a0, a1, a2
 	bext    a0, a1, a2
 	#aliases
+	sll.uw	a0, a1, 3
 	bclr    a0, a1, 31
 	bset    a0, a1, 31
 	binv    a0, a1, 31
--- a/gas/testsuite/gas/riscv/b-ext-64-na.d
+++ b/gas/testsuite/gas/riscv/b-ext-64-na.d
@@ -62,6 +62,7 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
 [ 	]+[0-9a-f]+:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0835951b[ 	]+slli\.uw[ 	]+a0,a1,0x3
 [ 	]+[0-9a-f]+:[ 	]+49f59513[ 	]+bclri[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+29f59513[ 	]+bseti[ 	]+a0,a1,0x1f
 [ 	]+[0-9a-f]+:[ 	]+69f59513[ 	]+binvi[ 	]+a0,a1,0x1f
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -971,6 +971,7 @@ const struct riscv_opcode riscv_opcodes[
 {"zext.w",    64, INSN_CLASS_ZBA,  "d,s",   MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
 {"zext.w",    64, INSN_CLASS_I, "d,s",       0, (int) M_ZEXTW, match_never, INSN_MACRO },
 {"add.uw",    64, INSN_CLASS_ZBA,  "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
+{"sll.uw",    64, INSN_CLASS_ZBA,  "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, INSN_ALIAS },
 {"slli.uw",   64, INSN_CLASS_ZBA,  "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
 
 /* Zbc or zbkc instructions.  */


^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 0/3] RISC-V: alias insn adjustments
  2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
                   ` (2 preceding siblings ...)
  2022-09-13 13:04 ` [PATCH 3/3] RISC-V: add alias for SLLI.UW Jan Beulich
@ 2022-09-13 14:54 ` Tsukasa OI
  2022-09-13 16:11   ` Jan Beulich
  2022-09-30  9:41 ` [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats" Jan Beulich
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 29+ messages in thread
From: Tsukasa OI @ 2022-09-13 14:54 UTC (permalink / raw)
  To: Jan Beulich, Binutils

On 2022/09/13 21:59, Jan Beulich via Binutils wrote:
> 1: re-arrange opcode table for consistent alias handling
> 2: drop stray INSN_ALIAS flags
> 3: add alias for SLLI.UW
> 
> In particular the 3rd patch may want considering to be at least slightly
> RFC.
> 
> Jan
> 

+1 to PATCH 1-2/3 except we can just add -M no-aliases to existing tests
zbkb-32.d and fence-tso.d just like my submission (they don't test any
aliases):

https://sourceware.org/pipermail/binutils/2022-July/121674.html

So except that I don't support adding fence-tso-na.d and zbkb-32-na.d,
that's okay.

Tsukasa

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 0/3] RISC-V: alias insn adjustments
  2022-09-13 14:54 ` [PATCH 0/3] RISC-V: alias insn adjustments Tsukasa OI
@ 2022-09-13 16:11   ` Jan Beulich
  2022-09-13 16:58     ` Tsukasa OI
  0 siblings, 1 reply; 29+ messages in thread
From: Jan Beulich @ 2022-09-13 16:11 UTC (permalink / raw)
  To: Tsukasa OI; +Cc: Binutils

On 13.09.2022 16:54, Tsukasa OI wrote:
> On 2022/09/13 21:59, Jan Beulich via Binutils wrote:
>> 1: re-arrange opcode table for consistent alias handling
>> 2: drop stray INSN_ALIAS flags
>> 3: add alias for SLLI.UW
>>
>> In particular the 3rd patch may want considering to be at least slightly
>> RFC.
>>
>> Jan
>>
> 
> +1 to PATCH 1-2/3 except we can just add -M no-aliases to existing tests
> zbkb-32.d and fence-tso.d just like my submission (they don't test any
> aliases):

I'd consider that wrong - disassembly should work correctly in both modes,
so both modes would better be tested. After all it was just one of the
two modes which didn't work.

One might further consider generalization, forcing most (all?) tests to be
done both ways.

> https://sourceware.org/pipermail/binutils/2022-July/121674.html

Oh, I guess I did see this earlier patch of yours and then forgot about
its existence, re-doing the work.

Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 0/3] RISC-V: alias insn adjustments
  2022-09-13 16:11   ` Jan Beulich
@ 2022-09-13 16:58     ` Tsukasa OI
  2022-09-14  6:26       ` Jan Beulich
  0 siblings, 1 reply; 29+ messages in thread
From: Tsukasa OI @ 2022-09-13 16:58 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Binutils

On 2022/09/14 1:11, Jan Beulich wrote:
> On 13.09.2022 16:54, Tsukasa OI wrote:
>> On 2022/09/13 21:59, Jan Beulich via Binutils wrote:
>>> 1: re-arrange opcode table for consistent alias handling
>>> 2: drop stray INSN_ALIAS flags
>>> 3: add alias for SLLI.UW
>>>
>>> In particular the 3rd patch may want considering to be at least slightly
>>> RFC.
>>>
>>> Jan
>>>
>>
>> +1 to PATCH 1-2/3 except we can just add -M no-aliases to existing tests
>> zbkb-32.d and fence-tso.d just like my submission (they don't test any
>> aliases):
> 
> I'd consider that wrong - disassembly should work correctly in both modes,
> so both modes would better be tested. After all it was just one of the
> two modes which didn't work.
> 
> One might further consider generalization, forcing most (all?) tests to be
> done both ways.

Good point and I'm convinced.  Then, how about using like "-noalias"
instead of "-na"?  I like the names that can be understood without
looking the source code and we rarely use acronyms on RISC-V GAS tests.

Thanks,
Tsukasa

> 
>> https://sourceware.org/pipermail/binutils/2022-July/121674.html
> 
> Oh, I guess I did see this earlier patch of yours and then forgot about
> its existence, re-doing the work.
> 
> Jan
> 

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 0/3] RISC-V: alias insn adjustments
  2022-09-13 16:58     ` Tsukasa OI
@ 2022-09-14  6:26       ` Jan Beulich
  0 siblings, 0 replies; 29+ messages in thread
From: Jan Beulich @ 2022-09-14  6:26 UTC (permalink / raw)
  To: Tsukasa OI
  Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

On 13.09.2022 18:58, Tsukasa OI wrote:
> On 2022/09/14 1:11, Jan Beulich wrote:
>> On 13.09.2022 16:54, Tsukasa OI wrote:
>>> On 2022/09/13 21:59, Jan Beulich via Binutils wrote:
>>>> 1: re-arrange opcode table for consistent alias handling
>>>> 2: drop stray INSN_ALIAS flags
>>>> 3: add alias for SLLI.UW
>>>>
>>>> In particular the 3rd patch may want considering to be at least slightly
>>>> RFC.
>>>>
>>>> Jan
>>>>
>>>
>>> +1 to PATCH 1-2/3 except we can just add -M no-aliases to existing tests
>>> zbkb-32.d and fence-tso.d just like my submission (they don't test any
>>> aliases):
>>
>> I'd consider that wrong - disassembly should work correctly in both modes,
>> so both modes would better be tested. After all it was just one of the
>> two modes which didn't work.
>>
>> One might further consider generalization, forcing most (all?) tests to be
>> done both ways.
> 
> Good point and I'm convinced.  Then, how about using like "-noalias"
> instead of "-na"?  I like the names that can be understood without
> looking the source code and we rarely use acronyms on RISC-V GAS tests.

Personally I prefer shorter names, but if arch maintainers agree with you,
I'd surely adjust.

Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2022-09-13 13:02 ` [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling Jan Beulich
@ 2022-09-15  2:30   ` Nelson Chu
  2022-09-15  7:42     ` Jan Beulich
  0 siblings, 1 reply; 29+ messages in thread
From: Nelson Chu @ 2022-09-15  2:30 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson

On Tue, Sep 13, 2022 at 9:02 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> For disassembly to pick up aliases in favor of underlying insns (helping
> readability in the common case), the aliases need to come ahead of the
> "base" insns. Slightly more code movement is needed because of insns
> with the same name needing to stay next to each other.
>
> Note that the "rorw" alias entry also has the missing INSN_ALIAS added
> here.
>
> Clone a few testcases to exercise -Mno-aliases some more, better
> covering the differences between the default and that disassembly mode.
>
> --- a/gas/testsuite/gas/riscv/b-ext.d
> +++ b/gas/testsuite/gas/riscv/b-ext.d
> @@ -23,8 +23,8 @@ Disassembly of section .text:
>  [      ]+30:[  ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
>  [      ]+34:[  ]+60c59533[     ]+rol[  ]+a0,a1,a2
>  [      ]+38:[  ]+60c5d533[     ]+ror[  ]+a0,a1,a2
> -[      ]+3c:[  ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> -[      ]+40:[  ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+3c:[  ]+6025d513[     ]+ror[  ]+a0,a1,0x2
> +[      ]+40:[  ]+6025d513[     ]+ror[  ]+a0,a1,0x2
>  [      ]+44:[  ]+69855513[     ]+rev8[         ]+a0,a0
>  [      ]+48:[  ]+28755513[     ]+orc.b[        ]+a0,a0
>  [      ]+4c:[  ]+20c5a533[     ]+sh1add[       ]+a0,a1,a2
> @@ -33,19 +33,19 @@ Disassembly of section .text:
>  [      ]+58:[  ]+0ac59533[     ]+clmul[        ]+a0,a1,a2
>  [      ]+5c:[  ]+0ac5b533[     ]+clmulh[       ]+a0,a1,a2
>  [      ]+60:[  ]+0ac5a533[     ]+clmulr[       ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+48059513[     ]+bclri[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+28059513[     ]+bseti[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+68059513[     ]+binvi[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+4805d513[     ]+bexti[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+48059513[     ]+bclr[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclr[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+28059513[     ]+bset[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bset[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+68059513[     ]+binv[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binv[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4805d513[     ]+bext[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bext[         ]+a0,a1,0x1f
>  [      ]+[0-9a-f]+:[   ]+48c59533[     ]+bclr[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+28c59533[     ]+bset[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+68c59533[     ]+binv[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+48c5d533[     ]+bext[         ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclr[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bset[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binv[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bext[         ]+a0,a1,0x1f
> --- a/gas/testsuite/gas/riscv/b-ext-64.d
> +++ b/gas/testsuite/gas/riscv/b-ext-64.d
> @@ -23,8 +23,8 @@ Disassembly of section .text:
>  [      ]+30:[  ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
>  [      ]+34:[  ]+60c59533[     ]+rol[  ]+a0,a1,a2
>  [      ]+38:[  ]+60c5d533[     ]+ror[  ]+a0,a1,a2
> -[      ]+3c:[  ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> -[      ]+40:[  ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+3c:[  ]+6025d513[     ]+ror[  ]+a0,a1,0x2
> +[      ]+40:[  ]+6025d513[     ]+ror[  ]+a0,a1,0x2
>  [      ]+44:[  ]+6b855513[     ]+rev8[         ]+a0,a0
>  [      ]+48:[  ]+28755513[     ]+orc.b[        ]+a0,a0
>  [      ]+4c:[  ]+20c5a533[     ]+sh1add[       ]+a0,a1,a2
> @@ -38,35 +38,35 @@ Disassembly of section .text:
>  [      ]+6c:[  ]+6025151b[     ]+cpopw[        ]+a0,a0
>  [      ]+70:[  ]+60c5953b[     ]+rolw[         ]+a0,a1,a2
>  [      ]+74:[  ]+60c5d53b[     ]+rorw[         ]+a0,a1,a2
> -[      ]+78:[  ]+6025d51b[     ]+roriw[        ]+a0,a1,0x2
> -[      ]+7c:[  ]+6025d51b[     ]+roriw[        ]+a0,a1,0x2
> +[      ]+78:[  ]+6025d51b[     ]+rorw[         ]+a0,a1,0x2
> +[      ]+7c:[  ]+6025d51b[     ]+rorw[         ]+a0,a1,0x2
>  [      ]+80:[  ]+20c5a53b[     ]+sh1add.uw[    ]+a0,a1,a2
>  [      ]+84:[  ]+20c5c53b[     ]+sh2add.uw[    ]+a0,a1,a2
>  [      ]+88:[  ]+20c5e53b[     ]+sh3add.uw[    ]+a0,a1,a2
>  [      ]+8c:[  ]+08c5853b[     ]+add.uw[       ]+a0,a1,a2
>  [      ]+90:[  ]+0805853b[     ]+zext.w[       ]+a0,a1
>  [      ]+94:[  ]+0825951b[     ]+slli.uw[      ]+a0,a1,0x2
> -[      ]+[0-9a-f]+:[   ]+48059513[     ]+bclri[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+28059513[     ]+bseti[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+68059513[     ]+binvi[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+4805d513[     ]+bexti[        ]+a0,a1,0x0
> -[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+4bf59513[     ]+bclri[        ]+a0,a1,0x3f
> -[      ]+[0-9a-f]+:[   ]+2bf59513[     ]+bseti[        ]+a0,a1,0x3f
> -[      ]+[0-9a-f]+:[   ]+6bf59513[     ]+binvi[        ]+a0,a1,0x3f
> -[      ]+[0-9a-f]+:[   ]+4bf5d513[     ]+bexti[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+48059513[     ]+bclr[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclr[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+28059513[     ]+bset[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bset[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+68059513[     ]+binv[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binv[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4805d513[     ]+bext[         ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bext[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4bf59513[     ]+bclr[         ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+2bf59513[     ]+bset[         ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+6bf59513[     ]+binv[         ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+4bf5d513[     ]+bext[         ]+a0,a1,0x3f
>  [      ]+[0-9a-f]+:[   ]+48c59533[     ]+bclr[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+28c59533[     ]+bset[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+68c59533[     ]+binv[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+48c5d533[     ]+bext[         ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> -[      ]+[0-9a-f]+:[   ]+4bf59513[     ]+bclri[        ]+a0,a1,0x3f
> -[      ]+[0-9a-f]+:[   ]+2bf59513[     ]+bseti[        ]+a0,a1,0x3f
> -[      ]+[0-9a-f]+:[   ]+6bf59513[     ]+binvi[        ]+a0,a1,0x3f
> -[      ]+[0-9a-f]+:[   ]+4bf5d513[     ]+bexti[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclr[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bset[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binv[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bext[         ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4bf59513[     ]+bclr[         ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+2bf59513[     ]+bset[         ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+6bf59513[     ]+binv[         ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+4bf5d513[     ]+bext[         ]+a0,a1,0x3f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/b-ext-64-na.d
> @@ -0,0 +1,72 @@
> +#as: -march=rv64i_zba_zbb_zbc_zbs
> +#source: b-ext-64.s
> +#objdump: -d -Mno-aliases
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[      ]+[0-9a-f]+:[   ]+60051513[     ]+clz[  ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+60151513[     ]+ctz[  ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+60251513[     ]+cpop[         ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+0ac5c533[     ]+min[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5d533[     ]+minu[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5e533[     ]+max[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5f533[     ]+maxu[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60451513[     ]+sext\.b[      ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+60551513[     ]+sext\.h[      ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+0805453b[     ]+zext\.h[      ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+40c5f533[     ]+andn[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+40c5e533[     ]+orn[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60c59533[     ]+rol[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60c5d533[     ]+ror[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6b855513[     ]+rev8[         ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+28755513[     ]+orc\.b[       ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+20c5a533[     ]+sh1add[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+20c5c533[     ]+sh2add[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+20c5e533[     ]+sh3add[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac59533[     ]+clmul[        ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5b533[     ]+clmulh[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5a533[     ]+clmulr[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+6005151b[     ]+clzw[         ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+6015151b[     ]+ctzw[         ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+6025151b[     ]+cpopw[        ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+60c5953b[     ]+rolw[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60c5d53b[     ]+rorw[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+6025d51b[     ]+roriw[        ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d51b[     ]+roriw[        ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+20c5a53b[     ]+sh1add\.uw[   ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+20c5c53b[     ]+sh2add\.uw[   ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+20c5e53b[     ]+sh3add\.uw[   ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+08c5853b[     ]+add\.uw[      ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0805853b[     ]+add\.uw[      ]+a0,a1,zero
> +[      ]+[0-9a-f]+:[   ]+0825951b[     ]+slli\.uw[     ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+48059513[     ]+bclri[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+28059513[     ]+bseti[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+68059513[     ]+binvi[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4805d513[     ]+bexti[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4bf59513[     ]+bclri[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+2bf59513[     ]+bseti[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+6bf59513[     ]+binvi[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+4bf5d513[     ]+bexti[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+48c59533[     ]+bclr[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+28c59533[     ]+bset[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+68c59533[     ]+binv[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+48c5d533[     ]+bext[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4bf59513[     ]+bclri[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+2bf59513[     ]+bseti[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+6bf59513[     ]+binvi[        ]+a0,a1,0x3f
> +[      ]+[0-9a-f]+:[   ]+4bf5d513[     ]+bexti[        ]+a0,a1,0x3f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/b-ext-na.d
> @@ -0,0 +1,51 @@
> +#as: -march=rv32i_zba_zbb_zbc_zbs
> +#source: b-ext.s
> +#objdump: -d -Mno-aliases
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[      ]+[0-9a-f]+:[   ]+60051513[     ]+clz[  ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+60151513[     ]+ctz[  ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+60251513[     ]+cpop[         ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+0ac5c533[     ]+min[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5d533[     ]+minu[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5e533[     ]+max[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5f533[     ]+maxu[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60451513[     ]+sext\.b[      ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+60551513[     ]+sext\.h[      ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+08054533[     ]+zext\.h[      ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+40c5f533[     ]+andn[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+40c5e533[     ]+orn[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60c59533[     ]+rol[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60c5d533[     ]+ror[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+69855513[     ]+rev8[         ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+28755513[     ]+orc\.b[       ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+20c5a533[     ]+sh1add[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+20c5c533[     ]+sh2add[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+20c5e533[     ]+sh3add[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac59533[     ]+clmul[        ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5b533[     ]+clmulh[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+0ac5a533[     ]+clmulr[       ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+48059513[     ]+bclri[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+28059513[     ]+bseti[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+68059513[     ]+binvi[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+4805d513[     ]+bexti[        ]+a0,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+48c59533[     ]+bclr[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+28c59533[     ]+bset[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+68c59533[     ]+binv[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+48c5d533[     ]+bext[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
> +[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
> --- a/gas/testsuite/gas/riscv/c-zero-imm.d
> +++ b/gas/testsuite/gas/riscv/c-zero-imm.d
> @@ -9,14 +9,14 @@ Disassembly of section .text:
>  0+000 <.text>:
>  [      ]+0:[   ]+4501[         ]+li[   ]+a0,0
>  [      ]+2:[   ]+4581[         ]+li[   ]+a1,0
> -[      ]+4:[   ]+8a01[         ]+andi[         ]+a2,a2,0
> -[      ]+6:[   ]+8a81[         ]+andi[         ]+a3,a3,0
> +[      ]+4:[   ]+8a01[         ]+and[  ]+a2,a2,0
> +[      ]+6:[   ]+8a81[         ]+and[  ]+a3,a3,0
>  [      ]+8:[   ]+0001[         ]+nop
>  [      ]+a:[   ]+873a[         ]+mv[   ]+a4,a4
> -[      ]+c:[   ]+0781[         ]+addi[         ]+a5,a5,0
> -[      ]+e:[   ]+00051513[     ]+slli[         ]+a0,a0,0x0
> -[      ]+12:[  ]+0005d593[     ]+srli[         ]+a1,a1,0x0
> -[      ]+16:[  ]+40065613[     ]+srai[         ]+a2,a2,0x0
> +[      ]+c:[   ]+0781[         ]+add[  ]+a5,a5,0
> +[      ]+e:[   ]+00051513[     ]+sll[  ]+a0,a0,0x0
> +[      ]+12:[  ]+0005d593[     ]+srl[  ]+a1,a1,0x0
> +[      ]+16:[  ]+40065613[     ]+sra[  ]+a2,a2,0x0
>  [      ]+1a:[  ]+0682[         ]+c.slli64[     ]+a3
>  [      ]+1c:[  ]+8301[         ]+c.srli64[     ]+a4
>  [      ]+1e:[  ]+8781[         ]+c.srai64[     ]+a5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/c-zero-imm-na.d
> @@ -0,0 +1,24 @@
> +#as:
> +#source: c-zero-imm.s
> +#objdump: -dr -Mno-aliases
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
> +[      ]+[0-9a-f]+:[   ]+4501[         ]+c\.li[        ]+a0,0
> +[      ]+[0-9a-f]+:[   ]+4581[         ]+c\.li[        ]+a1,0
> +[      ]+[0-9a-f]+:[   ]+8a01[         ]+c\.andi[      ]+a2,0
> +[      ]+[0-9a-f]+:[   ]+8a81[         ]+c\.andi[      ]+a3,0
> +[      ]+[0-9a-f]+:[   ]+0001[         ]+c\.addi[      ]+zero,0
> +[      ]+[0-9a-f]+:[   ]+873a[         ]+c\.mv[        ]+a4,a4
> +[      ]+[0-9a-f]+:[   ]+0781[         ]+c\.addi[      ]+a5,0
> +[      ]+[0-9a-f]+:[   ]+00051513[     ]+slli[         ]+a0,a0,0x0
> +[      ]+[0-9a-f]+:[   ]+0005d593[     ]+srli[         ]+a1,a1,0x0
> +[      ]+[0-9a-f]+:[   ]+40065613[     ]+srai[         ]+a2,a2,0x0
> +[      ]+[0-9a-f]+:[   ]+0682[         ]+c\.slli64[    ]+a3
> +[      ]+[0-9a-f]+:[   ]+8301[         ]+c\.srli64[    ]+a4
> +[      ]+[0-9a-f]+:[   ]+8781[         ]+c\.srai64[    ]+a5
> +#...
> --- a/gas/testsuite/gas/riscv/c-zero-reg.d
> +++ b/gas/testsuite/gas/riscv/c-zero-reg.d
> @@ -14,7 +14,7 @@ Disassembly of section .text:
>  [      ]+8:[   ]+9006[         ]+c.add[        ]+zero,ra
>  [      ]+a:[   ]+00500013[     ]+li[   ]+zero,5
>  [      ]+e:[   ]+00006037[     ]+lui[  ]+zero,0x6
> -[      ]+12:[  ]+00701013[     ]+slli[         ]+zero,zero,0x7
> +[      ]+12:[  ]+00701013[     ]+sll[  ]+zero,zero,0x7
>  [      ]+16:[  ]+00008013[     ]+mv[   ]+zero,ra
>  [      ]+1a:[  ]+00100033[     ]+add[  ]+zero,zero,ra
>  #...
> --- a/gas/testsuite/gas/riscv/csr-insns-pseudo.d
> +++ b/gas/testsuite/gas/riscv/csr-insns-pseudo.d
> @@ -12,9 +12,9 @@ Disassembly of section .text:
>  [      ]+[0-9a-f]+:[   ]+00029073[     ]+csrw[         ]+ustatus,t0
>  [      ]+[0-9a-f]+:[   ]+0002a073[     ]+csrs[         ]+ustatus,t0
>  [      ]+[0-9a-f]+:[   ]+0002b073[     ]+csrc[         ]+ustatus,t0
> -[      ]+[0-9a-f]+:[   ]+000fd073[     ]+csrwi[        ]+ustatus,31
> -[      ]+[0-9a-f]+:[   ]+000fe073[     ]+csrsi[        ]+ustatus,31
> -[      ]+[0-9a-f]+:[   ]+000ff073[     ]+csrci[        ]+ustatus,31
> +[      ]+[0-9a-f]+:[   ]+000fd073[     ]+csrw[         ]+ustatus,31
> +[      ]+[0-9a-f]+:[   ]+000fe073[     ]+csrs[         ]+ustatus,31
> +[      ]+[0-9a-f]+:[   ]+000ff073[     ]+csrc[         ]+ustatus,31
>  [      ]+[0-9a-f]+:[   ]+c00022f3[     ]+rdcycle[      ]+t0
>  [      ]+[0-9a-f]+:[   ]+c01022f3[     ]+rdtime[       ]+t0
>  [      ]+[0-9a-f]+:[   ]+c02022f3[     ]+rdinstret[    ]+t0
> --- a/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d
> +++ b/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d
> @@ -12,9 +12,9 @@ Disassembly of section .text:
>  [      ]+[0-9a-f]+:[   ]+00029073[     ]+csrw[         ]+ustatus,t0
>  [      ]+[0-9a-f]+:[   ]+0002a073[     ]+csrs[         ]+ustatus,t0
>  [      ]+[0-9a-f]+:[   ]+0002b073[     ]+csrc[         ]+ustatus,t0
> -[      ]+[0-9a-f]+:[   ]+000fd073[     ]+csrwi[        ]+ustatus,31
> -[      ]+[0-9a-f]+:[   ]+000fe073[     ]+csrsi[        ]+ustatus,31
> -[      ]+[0-9a-f]+:[   ]+000ff073[     ]+csrci[        ]+ustatus,31
> +[      ]+[0-9a-f]+:[   ]+000fd073[     ]+csrw[         ]+ustatus,31
> +[      ]+[0-9a-f]+:[   ]+000fe073[     ]+csrs[         ]+ustatus,31
> +[      ]+[0-9a-f]+:[   ]+000ff073[     ]+csrc[         ]+ustatus,31
>  [      ]+[0-9a-f]+:[   ]+c00022f3[     ]+rdcycle[      ]+t0
>  [      ]+[0-9a-f]+:[   ]+c01022f3[     ]+rdtime[       ]+t0
>  [      ]+[0-9a-f]+:[   ]+c02022f3[     ]+rdinstret[    ]+t0
> --- a/gas/testsuite/gas/riscv/ext-32.d
> +++ b/gas/testsuite/gas/riscv/ext-32.d
> @@ -9,31 +9,31 @@ Disassembly of section .text:
>
>  0+000 <target>:
>  [      ]+0:[   ]+0ff57513[     ]+zext.b[       ]+a0,a0
> -[      ]+4:[   ]+01051513[     ]+slli[         ]+a0,a0,0x10
> -[      ]+8:[   ]+01055513[     ]+srli[         ]+a0,a0,0x10
> -[      ]+c:[   ]+01851513[     ]+slli[         ]+a0,a0,0x18
> -[      ]+10:[  ]+41855513[     ]+srai[         ]+a0,a0,0x18
> -[      ]+14:[  ]+01051513[     ]+slli[         ]+a0,a0,0x10
> -[      ]+18:[  ]+41055513[     ]+srai[         ]+a0,a0,0x10
> +[      ]+4:[   ]+01051513[     ]+sll[  ]+a0,a0,0x10
> +[      ]+8:[   ]+01055513[     ]+srl[  ]+a0,a0,0x10
> +[      ]+c:[   ]+01851513[     ]+sll[  ]+a0,a0,0x18
> +[      ]+10:[  ]+41855513[     ]+sra[  ]+a0,a0,0x18
> +[      ]+14:[  ]+01051513[     ]+sll[  ]+a0,a0,0x10
> +[      ]+18:[  ]+41055513[     ]+sra[  ]+a0,a0,0x10
>  [      ]+1c:[  ]+0ff67593[     ]+zext.b[       ]+a1,a2
> -[      ]+20:[  ]+01061593[     ]+slli[         ]+a1,a2,0x10
> -[      ]+24:[  ]+0105d593[     ]+srli[         ]+a1,a1,0x10
> -[      ]+28:[  ]+01861593[     ]+slli[         ]+a1,a2,0x18
> -[      ]+2c:[  ]+4185d593[     ]+srai[         ]+a1,a1,0x18
> -[      ]+30:[  ]+01061593[     ]+slli[         ]+a1,a2,0x10
> -[      ]+34:[  ]+4105d593[     ]+srai[         ]+a1,a1,0x10
> +[      ]+20:[  ]+01061593[     ]+sll[  ]+a1,a2,0x10
> +[      ]+24:[  ]+0105d593[     ]+srl[  ]+a1,a1,0x10
> +[      ]+28:[  ]+01861593[     ]+sll[  ]+a1,a2,0x18
> +[      ]+2c:[  ]+4185d593[     ]+sra[  ]+a1,a1,0x18
> +[      ]+30:[  ]+01061593[     ]+sll[  ]+a1,a2,0x10
> +[      ]+34:[  ]+4105d593[     ]+sra[  ]+a1,a1,0x10
>  [      ]+38:[  ]+0ff57513[     ]+zext.b[       ]+a0,a0
> -[      ]+3c:[  ]+0542[         ]+slli[         ]+a0,a0,0x10
> -[      ]+3e:[  ]+8141[         ]+srli[         ]+a0,a0,0x10
> -[      ]+40:[  ]+0562[         ]+slli[         ]+a0,a0,0x18
> -[      ]+42:[  ]+8561[         ]+srai[         ]+a0,a0,0x18
> -[      ]+44:[  ]+0542[         ]+slli[         ]+a0,a0,0x10
> -[      ]+46:[  ]+8541[         ]+srai[         ]+a0,a0,0x10
> +[      ]+3c:[  ]+0542[         ]+sll[  ]+a0,a0,0x10
> +[      ]+3e:[  ]+8141[         ]+srl[  ]+a0,a0,0x10
> +[      ]+40:[  ]+0562[         ]+sll[  ]+a0,a0,0x18
> +[      ]+42:[  ]+8561[         ]+sra[  ]+a0,a0,0x18
> +[      ]+44:[  ]+0542[         ]+sll[  ]+a0,a0,0x10
> +[      ]+46:[  ]+8541[         ]+sra[  ]+a0,a0,0x10
>  [      ]+48:[  ]+0ff67593[     ]+zext.b[       ]+a1,a2
> -[      ]+4c:[  ]+01061593[     ]+slli[         ]+a1,a2,0x10
> -[      ]+50:[  ]+81c1[         ]+srli[         ]+a1,a1,0x10
> -[      ]+52:[  ]+01861593[     ]+slli[         ]+a1,a2,0x18
> -[      ]+56:[  ]+85e1[         ]+srai[         ]+a1,a1,0x18
> -[      ]+58:[  ]+01061593[     ]+slli[         ]+a1,a2,0x10
> -[      ]+5c:[  ]+85c1[         ]+srai[         ]+a1,a1,0x10
> +[      ]+4c:[  ]+01061593[     ]+sll[  ]+a1,a2,0x10
> +[      ]+50:[  ]+81c1[         ]+srl[  ]+a1,a1,0x10
> +[      ]+52:[  ]+01861593[     ]+sll[  ]+a1,a2,0x18
> +[      ]+56:[  ]+85e1[         ]+sra[  ]+a1,a1,0x18
> +[      ]+58:[  ]+01061593[     ]+sll[  ]+a1,a2,0x10
> +[      ]+5c:[  ]+85c1[         ]+sra[  ]+a1,a1,0x10
>  #...
> --- a/gas/testsuite/gas/riscv/ext-64.d
> +++ b/gas/testsuite/gas/riscv/ext-64.d
> @@ -9,43 +9,43 @@ Disassembly of section .text:
>
>  0+000 <target>:
>  [      ]+0:[   ]+0ff57513[     ]+zext.b[       ]+a0,a0
> -[      ]+4:[   ]+03051513[     ]+slli[         ]+a0,a0,0x30
> -[      ]+8:[   ]+03055513[     ]+srli[         ]+a0,a0,0x30
> -[      ]+c:[   ]+03851513[     ]+slli[         ]+a0,a0,0x38
> -[      ]+10:[  ]+43855513[     ]+srai[         ]+a0,a0,0x38
> -[      ]+14:[  ]+03051513[     ]+slli[         ]+a0,a0,0x30
> -[      ]+18:[  ]+43055513[     ]+srai[         ]+a0,a0,0x30
> +[      ]+4:[   ]+03051513[     ]+sll[  ]+a0,a0,0x30
> +[      ]+8:[   ]+03055513[     ]+srl[  ]+a0,a0,0x30
> +[      ]+c:[   ]+03851513[     ]+sll[  ]+a0,a0,0x38
> +[      ]+10:[  ]+43855513[     ]+sra[  ]+a0,a0,0x38
> +[      ]+14:[  ]+03051513[     ]+sll[  ]+a0,a0,0x30
> +[      ]+18:[  ]+43055513[     ]+sra[  ]+a0,a0,0x30
>  [      ]+1c:[  ]+0ff67593[     ]+zext.b[       ]+a1,a2
> -[      ]+20:[  ]+03061593[     ]+slli[         ]+a1,a2,0x30
> -[      ]+24:[  ]+0305d593[     ]+srli[         ]+a1,a1,0x30
> -[      ]+28:[  ]+03861593[     ]+slli[         ]+a1,a2,0x38
> -[      ]+2c:[  ]+4385d593[     ]+srai[         ]+a1,a1,0x38
> -[      ]+30:[  ]+03061593[     ]+slli[         ]+a1,a2,0x30
> -[      ]+34:[  ]+4305d593[     ]+srai[         ]+a1,a1,0x30
> -[      ]+38:[  ]+02051513[     ]+slli[         ]+a0,a0,0x20
> -[      ]+3c:[  ]+02055513[     ]+srli[         ]+a0,a0,0x20
> +[      ]+20:[  ]+03061593[     ]+sll[  ]+a1,a2,0x30
> +[      ]+24:[  ]+0305d593[     ]+srl[  ]+a1,a1,0x30
> +[      ]+28:[  ]+03861593[     ]+sll[  ]+a1,a2,0x38
> +[      ]+2c:[  ]+4385d593[     ]+sra[  ]+a1,a1,0x38
> +[      ]+30:[  ]+03061593[     ]+sll[  ]+a1,a2,0x30
> +[      ]+34:[  ]+4305d593[     ]+sra[  ]+a1,a1,0x30
> +[      ]+38:[  ]+02051513[     ]+sll[  ]+a0,a0,0x20
> +[      ]+3c:[  ]+02055513[     ]+srl[  ]+a0,a0,0x20
>  [      ]+40:[  ]+0005051b[     ]+sext.w[       ]+a0,a0
> -[      ]+44:[  ]+02061593[     ]+slli[         ]+a1,a2,0x20
> -[      ]+48:[  ]+0205d593[     ]+srli[         ]+a1,a1,0x20
> +[      ]+44:[  ]+02061593[     ]+sll[  ]+a1,a2,0x20
> +[      ]+48:[  ]+0205d593[     ]+srl[  ]+a1,a1,0x20
>  [      ]+4c:[  ]+0006059b[     ]+sext.w[       ]+a1,a2
>  [      ]+50:[  ]+0ff57513[     ]+zext.b[       ]+a0,a0
> -[      ]+54:[  ]+1542[         ]+slli[         ]+a0,a0,0x30
> -[      ]+56:[  ]+9141[         ]+srli[         ]+a0,a0,0x30
> -[      ]+58:[  ]+1562[         ]+slli[         ]+a0,a0,0x38
> -[      ]+5a:[  ]+9561[         ]+srai[         ]+a0,a0,0x38
> -[      ]+5c:[  ]+1542[         ]+slli[         ]+a0,a0,0x30
> -[      ]+5e:[  ]+9541[         ]+srai[         ]+a0,a0,0x30
> +[      ]+54:[  ]+1542[         ]+sll[  ]+a0,a0,0x30
> +[      ]+56:[  ]+9141[         ]+srl[  ]+a0,a0,0x30
> +[      ]+58:[  ]+1562[         ]+sll[  ]+a0,a0,0x38
> +[      ]+5a:[  ]+9561[         ]+sra[  ]+a0,a0,0x38
> +[      ]+5c:[  ]+1542[         ]+sll[  ]+a0,a0,0x30
> +[      ]+5e:[  ]+9541[         ]+sra[  ]+a0,a0,0x30
>  [      ]+60:[  ]+0ff67593[     ]+zext.b[       ]+a1,a2
> -[      ]+64:[  ]+03061593[     ]+slli[         ]+a1,a2,0x30
> -[      ]+68:[  ]+91c1[         ]+srli[         ]+a1,a1,0x30
> -[      ]+6a:[  ]+03861593[     ]+slli[         ]+a1,a2,0x38
> -[      ]+6e:[  ]+95e1[         ]+srai[         ]+a1,a1,0x38
> -[      ]+70:[  ]+03061593[     ]+slli[         ]+a1,a2,0x30
> -[      ]+74:[  ]+95c1[         ]+srai[         ]+a1,a1,0x30
> -[      ]+76:[  ]+1502[         ]+slli[         ]+a0,a0,0x20
> -[      ]+78:[  ]+9101[         ]+srli[         ]+a0,a0,0x20
> +[      ]+64:[  ]+03061593[     ]+sll[  ]+a1,a2,0x30
> +[      ]+68:[  ]+91c1[         ]+srl[  ]+a1,a1,0x30
> +[      ]+6a:[  ]+03861593[     ]+sll[  ]+a1,a2,0x38
> +[      ]+6e:[  ]+95e1[         ]+sra[  ]+a1,a1,0x38
> +[      ]+70:[  ]+03061593[     ]+sll[  ]+a1,a2,0x30
> +[      ]+74:[  ]+95c1[         ]+sra[  ]+a1,a1,0x30
> +[      ]+76:[  ]+1502[         ]+sll[  ]+a0,a0,0x20
> +[      ]+78:[  ]+9101[         ]+srl[  ]+a0,a0,0x20
>  [      ]+7a:[  ]+2501[         ]+sext.w[       ]+a0,a0
> -[      ]+7c:[  ]+02061593[     ]+slli[         ]+a1,a2,0x20
> -[      ]+80:[  ]+9181[         ]+srli[         ]+a1,a1,0x20
> +[      ]+7c:[  ]+02061593[     ]+sll[  ]+a1,a2,0x20
> +[      ]+80:[  ]+9181[         ]+srl[  ]+a1,a1,0x20
>  [      ]+82:[  ]+0006059b[     ]+sext.w[       ]+a1,a2
>  #...
> --- a/gas/testsuite/gas/riscv/insn.d
> +++ b/gas/testsuite/gas/riscv/insn.d
> @@ -8,7 +8,7 @@ Disassembly of section .text:
>
>  0+000 <target>:
>  [^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> -[^:]+:[        ]+00d58513[     ]+addi[         ]+a0,a1,13
> +[^:]+:[        ]+00d58513[     ]+add[  ]+a0,a1,13
>  [^:]+:[        ]+00a58567[     ]+jalr[         ]+a0,10\(a1\)
>  [^:]+:[        ]+00458503[     ]+lb[   ]+a0,4\(a1\)
>  [^:]+:[        ]+feb508e3[     ]+beq[  ]+a0,a1,0 \<target\>
> @@ -22,8 +22,8 @@ Disassembly of section .text:
>  [^:]+:[        ]+fddff56f[     ]+jal[  ]+a0,0 \<target\>
>  [^:]+: R_RISCV_JAL[    ]+target
>  [^:]+:[        ]+852e[         ]+mv[   ]+a0,a1
> -[^:]+:[        ]+0511[         ]+addi[         ]+a0,a0,4 # .*
> -[^:]+:[        ]+002c[         ]+addi[         ]+a1,sp,8
> +[^:]+:[        ]+0511[         ]+add[  ]+a0,a0,4 # .*
> +[^:]+:[        ]+002c[         ]+add[  ]+a1,sp,8
>  [^:]+:[        ]+c0aa[         ]+sw[   ]+a0,64\(sp\)
>  [^:]+:[        ]+41a8[         ]+lw[   ]+a0,64\(a1\)
>  [^:]+:[        ]+c1a8[         ]+sw[   ]+a0,64\(a1\)
> @@ -32,7 +32,7 @@ Disassembly of section .text:
>  [^:]+:[        ]+b7e9[         ]+j[    ]+0 \<target\>
>  [^:]+: R_RISCV_RVC_JUMP[       ]+target
>  [^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> -[^:]+:[        ]+00d58513[     ]+addi[         ]+a0,a1,13
> +[^:]+:[        ]+00d58513[     ]+add[  ]+a0,a1,13
>  [^:]+:[        ]+00a58567[     ]+jalr[         ]+a0,10\(a1\)
>  [^:]+:[        ]+00458503[     ]+lb[   ]+a0,4\(a1\)
>  [^:]+:[        ]+fab50ce3[     ]+beq[  ]+a0,a1,0 \<target\>
> @@ -46,8 +46,8 @@ Disassembly of section .text:
>  [^:]+:[        ]+fa5ff56f[     ]+jal[  ]+a0,0 \<target\>
>  [^:]+: R_RISCV_JAL[    ]+target
>  [^:]+:[        ]+852e[         ]+mv[   ]+a0,a1
> -[^:]+:[        ]+0511[         ]+addi[         ]+a0,a0,4 # .*
> -[^:]+:[        ]+002c[         ]+addi[         ]+a1,sp,8
> +[^:]+:[        ]+0511[         ]+add[  ]+a0,a0,4 # .*
> +[^:]+:[        ]+002c[         ]+add[  ]+a1,sp,8
>  [^:]+:[        ]+c0aa[         ]+sw[   ]+a0,64\(sp\)
>  [^:]+:[        ]+41a8[         ]+lw[   ]+a0,64\(a1\)
>  [^:]+:[        ]+c1a8[         ]+sw[   ]+a0,64\(a1\)
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/insn-na.d
> @@ -0,0 +1,69 @@
> +#as: -march=rv32ifcv
> +#source: insn.s
> +#objdump: -dw -Mno-aliases
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00d58513[     ]+addi[         ]+a0,a1,13
> +[^:]+:[        ]+00a58567[     ]+jalr[         ]+a0,10\(a1\)
> +[^:]+:[        ]+00458503[     ]+lb[   ]+a0,4\(a1\)
> +[^:]+:[        ]+feb508e3[     ]+beq[  ]+a0,a1,0 \<target\>
> +[^:]+:[        ]+feb506e3[     ]+beq[  ]+a0,a1,0 \<target\>
> +[^:]+:[        ]+00a58223[     ]+sb[   ]+a0,4\(a1\)
> +[^:]+:[        ]+00fff537[     ]+lui[  ]+a0,0xfff
> +[^:]+:[        ]+fe1ff56f[     ]+jal[  ]+a0,0 \<target\>
> +[^:]+:[        ]+fddff56f[     ]+jal[  ]+a0,0 \<target\>
> +[^:]+:[        ]+852e[         ]+c\.mv[        ]+a0,a1
> +[^:]+:[        ]+0511[         ]+c\.addi[      ]+a0,4 # .*
> +[^:]+:[        ]+002c[         ]+c\.addi4spn[  ]+a1,sp,8
> +[^:]+:[        ]+c0aa[         ]+c\.swsp[      ]+a0,64\(sp\)
> +[^:]+:[        ]+41a8[         ]+c\.lw[        ]+a0,64\(a1\)
> +[^:]+:[        ]+c1a8[         ]+c\.sw[        ]+a0,64\(a1\)
> +[^:]+:[        ]+d5f1[         ]+c\.beqz[      ]+a1,0 \<target\>
> +[^:]+:[        ]+b7e9[         ]+c\.j[         ]+0 \<target\>
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00d58513[     ]+addi[         ]+a0,a1,13
> +[^:]+:[        ]+00a58567[     ]+jalr[         ]+a0,10\(a1\)
> +[^:]+:[        ]+00458503[     ]+lb[   ]+a0,4\(a1\)
> +[^:]+:[        ]+fab50ce3[     ]+beq[  ]+a0,a1,0 \<target\>
> +[^:]+:[        ]+fab50ae3[     ]+beq[  ]+a0,a1,0 \<target\>
> +[^:]+:[        ]+00a58223[     ]+sb[   ]+a0,4\(a1\)
> +[^:]+:[        ]+00fff537[     ]+lui[  ]+a0,0xfff
> +[^:]+:[        ]+fa9ff56f[     ]+jal[  ]+a0,0 \<target\>
> +[^:]+:[        ]+fa5ff56f[     ]+jal[  ]+a0,0 \<target\>
> +[^:]+:[        ]+852e[         ]+c\.mv[        ]+a0,a1
> +[^:]+:[        ]+0511[         ]+c\.addi[      ]+a0,4 # .*
> +[^:]+:[        ]+002c[         ]+c\.addi4spn[  ]+a1,sp,8
> +[^:]+:[        ]+c0aa[         ]+c\.swsp[      ]+a0,64\(sp\)
> +[^:]+:[        ]+41a8[         ]+c\.lw[        ]+a0,64\(a1\)
> +[^:]+:[        ]+c1a8[         ]+c\.sw[        ]+a0,64\(a1\)
> +[^:]+:[        ]+8d6d[         ]+c\.and[       ]+a0,a1
> +[^:]+:[        ]+d9c9[         ]+c\.beqz[      ]+a1,0 \<target\>
> +[^:]+:[        ]+bf41[         ]+c\.j[         ]+0 \<target\>
> +[^:]+:[        ]+68c58543[     ]+fmadd\.s[     ]+fa0,fa1,fa2,fa3,rne
> +[^:]+:[        ]+68c58543[     ]+fmadd\.s[     ]+fa0,fa1,fa2,fa3,rne
> +[^:]+:[        ]+68c58543[     ]+fmadd\.s[     ]+fa0,fa1,fa2,fa3,rne
> +[^:]+:[        ]+68c58543[     ]+fmadd\.s[     ]+fa0,fa1,fa2,fa3,rne
> +[^:]+:[        ]+68c58543[     ]+fmadd\.s[     ]+fa0,fa1,fa2,fa3,rne
> +[^:]+:[        ]+68c58543[     ]+fmadd\.s[     ]+fa0,fa1,fa2,fa3,rne
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+00c58533[     ]+add[  ]+a0,a1,a2
> +[^:]+:[        ]+022180d7[     ]+vadd\.vv[     ]+v1,v2,v3
> +[^:]+:[        ]+0001[         ]+c\.addi[      ]+zero,0
> +[^:]+:[        ]+00000013[     ]+addi[         ]+zero,zero,0
> +[^:]+:[        ]+001f 0000 0000[       ].*
> +[^:]+:[        ]+0000003f 00000000[    ].*
> +[^:]+:[        ]+0001[         ]+c\.addi[      ]+zero,0
> +[^:]+:[        ]+00000013[     ]+addi[         ]+zero,zero,0
> +[^:]+:[        ]+001f 0000 0000[       ].*
> +[^:]+:[        ]+0000003f 00000000[    ].*
> --- a/gas/testsuite/gas/riscv/k-ext-64.d
> +++ b/gas/testsuite/gas/riscv/k-ext-64.d
> @@ -10,10 +10,10 @@ Disassembly of section .text:
>  0+000 <target>:
>  [      ]+[0-9a-f]+:[   ]+60c5d533[     ]+ror[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+60c59533[     ]+rol[  ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+ror[  ]+a0,a1,0x2
>  [      ]+[0-9a-f]+:[   ]+60c5d53b[     ]+rorw[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+60c5953b[     ]+rolw[         ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+6025d51b[     ]+roriw[        ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d51b[     ]+rorw[         ]+a0,a1,0x2
>  [      ]+[0-9a-f]+:[   ]+40c5f533[     ]+andn[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5e533[     ]+orn[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
> --- a/gas/testsuite/gas/riscv/k-ext.d
> +++ b/gas/testsuite/gas/riscv/k-ext.d
> @@ -10,7 +10,7 @@ Disassembly of section .text:
>  0+000 <target>:
>  [      ]+[0-9a-f]+:[   ]+60c5d533[     ]+ror[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+60c59533[     ]+rol[  ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+ror[  ]+a0,a1,0x2
>  [      ]+[0-9a-f]+:[   ]+40c5f533[     ]+andn[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5e533[     ]+orn[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
> --- a/gas/testsuite/gas/riscv/li32.d
> +++ b/gas/testsuite/gas/riscv/li32.d
> @@ -8,10 +8,10 @@ Disassembly of section .text:
>
>  0+000 <target>:
>  [^:]+:[        ]+6521[         ]+lui[  ]+a0,0x8
> -[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1 # .*
> +[^:]+:[        ]+0505[         ]+add[  ]+a0,a0,1 # .*
>  [^:]+:[        ]+6509[         ]+lui[  ]+a0,0x2
> -[^:]+:[        ]+f0150513[     ]+addi[         ]+a0,a0,-255 # .*
> +[^:]+:[        ]+f0150513[     ]+add[  ]+a0,a0,-255 # .*
>  [^:]+:[        ]+12345537[     ]+lui[  ]+a0,0x12345
> -[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1 # .*
> +[^:]+:[        ]+0505[         ]+add[  ]+a0,a0,1 # .*
>  [^:]+:[        ]+f2345537[     ]+lui[  ]+a0,0xf2345
> -[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1 # .*
> +[^:]+:[        ]+0505[         ]+add[  ]+a0,a0,1 # .*
> --- a/gas/testsuite/gas/riscv/li64.d
> +++ b/gas/testsuite/gas/riscv/li64.d
> @@ -8,37 +8,37 @@ Disassembly of section .text:
>
>  0000000000000000 <target>:
>  [^:]+:[        ]+6521[         ]+lui[  ]+a0,0x8
> -[^:]+:[        ]+2505[         ]+addiw[        ]+a0,a0,1 # .*
> +[^:]+:[        ]+2505[         ]+addw[         ]+a0,a0,1 # .*
>  [^:]+:[        ]+6509[         ]+lui[  ]+a0,0x2
> -[^:]+:[        ]+f015051b[     ]+addiw[        ]+a0,a0,-255 # .*
> +[^:]+:[        ]+f015051b[     ]+addw[         ]+a0,a0,-255 # .*
>  [^:]+:[        ]+12345537[     ]+lui[  ]+a0,0x12345
> -[^:]+:[        ]+2505[         ]+addiw[        ]+a0,a0,1 # .*
> +[^:]+:[        ]+2505[         ]+addw[         ]+a0,a0,1 # .*
>  [^:]+:[        ]+000f2537[     ]+lui[  ]+a0,0xf2
> -[^:]+:[        ]+3455051b[     ]+addiw[        ]+a0,a0,837 # .*
> -[^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
> -[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
> +[^:]+:[        ]+3455051b[     ]+addw[         ]+a0,a0,837 # .*
> +[^:]+:[        ]+0532[         ]+sll[  ]+a0,a0,0xc
> +[^:]+:[        ]+0505[         ]+add[  ]+a0,a0,1
>  [^:]+:[        ]+00f12537[     ]+lui[  ]+a0,0xf12
> -[^:]+:[        ]+3455051b[     ]+addiw[        ]+a0,a0,837 # .*
> -[^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
> -[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
> +[^:]+:[        ]+3455051b[     ]+addw[         ]+a0,a0,837 # .*
> +[^:]+:[        ]+0532[         ]+sll[  ]+a0,a0,0xc
> +[^:]+:[        ]+0505[         ]+add[  ]+a0,a0,1
>  [^:]+:[        ]+ff010537[     ]+lui[  ]+a0,0xff010
> -[^:]+:[        ]+f015051b[     ]+addiw[        ]+a0,a0,-255 # .*
> -[^:]+:[        ]+054e[         ]+slli[         ]+a0,a0,0x13
> -[^:]+:[        ]+80150513[     ]+addi[         ]+a0,a0,-2047
> -[^:]+:[        ]+0536[         ]+slli[         ]+a0,a0,0xd
> -[^:]+:[        ]+f0150513[     ]+addi[         ]+a0,a0,-255
> -[^:]+:[        ]+0010051b[     ]+addiw[        ]+a0,zero,1
> -[^:]+:[        ]+151a[         ]+slli[         ]+a0,a0,0x26
> -[^:]+:[        ]+1565[         ]+addi[         ]+a0,a0,-7
> -[^:]+:[        ]+0536[         ]+slli[         ]+a0,a0,0xd
> -[^:]+:[        ]+34550513[     ]+addi[         ]+a0,a0,837
> -[^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
> -[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
> +[^:]+:[        ]+f015051b[     ]+addw[         ]+a0,a0,-255 # .*
> +[^:]+:[        ]+054e[         ]+sll[  ]+a0,a0,0x13
> +[^:]+:[        ]+80150513[     ]+add[  ]+a0,a0,-2047
> +[^:]+:[        ]+0536[         ]+sll[  ]+a0,a0,0xd
> +[^:]+:[        ]+f0150513[     ]+add[  ]+a0,a0,-255
> +[^:]+:[        ]+0010051b[     ]+addw[         ]+a0,zero,1
> +[^:]+:[        ]+151a[         ]+sll[  ]+a0,a0,0x26
> +[^:]+:[        ]+1565[         ]+add[  ]+a0,a0,-7
> +[^:]+:[        ]+0536[         ]+sll[  ]+a0,a0,0xd
> +[^:]+:[        ]+34550513[     ]+add[  ]+a0,a0,837
> +[^:]+:[        ]+0532[         ]+sll[  ]+a0,a0,0xc
> +[^:]+:[        ]+0505[         ]+add[  ]+a0,a0,1
>  [^:]+:[        ]+01fc4537[     ]+lui[  ]+a0,0x1fc4
> -[^:]+:[        ]+c915051b[     ]+addiw[        ]+a0,a0,-879 # .*
> -[^:]+:[        ]+0536[         ]+slli[         ]+a0,a0,0xd
> -[^:]+:[        ]+1565[         ]+addi[         ]+a0,a0,-7
> -[^:]+:[        ]+0536[         ]+slli[         ]+a0,a0,0xd
> -[^:]+:[        ]+34550513[     ]+addi[         ]+a0,a0,837
> -[^:]+:[        ]+0532[         ]+slli[         ]+a0,a0,0xc
> -[^:]+:[        ]+0505[         ]+addi[         ]+a0,a0,1
> +[^:]+:[        ]+c915051b[     ]+addw[         ]+a0,a0,-879 # .*
> +[^:]+:[        ]+0536[         ]+sll[  ]+a0,a0,0xd
> +[^:]+:[        ]+1565[         ]+add[  ]+a0,a0,-7
> +[^:]+:[        ]+0536[         ]+sll[  ]+a0,a0,0xd
> +[^:]+:[        ]+34550513[     ]+add[  ]+a0,a0,837
> +[^:]+:[        ]+0532[         ]+sll[  ]+a0,a0,0xc
> +[^:]+:[        ]+0505[         ]+add[  ]+a0,a0,1
> --- a/gas/testsuite/gas/riscv/lla32.d
> +++ b/gas/testsuite/gas/riscv/lla32.d
> @@ -10,10 +10,10 @@ Disassembly of section .text:
>     0:  00100513                li      a0,1
>     4:  00001537                lui     a0,0x1
>     8:  00001537                lui     a0,0x1
> -   c:  00150513                addi    a0,a0,1 # 1001 <c>
> +   c:  00150513                add     a0,a0,1 # 1001 <c>
>    10:  00001537                lui     a0,0x1
> -  14:  fff50513                addi    a0,a0,-1 # fff <d>
> +  14:  fff50513                add     a0,a0,-1 # fff <d>
>    18:  80000537                lui     a0,0x80000
> -  1c:  fff50513                addi    a0,a0,-1 # 7fffffff <h\+0x80000000>
> +  1c:  fff50513                add     a0,a0,-1 # 7fffffff <h\+0x80000000>
>    20:  00000513                li      a0,0
>    24:  fff00513                li      a0,-1
> --- a/gas/testsuite/gas/riscv/lla64.d
> +++ b/gas/testsuite/gas/riscv/lla64.d
> @@ -7,14 +7,14 @@
>  Disassembly of section .text:
>
>  0+000 <.text>:
> -   0:  0010051b                addiw   a0,zero,1
> +   0:  0010051b                addw    a0,zero,1
>     4:  00001537                lui     a0,0x1
>     8:  00001537                lui     a0,0x1
> -   c:  0015051b                addiw   a0,a0,1 # .*
> +   c:  0015051b                addw    a0,a0,1 # .*
>    10:  00001537                lui     a0,0x1
> -  14:  fff5051b                addiw   a0,a0,-1 # .*
> +  14:  fff5051b                addw    a0,a0,-1 # .*
>    18:  80000537                lui     a0,0x80000
> -  1c:  fff5051b                addiw   a0,a0,-1 # .*
> +  1c:  fff5051b                addw    a0,a0,-1 # .*
>    20:  0000051b                sext.w  a0,zero
> -  24:  fff0051b                addiw   a0,zero,-1
> +  24:  fff0051b                addw    a0,zero,-1
>    28:  80000537                lui     a0,0x80000
> --- a/gas/testsuite/gas/riscv/zbkb-32.d
> +++ b/gas/testsuite/gas/riscv/zbkb-32.d
> @@ -10,7 +10,7 @@ Disassembly of section .text:
>  0+000 <target>:
>  [      ]+[0-9a-f]+:[   ]+60c5d533[     ]+ror[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+60c59533[     ]+rol[  ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+ror[  ]+a0,a1,0x2
>  [      ]+[0-9a-f]+:[   ]+40c5f533[     ]+andn[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5e533[     ]+orn[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
> --- a/gas/testsuite/gas/riscv/zbkb-64.d
> +++ b/gas/testsuite/gas/riscv/zbkb-64.d
> @@ -10,10 +10,10 @@ Disassembly of section .text:
>  0+000 <target>:
>  [      ]+[0-9a-f]+:[   ]+60c5d533[     ]+ror[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+60c59533[     ]+rol[  ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+ror[  ]+a0,a1,0x2
>  [      ]+[0-9a-f]+:[   ]+60c5d53b[     ]+rorw[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+60c5953b[     ]+rolw[         ]+a0,a1,a2
> -[      ]+[0-9a-f]+:[   ]+6025d51b[     ]+roriw[        ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+6025d51b[     ]+rorw[         ]+a0,a1,0x2
>  [      ]+[0-9a-f]+:[   ]+40c5f533[     ]+andn[         ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5e533[     ]+orn[  ]+a0,a1,a2
>  [      ]+[0-9a-f]+:[   ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
> --- a/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d
> +++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-01.d
> @@ -11,7 +11,7 @@ Disassembly of section .text:
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
>  .*:[   ]+[0-9a-f]+[    ]+(lw|ld)[      ]+.*<(_GLOBAL_OFFSET_TABLE_.*|__DATA_BEGIN__.*|.*)>
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
> -.*:[   ]+[0-9a-f]+[    ]+addi[         ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
> +.*:[   ]+[0-9a-f]+[    ]+addi?[        ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
>  .*:[   ]+[0-9a-f]+[    ]+jalr[         ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
> --- a/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d
> +++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-02.d
> @@ -13,7 +13,7 @@ Disassembly of section .text:
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
>  .*:[   ]+[0-9a-f]+[    ]+(lw|ld)[      ]+.*<(__DATA_BEGIN__.*|.*)>
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
> -.*:[   ]+[0-9a-f]+[    ]+addi[         ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
> +.*:[   ]+[0-9a-f]+[    ]+addi?[        ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
>  .*:[   ]+[0-9a-f]+[    ]+jalr[         ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
> --- a/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d
> +++ b/ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d
> @@ -9,7 +9,7 @@ Disassembly of section .text:
>  #...
>  0+[0-9a-f]+ <bar>:
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
> -.*:[   ]+[0-9a-f]+[    ]+addi[         ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
> +.*:[   ]+[0-9a-f]+[    ]+addi?[        ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+.*
>  .*:[   ]+[0-9a-f]+[    ]+(lw|ld)[      ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
>  #...
> --- a/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d
> +++ b/ld/testsuite/ld-riscv-elf/pcgp-relax-02.d
> @@ -10,6 +10,6 @@ Disassembly of section .text:
>
>  [0-9a-f]+ <_start>:
>  .*:[   ]+[0-9a-f]+[    ]+auipc[        ]+a1.*
> -.*:[   ]+[0-9a-f]+[    ]+addi[         ]+a0,gp.*<data_a>
> -.*:[   ]+[0-9a-f]+[    ]+addi[         ]+a1,a1.*<data_b>
> +.*:[   ]+[0-9a-f]+[    ]+addi?[        ]+a0,gp.*<data_a>
> +.*:[   ]+[0-9a-f]+[    ]+addi?[        ]+a1,a1.*<data_b>
>  #pass
> --- a/ld/testsuite/ld-riscv-elf/weakref32.d
> +++ b/ld/testsuite/ld-riscv-elf/weakref32.d
> @@ -9,12 +9,12 @@ Disassembly of section \.text:
>  90000004:      02078663                beqz    a5,90000030 <_start\+0x30>
>  90000008:      00000793                li      a5,0
>  9000000c:      02078263                beqz    a5,90000030 <_start\+0x30>
> -90000010:      ff010113                addi    sp,sp,-16
> +90000010:      ff010113                addi?   sp,sp,-16
>  90000014:      00112623                sw      ra,12\(sp\)
>  90000018:      00000097                auipc   ra,0x0
>  9000001c:      000000e7                jalr    zero # 0 <_start\-0x90000000>
>  90000020:      00c12083                lw      ra,12\(sp\)
> -90000024:      01010113                addi    sp,sp,16
> +90000024:      01010113                addi?   sp,sp,16
>  90000028:      00000317                auipc   t1,0x0
>  9000002c:      00000067                jr      zero # 0 <_start\-0x90000000>
>  90000030:      00008067                ret
> --- a/ld/testsuite/ld-riscv-elf/weakref64.d
> +++ b/ld/testsuite/ld-riscv-elf/weakref64.d
> @@ -9,12 +9,12 @@ Disassembly of section \.text:
>      90000004:  02078663                beqz    a5,90000030 <_start\+0x30>
>      90000008:  00000793                li      a5,0
>      9000000c:  02078263                beqz    a5,90000030 <_start\+0x30>
> -    90000010:  ff010113                addi    sp,sp,-16
> +    90000010:  ff010113                addi?   sp,sp,-16
>      90000014:  00113423                sd      ra,8\(sp\)
>      90000018:  00000097                auipc   ra,0x0
>      9000001c:  000000e7                jalr    zero # 0 <_start\-0x90000000>
>      90000020:  00813083                ld      ra,8\(sp\)
> -    90000024:  01010113                addi    sp,sp,16
> +    90000024:  01010113                addi?   sp,sp,16
>      90000028:  00000317                auipc   t1,0x0
>      9000002c:  00000067                jr      zero # 0 <_start\-0x90000000>
>      90000030:  00008067                ret
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
>  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
>  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
>  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
> +{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
>  {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
> -{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
>  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
>  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
> @@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
>  {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
>  {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
>  {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
> -{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> -{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>  {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>  {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
>  {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
> +{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> +{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },

Doesn't ANDI a base instruction?  The operand "d,s,j" of AND is an
alias of ANDI, so the original order seems correct.  Always dump *.i
instructions to the non-i type looks weird, and llvm-dump seems has
the same behavior as current GNU objdump.

% cat tmp.s
and a0, a1, 0x10
% riscv64-unknown-elf-as tmp.s -o tmp.o
% riscv64-unknown-elf-objdump -d tmp.o

tmp.o:     file format elf64-littleriscv


Disassembly of section .text:

0000000000000000 <.text>:

   0: 0105f513          and a0,a1,16
% llvm-objdump -d tmp.o

tmp.o: file format elf64-littleriscv

Disassembly of section .text:

0000000000000000 <$x>:
       0: 13 f5 05 01  andi a0, a1, 16

>  {"beqz",        0, INSN_CLASS_C, "Cs,Cp",     MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>  {"beqz",        0, INSN_CLASS_I, "s,p",       MATCH_BEQ, MASK_BEQ|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>  {"beq",         0, INSN_CLASS_C, "Cs,Cz,Cp",  MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
> @@ -337,13 +337,6 @@ const struct riscv_opcode riscv_opcodes[
>  {"bnez",        0, INSN_CLASS_I, "s,p",       MATCH_BNE, MASK_BNE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>  {"bne",         0, INSN_CLASS_C, "Cs,Cz,Cp",  MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>  {"bne",         0, INSN_CLASS_I, "s,t,p",     MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
> -{"addi",        0, INSN_CLASS_C, "Ct,Cc,CK",  MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
> -{"addi",        0, INSN_CLASS_C, "d,CU,Cj",   MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
> -{"addi",        0, INSN_CLASS_C, "d,CU,z",    MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
> -{"addi",        0, INSN_CLASS_C, "Cc,Cc,CL",  MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
> -{"addi",        0, INSN_CLASS_C, "d,Cz,Co",   MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
> -{"addi",        0, INSN_CLASS_C, "d,CV,z",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
> -{"addi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
>  {"add",         0, INSN_CLASS_C, "d,CU,CV",   MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
>  {"add",         0, INSN_CLASS_C, "d,CV,CU",   MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
>  {"add",         0, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
> @@ -353,26 +346,33 @@ const struct riscv_opcode riscv_opcodes[
>  {"add",         0, INSN_CLASS_I, "d,s,t",     MATCH_ADD, MASK_ADD, match_opcode, 0 },
>  {"add",         0, INSN_CLASS_I, "d,s,t,1",   MATCH_ADD, MASK_ADD, match_opcode, 0 },
>  {"add",         0, INSN_CLASS_I, "d,s,j",     MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
> +{"addi",        0, INSN_CLASS_C, "Ct,Cc,CK",  MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
> +{"addi",        0, INSN_CLASS_C, "d,CU,Cj",   MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
> +{"addi",        0, INSN_CLASS_C, "d,CU,z",    MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
> +{"addi",        0, INSN_CLASS_C, "Cc,Cc,CL",  MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
> +{"addi",        0, INSN_CLASS_C, "d,Cz,Co",   MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
> +{"addi",        0, INSN_CLASS_C, "d,CV,z",    MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
> +{"addi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ADDI, MASK_ADDI, match_opcode, 0 },

Same as AND and ANDI.  The followings should be the same issue.


>  {"la",          0, INSN_CLASS_I, "d,B",       0, (int) M_LA, match_never, INSN_MACRO },
>  {"lla",         0, INSN_CLASS_I, "d,B",       0, (int) M_LLA, match_never, INSN_MACRO },
>  {"la.tls.gd",   0, INSN_CLASS_I, "d,A",       0, (int) M_LA_TLS_GD, match_never, INSN_MACRO },
>  {"la.tls.ie",   0, INSN_CLASS_I, "d,A",       0, (int) M_LA_TLS_IE, match_never, INSN_MACRO },
>  {"neg",         0, INSN_CLASS_I, "d,t",       MATCH_SUB, MASK_SUB|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0  */
> -{"slli",        0, INSN_CLASS_C, "d,CU,C>",   MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
> -{"slli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
>  {"sll",         0, INSN_CLASS_C, "d,CU,C>",   MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
>  {"sll",         0, INSN_CLASS_I, "d,s,t",     MATCH_SLL, MASK_SLL, match_opcode, 0 },
>  {"sll",         0, INSN_CLASS_I, "d,s,>",     MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
> -{"srli",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
> -{"srli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
> +{"slli",        0, INSN_CLASS_C, "d,CU,C>",   MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
> +{"slli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
>  {"srl",         0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
>  {"srl",         0, INSN_CLASS_I, "d,s,t",     MATCH_SRL, MASK_SRL, match_opcode, 0 },
>  {"srl",         0, INSN_CLASS_I, "d,s,>",     MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
> -{"srai",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
> -{"srai",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
> +{"srli",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
> +{"srli",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
>  {"sra",         0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
>  {"sra",         0, INSN_CLASS_I, "d,s,t",     MATCH_SRA, MASK_SRA, match_opcode, 0 },
>  {"sra",         0, INSN_CLASS_I, "d,s,>",     MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
> +{"srai",        0, INSN_CLASS_C, "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
> +{"srai",        0, INSN_CLASS_I, "d,s,>",     MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
>  {"sub",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
>  {"sub",         0, INSN_CLASS_I, "d,s,t",     MATCH_SUB, MASK_SUB, match_opcode, 0 },
>  {"lb",          0, INSN_CLASS_I, "d,o(s)",    MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE },
> @@ -391,11 +391,11 @@ const struct riscv_opcode riscv_opcodes[
>  {"prefetch.i",  0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 },
>  {"prefetch.r",  0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 },
>  {"prefetch.w",  0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 },
> -{"ori",         0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, 0 },
> +{"or",          0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
>  {"or",          0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
>  {"or",          0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
>  {"or",          0, INSN_CLASS_I, "d,s,t",     MATCH_OR, MASK_OR, match_opcode, 0 },
> -{"or",          0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
> +{"ori",         0, INSN_CLASS_I, "d,s,j",     MATCH_ORI, MASK_ORI, match_opcode, 0 },
>  {"auipc",       0, INSN_CLASS_I, "d,u",       MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
>  {"seqz",        0, INSN_CLASS_I, "d,s",       MATCH_SLTIU|ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
>  {"snez",        0, INSN_CLASS_I, "d,t",       MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
> @@ -430,11 +430,11 @@ const struct riscv_opcode riscv_opcodes[
>  {"rdtimeh",    32, INSN_CLASS_I, "d",         MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
>  {"ecall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
>  {"scall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
> -{"xori",        0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, 0 },
> +{"xor",         0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
>  {"xor",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
>  {"xor",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
>  {"xor",         0, INSN_CLASS_I, "d,s,t",     MATCH_XOR, MASK_XOR, match_opcode, 0 },
> -{"xor",         0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
> +{"xori",        0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, 0 },
>  {"lwu",        64, INSN_CLASS_I, "d,o(s)",    MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE },
>  {"lwu",        64, INSN_CLASS_I, "d,A",       0, (int) M_LWU, match_never, INSN_MACRO },
>  {"ld",         64, INSN_CLASS_C, "d,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
> @@ -447,23 +447,23 @@ const struct riscv_opcode riscv_opcodes[
>  {"sd",         64, INSN_CLASS_I, "t,A,s",     0, (int) M_SD, match_never, INSN_MACRO },
>  {"sext.w",     64, INSN_CLASS_C, "d,CU",      MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
>  {"sext.w",     64, INSN_CLASS_I, "d,s",       MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS },
> -{"addiw",      64, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
> -{"addiw",      64, INSN_CLASS_I, "d,s,j",     MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 },
>  {"addw",       64, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
>  {"addw",       64, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
>  {"addw",       64, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
>  {"addw",       64, INSN_CLASS_I, "d,s,t",     MATCH_ADDW, MASK_ADDW, match_opcode, 0 },
>  {"addw",       64, INSN_CLASS_I, "d,s,j",     MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS },
> +{"addiw",      64, INSN_CLASS_C, "d,CU,Co",   MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
> +{"addiw",      64, INSN_CLASS_I, "d,s,j",     MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 },
>  {"negw",       64, INSN_CLASS_I, "d,t",       MATCH_SUBW, MASK_SUBW|MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0  */
> -{"slliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 },
>  {"sllw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SLLW, MASK_SLLW, match_opcode, 0 },
>  {"sllw",       64, INSN_CLASS_I, "d,s,<",     MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS },
> -{"srliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 },
> +{"slliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 },
>  {"srlw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SRLW, MASK_SRLW, match_opcode, 0 },
>  {"srlw",       64, INSN_CLASS_I, "d,s,<",     MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS },
> -{"sraiw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 },
> +{"srliw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 },
>  {"sraw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SRAW, MASK_SRAW, match_opcode, 0 },
>  {"sraw",       64, INSN_CLASS_I, "d,s,<",     MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS },
> +{"sraiw",      64, INSN_CLASS_I, "d,s,<",     MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 },
>  {"subw",       64, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS },
>  {"subw",       64, INSN_CLASS_I, "d,s,t",     MATCH_SUBW, MASK_SUBW, match_opcode, 0 },
>
> @@ -885,24 +885,24 @@ const struct riscv_opcode riscv_opcodes[
>
>  /* Supervisor instructions.  */
>  {"csrr",       0, INSN_CLASS_ZICSR,"d,E",      MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
> -{"csrwi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
> -{"csrsi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS },
> -{"csrci",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS },
>  {"csrw",       0, INSN_CLASS_ZICSR,"E,s",      MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
>  {"csrw",       0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
> +{"csrwi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
>  {"csrs",       0, INSN_CLASS_ZICSR,"E,s",      MATCH_CSRRS, MASK_CSRRS|MASK_RD, match_opcode, INSN_ALIAS },
>  {"csrs",       0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS },
> +{"csrsi",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS },
>  {"csrc",       0, INSN_CLASS_ZICSR,"E,s",      MATCH_CSRRC, MASK_CSRRC|MASK_RD, match_opcode, INSN_ALIAS },
>  {"csrc",       0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS },
> -{"csrrwi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
> -{"csrrsi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
> -{"csrrci",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
> +{"csrci",      0, INSN_CLASS_ZICSR,"E,Z",      MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS },
>  {"csrrw",      0, INSN_CLASS_ZICSR,"d,E,s",    MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 },
>  {"csrrw",      0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS },
> +{"csrrwi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
>  {"csrrs",      0, INSN_CLASS_ZICSR,"d,E,s",    MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 },
>  {"csrrs",      0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS },
> +{"csrrsi",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
>  {"csrrc",      0, INSN_CLASS_ZICSR,"d,E,s",    MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 },
>  {"csrrc",      0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS },
> +{"csrrci",     0, INSN_CLASS_ZICSR,"d,E,Z",    MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
>  {"uret",       0, INSN_CLASS_I,    "",         MATCH_URET, MASK_URET, match_opcode, 0 },
>  {"sret",       0, INSN_CLASS_I,    "",         MATCH_SRET, MASK_SRET, match_opcode, 0 },
>  {"hret",       0, INSN_CLASS_I,    "",         MATCH_HRET, MASK_HRET, match_opcode, 0 },
> @@ -951,15 +951,15 @@ const struct riscv_opcode riscv_opcodes[
>  {"orn",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
>  {"xnor",       0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
>  {"rol",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
> -{"rori",       0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
>  {"ror",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
>  {"ror",        0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
> +{"rori",       0, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
>  {"rev8",      32, INSN_CLASS_ZBB_OR_ZBKB,  "d,s",   MATCH_GREVI | MATCH_SHAMT_REV8_32, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
>  {"rev8",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s",   MATCH_GREVI | MATCH_SHAMT_REV8_64, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
>  {"rolw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
> -{"roriw",     64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
>  {"rorw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> -{"rorw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> +{"rorw",      64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
> +{"roriw",     64, INSN_CLASS_ZBB_OR_ZBKB,  "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
>
>  /* Zba instructions.  */
>  {"sh1add",     0, INSN_CLASS_ZBA,  "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
> @@ -979,18 +979,18 @@ const struct riscv_opcode riscv_opcodes[
>  {"clmulr",     0, INSN_CLASS_ZBC,  "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
>
>  /* Zbs instructions.  */
> -{"bclri",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
> -{"bseti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
> -{"binvi",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
> -{"bexti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
>  {"bclr",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
>  {"bclr",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
> +{"bclri",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
>  {"bset",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BSET, MASK_BSET, match_opcode, 0 },
>  {"bset",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
> +{"bseti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
>  {"binv",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BINV, MASK_BINV, match_opcode, 0 },
>  {"binv",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
> +{"binvi",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
>  {"bext",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
>  {"bext",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
> +{"bexti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
>
>  /* Zbkx instructions.  */
>  {"xperm4",     0, INSN_CLASS_ZBKX,  "d,s,t",  MATCH_XPERM4, MASK_XPERM4, match_opcode, 0 },
>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags
  2022-09-13 13:03 ` [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags Jan Beulich
@ 2022-09-15  2:43   ` Nelson Chu
  0 siblings, 0 replies; 29+ messages in thread
From: Nelson Chu @ 2022-09-15  2:43 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson

Thanks, this patch fixes the problem when dumping fence.tso, zip and
unzip with -Mno-aliases.  Please commit this one when you think it's
time.

* Before applying this patch,

% cat tmp.s
zip a0, a1
unzip a0, a1
fence.tso
% riscv64-unknown-elf-as -march=rv32i_zbkb tmp.s -o tmp.o
% riscv64-unknown-elf-objdump -d tmp.o

tmp.o:     file format elf32-littleriscv


Disassembly of section .text:

00000000 <.text>:
   0: 08f59513          zip a0,a1
   4: 08f5d513          unzip a0,a1
   8: 8330000f          fence.tso
% riscv64-unknown-elf-objdump -d -Mno-aliases tmp.o

tmp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0: 08f59513          .4byte 0x8f59513
   4: 08f5d513          .4byte 0x8f5d513
   8: 8330000f          .4byte 0x8330000f

* After applying this patch, I get the right result for -Mno-aliases,

% riscv64-unknown-elf-objdump -d -Mno-aliases tmp.o

tmp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0: 08f59513          zip a0,a1
   4: 08f5d513          unzip a0,a1
   8: 8330000f          fence.tso

Thanks
Nelson

On Tue, Sep 13, 2022 at 9:03 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but
> presently they aren't. This fixes disassembly of these insns with
> -Mno-aliases.
>
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/fence-tso-na.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv32ic
> +#source: fence-tso.s
> +#objdump: -dr -Mno-aliases
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[      ]+[0-9a-f]+:[   ]+8330000f[     ]+fence.tso
> +#pass
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zbkb-32-na.d
> @@ -0,0 +1,23 @@
> +#as: -march=rv32i_zbkb
> +#source: zbkb-32.s
> +#objdump: -d -Mno-aliases
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[      ]+[0-9a-f]+:[   ]+60c5d533[     ]+ror[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+60c59533[     ]+rol[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+6025d513[     ]+rori[         ]+a0,a1,0x2
> +[      ]+[0-9a-f]+:[   ]+40c5f533[     ]+andn[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+40c5e533[     ]+orn[  ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+40c5c533[     ]+xnor[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+08c5c533[     ]+pack[         ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+08c5f533[     ]+packh[        ]+a0,a1,a2
> +[      ]+[0-9a-f]+:[   ]+68755513[     ]+brev8[        ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+69855513[     ]+rev8[         ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+08f51513[     ]+zip[  ]+a0,a0
> +[      ]+[0-9a-f]+:[   ]+08f55513[     ]+unzip[        ]+a0,a0
> +#pass
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -421,7 +421,7 @@ const struct riscv_opcode riscv_opcodes[
>  {"fence",       0, INSN_CLASS_I, "",          MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
>  {"fence",       0, INSN_CLASS_I, "P,Q",       MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
>  {"fence.i",     0, INSN_CLASS_ZIFENCEI, "",   MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
> -{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, INSN_ALIAS },
> +{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 },
>  {"rdcycle",     0, INSN_CLASS_I, "d",         MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
>  {"rdinstret",   0, INSN_CLASS_I, "d",         MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
>  {"rdtime",      0, INSN_CLASS_I, "d",         MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
> @@ -942,8 +942,8 @@ const struct riscv_opcode riscv_opcodes[
>  {"cpopw",     64, INSN_CLASS_ZBB,  "d,s",   MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
>  {"brev8",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
>  {"brev8",     64, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
> -{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> -{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
> +{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
> +{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
>  {"pack",       0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
>  {"packh",      0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
>  {"packw",     64, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2022-09-15  2:30   ` Nelson Chu
@ 2022-09-15  7:42     ` Jan Beulich
  2022-09-16  9:53       ` Nelson Chu
  0 siblings, 1 reply; 29+ messages in thread
From: Jan Beulich @ 2022-09-15  7:42 UTC (permalink / raw)
  To: Nelson Chu; +Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson

On 15.09.2022 04:30, Nelson Chu wrote:
> On Tue, Sep 13, 2022 at 9:02 PM Jan Beulich <jbeulich@suse.com> wrote:
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
>>  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
>>  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
>>  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
>> +{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>>  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
>>  {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
>> -{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>>  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
>>  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
>>  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
>> @@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
>>  {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
>>  {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
>>  {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
>> -{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>> -{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>>  {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>>  {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
>>  {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
>> +{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>> +{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
> 
> Doesn't ANDI a base instruction?

Of course. Like for all aliases, there is a corresponding base
instruction. I guess I simply don't understand what you mean to
express with the question.

>  The operand "d,s,j" of AND is an
> alias of ANDI, so the original order seems correct.  Always dump *.i
> instructions to the non-i type looks weird, and llvm-dump seems has
> the same behavior as current GNU objdump.
> 
> % cat tmp.s
> and a0, a1, 0x10
> % riscv64-unknown-elf-as tmp.s -o tmp.o
> % riscv64-unknown-elf-objdump -d tmp.o
> 
> tmp.o:     file format elf64-littleriscv
> 
> 
> Disassembly of section .text:
> 
> 0000000000000000 <.text>:
> 
>    0: 0105f513          and a0,a1,16

What's weird about that? And if that's weird, would you mind spelling
out the conditions under which aliases are to be preferred over base
instructions when disassembling? There actually is a "These aliases are
for assembly but not disassembly" comment somewhere in the file,
clarifying for two of the aliases that they ought to come after their
base insns. But for all other aliases which aren't simply a different
(but not shorter) name for the same insn (e.g. "bgt" vs "blt") I'd
assume the aliases should be preferred, for the reason stated in the
patch description. That said - I can see it being a matter of taste
for <insn>i vs <insn>, but if so this should be spelled out somewhere.

> % llvm-objdump -d tmp.o
> 
> tmp.o: file format elf64-littleriscv
> 
> Disassembly of section .text:
> 
> 0000000000000000 <$x>:
>        0: 13 f5 05 01  andi a0, a1, 16

I don't think I view llvm as a "canonical reference". Perhaps they merely
followed the GNU behavior?

Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2022-09-15  7:42     ` Jan Beulich
@ 2022-09-16  9:53       ` Nelson Chu
  2023-07-11 21:02         ` Fangrui Song
       [not found]         ` <DS7PR12MB576580071090C394AECFC618CB31A@DS7PR12MB5765.namprd12.prod.outlook.com>
  0 siblings, 2 replies; 29+ messages in thread
From: Nelson Chu @ 2022-09-16  9:53 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson

On Thu, Sep 15, 2022 at 3:42 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 15.09.2022 04:30, Nelson Chu wrote:
> > On Tue, Sep 13, 2022 at 9:02 PM Jan Beulich <jbeulich@suse.com> wrote:
> >> --- a/opcodes/riscv-opc.c
> >> +++ b/opcodes/riscv-opc.c
> >> @@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
> >>  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
> >>  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
> >>  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
> >> +{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
> >>  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
> >>  {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
> >> -{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
> >>  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
> >>  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
> >>  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
> >> @@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
> >>  {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
> >>  {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
> >>  {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
> >> -{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> >> -{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
> >>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
> >>  {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
> >>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> >>  {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
> >>  {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
> >> +{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> >> +{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
> >
> > Doesn't ANDI a base instruction?
>
> Of course. Like for all aliases, there is a corresponding base
> instruction. I guess I simply don't understand what you mean to
> express with the question.
>
> >  The operand "d,s,j" of AND is an
> > alias of ANDI, so the original order seems correct.  Always dump *.i
> > instructions to the non-i type looks weird, and llvm-dump seems has
> > the same behavior as current GNU objdump.
> >
> > % cat tmp.s
> > and a0, a1, 0x10
> > % riscv64-unknown-elf-as tmp.s -o tmp.o
> > % riscv64-unknown-elf-objdump -d tmp.o
> >
> > tmp.o:     file format elf64-littleriscv
> >
> >
> > Disassembly of section .text:
> >
> > 0000000000000000 <.text>:
> >
> >    0: 0105f513          and a0,a1,16
>
> What's weird about that? And if that's weird, would you mind spelling
> out the conditions under which aliases are to be preferred over base
> instructions when disassembling? There actually is a "These aliases are
> for assembly but not disassembly" comment somewhere in the file,
> clarifying for two of the aliases that they ought to come after their
> base insns. But for all other aliases which aren't simply a different
> (but not shorter) name for the same insn (e.g. "bgt" vs "blt") I'd
> assume the aliases should be preferred, for the reason stated in the
> patch description. That said - I can see it being a matter of taste
> for <insn>i vs <insn>, but if so this should be spelled out somewhere.

Yeah, that's what I worried about.  At the beginning, I think dumping
a base instruction as another base instruction looks weird.  But these
days I also noticed that - we also dump compressed instructions as
base i without "c." prefixes, so why I feel weird is just that I'm
used to it because of historical behavior.  I have no objection to
this, so please go ahead if there are no objections for a period of
time.  But if there are any objections, then we probably can mark
these aliases by something like INSN_ALIAS_CANNOT_DUMP in the opcode
table, and that's what Kito suggested to me before, but I didn't think
it was a serious problem at the time.

Thanks
Nelson

> > % llvm-objdump -d tmp.o
> >
> > tmp.o: file format elf64-littleriscv
> >
> > Disassembly of section .text:
> >
> > 0000000000000000 <$x>:
> >        0: 13 f5 05 01  andi a0, a1, 16
>
> I don't think I view llvm as a "canonical reference". Perhaps they merely
> followed the GNU behavior?
>
> Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats"
  2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
                   ` (3 preceding siblings ...)
  2022-09-13 14:54 ` [PATCH 0/3] RISC-V: alias insn adjustments Tsukasa OI
@ 2022-09-30  9:41 ` Jan Beulich
  2022-09-30 10:26   ` Christoph Müllner
  2022-09-30  9:42 ` [PATCH] RISC-V: fallout from "re-arrange opcode table for consistent alias handling" Jan Beulich
  2022-09-30  9:42 ` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics Jan Beulich
  6 siblings, 1 reply; 29+ messages in thread
From: Jan Beulich @ 2022-09-30  9:41 UTC (permalink / raw)
  To: Binutils
  Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu,
	Christoph Müllner

Pre- and post-increment/decrement are side effects, the behavior of
which is undefined when combined with passing an address of the accessed
variable in the same function invocation. There's no need for the
increments here - simply adding 1 achieves the intended effect without
triggering compiler diagnostics (which are fatal with -Werror).
---
Committing as obvious.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1287,10 +1287,10 @@ validate_riscv_insn (const struct riscv_
 		case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S.  */
 		  goto use_imm;
 		use_imm:
-		  n = strtol (++oparg, (char **)&oparg, 10);
+		  n = strtol (oparg + 1, (char **)&oparg, 10);
 		  if (*oparg != '@')
 		    goto unknown_validate_operand;
-		  s = strtol (++oparg, (char **)&oparg, 10);
+		  s = strtol (oparg + 1, (char **)&oparg, 10);
 		  oparg--;
 
 		  USE_IMM (n, s);
@@ -3327,10 +3327,10 @@ riscv_ip (char *str, struct riscv_cl_ins
 		      sign = false;
 		      goto parse_imm;
 		    parse_imm:
-		      n = strtol (++oparg, (char **)&oparg, 10);
+		      n = strtol (oparg + 1, (char **)&oparg, 10);
 		      if (*oparg != '@')
 			goto unknown_riscv_ip_operand;
-		      s = strtol (++oparg, (char **)&oparg, 10);
+		      s = strtol (oparg + 1, (char **)&oparg, 10);
 		      oparg--;
 
 		      my_getExpression (imm_expr, asarg);
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -586,10 +586,10 @@ print_insn_args (const char *oparg, insn
 		  sign = false;
 		  goto print_imm;
 		print_imm:
-		  n = strtol (++oparg, (char **)&oparg, 10);
+		  n = strtol (oparg + 1, (char **)&oparg, 10);
 		  if (*oparg != '@')
 		    goto undefined_modifier;
-		  s = strtol (++oparg, (char **)&oparg, 10);
+		  s = strtol (oparg + 1, (char **)&oparg, 10);
 		  oparg--;
 
 		  if (!sign)

^ permalink raw reply	[flat|nested] 29+ messages in thread

* [PATCH] RISC-V: fallout from "re-arrange opcode table for consistent alias handling"
  2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
                   ` (4 preceding siblings ...)
  2022-09-30  9:41 ` [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats" Jan Beulich
@ 2022-09-30  9:42 ` Jan Beulich
  2022-09-30  9:42 ` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics Jan Beulich
  6 siblings, 0 replies; 29+ messages in thread
From: Jan Beulich @ 2022-09-30  9:42 UTC (permalink / raw)
  To: Binutils; +Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

Several new testcasee have appeared since the submission of said change,
some of which now also need adjustment.
---
Committing as obvious follow-up.

--- a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
@@ -9,10 +9,10 @@ Disassembly of section .text:
 
 0+ffffffe0 <_start>:
 [ 	]+ffffffe0:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0
-[ 	]+ffffffe4:[ 	]+0182831b[ 	]+addiw[ 	]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
+[ 	]+ffffffe4:[ 	]+0182831b[ 	]+addw[ 	]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
 [ 	]+ffffffe8:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
-[ 	]+ffffffec:[ 	]+01c38e1b[ 	]+addiw[ 	]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
+[ 	]+ffffffec:[ 	]+01c38e1b[ 	]+addw[ 	]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
 [ 	]+fffffff0:[ 	]+00000e97[ 	]+auipc[ 	]+t4,0x0
-[ 	]+fffffff4:[ 	]+2eb1[ 	]+addiw[ 	]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
+[ 	]+fffffff4:[ 	]+2eb1[ 	]+addw[ 	]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
 [ 	]+fffffff6:[ 	]+00000f17[ 	]+auipc[ 	]+t5,0x0
-[ 	]+fffffffa:[ 	]+2f49[ 	]+addiw[ 	]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
+[ 	]+fffffffa:[ 	]+2f49[ 	]+addw[ 	]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
--- a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
@@ -9,10 +9,10 @@ Disassembly of section .text:
 
 0+7fffffe0 <_start>:
 [ 	]+7fffffe0:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0
-[ 	]+7fffffe4:[ 	]+0182831b[ 	]+addiw[ 	]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
+[ 	]+7fffffe4:[ 	]+0182831b[ 	]+addw[ 	]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
 [ 	]+7fffffe8:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
-[ 	]+7fffffec:[ 	]+01c38e1b[ 	]+addiw[ 	]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
+[ 	]+7fffffec:[ 	]+01c38e1b[ 	]+addw[ 	]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
 [ 	]+7ffffff0:[ 	]+00000e97[ 	]+auipc[ 	]+t4,0x0
-[ 	]+7ffffff4:[ 	]+2eb1[ 	]+addiw[ 	]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
+[ 	]+7ffffff4:[ 	]+2eb1[ 	]+addw[ 	]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
 [ 	]+7ffffff6:[ 	]+00000f17[ 	]+auipc[ 	]+t5,0x0
-[ 	]+7ffffffa:[ 	]+2f49[ 	]+addiw[ 	]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
+[ 	]+7ffffffa:[ 	]+2f49[ 	]+addw[ 	]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
--- a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
@@ -19,9 +19,9 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+ffffbeb7[ 	]+lui[  	]+t4,0xffffb
 [ 	]+[0-9a-f]+:[ 	]+000e8a67[ 	]+jalr[ 	]+s4,t4 # ffffb000 <addr_jalr_3>
 [ 	]+[0-9a-f]+:[ 	]+ffffaf37[ 	]+lui[  	]+t5,0xffffa
-[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+addi[ 	]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
+[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+add[ 	]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
 [ 	]+[0-9a-f]+:[ 	]+ffff9fb7[ 	]+lui[  	]+t6,0xffff9
-[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+addi[ 	]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
+[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+add[ 	]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
 [ 	]+[0-9a-f]+:[ 	]+4001a283[ 	]+lw[   	]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
 [ 	]+[0-9a-f]+:[ 	]+c001a303[ 	]+lw[   	]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg>
 [ 	]+[0-9a-f]+:[ 	]+10002383[ 	]+lw[   	]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
--- a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
@@ -19,13 +19,13 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+ffffbeb7[ 	]+lui[  	]+t4,0xffffb
 [ 	]+[0-9a-f]+:[ 	]+000e8a67[ 	]+jalr[ 	]+s4,t4 # ffffffffffffb000 <addr_jalr_3>
 [ 	]+[0-9a-f]+:[ 	]+ffffaf37[ 	]+lui[  	]+t5,0xffffa
-[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+addi[ 	]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
+[ 	]+[0-9a-f]+:[ 	]+ff0f0a93[ 	]+add[ 	]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
 [ 	]+[0-9a-f]+:[ 	]+ffff9fb7[ 	]+lui[  	]+t6,0xffff9
-[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+addi[ 	]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
+[ 	]+[0-9a-f]+:[ 	]+1fb1[ 	]+add[ 	]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
 [ 	]+[0-9a-f]+:[ 	]+ffff8b37[ 	]+lui[  	]+s6,0xffff8
-[ 	]+[0-9a-f]+:[ 	]+fe8b0b9b[ 	]+addiw[ 	]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
+[ 	]+[0-9a-f]+:[ 	]+fe8b0b9b[ 	]+addw[ 	]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
 [ 	]+[0-9a-f]+:[ 	]+ffff7c37[ 	]+lui[  	]+s8,0xffff7
-[ 	]+[0-9a-f]+:[ 	]+3c11[ 	]+addiw[ 	]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
+[ 	]+[0-9a-f]+:[ 	]+3c11[ 	]+addw[ 	]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
 [ 	]+[0-9a-f]+:[ 	]+4001a283[ 	]+lw[   	]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
 [ 	]+[0-9a-f]+:[ 	]+c001a303[ 	]+lw[   	]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg>
 [ 	]+[0-9a-f]+:[ 	]+10002383[ 	]+lw[   	]+t2,256\(zero\) # 100 <addr_rel_zero_pos>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics
  2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
                   ` (5 preceding siblings ...)
  2022-09-30  9:42 ` [PATCH] RISC-V: fallout from "re-arrange opcode table for consistent alias handling" Jan Beulich
@ 2022-09-30  9:42 ` Jan Beulich
  2022-09-30 10:13   ` Christoph Müllner
  2022-09-30 14:43   ` Nelson Chu
  6 siblings, 2 replies; 29+ messages in thread
From: Jan Beulich @ 2022-09-30  9:42 UTC (permalink / raw)
  To: Binutils
  Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu,
	Christoph Müllner

There's no need for such workarounds anymore now that we use C99
uniformly. This addresses several testsuite failures encountered when
(cross-)building on a 32-bit host.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3338,14 +3338,14 @@ riscv_ip (char *str, struct riscv_cl_ins
 		      if (!sign)
 			{
 			  if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
-			    as_bad (_("improper immediate value (%lu)"),
-				    (unsigned long) imm_expr->X_add_number);
+			    as_bad (_("improper immediate value (%"PRIu64")"),
+				    imm_expr->X_add_number);
 			}
 		      else
 			{
 			  if (!VALIDATE_S_IMM (imm_expr->X_add_number, n))
-			    as_bad (_("improper immediate value (%li)"),
-				    (long) imm_expr->X_add_number);
+			    as_bad (_("improper immediate value (%"PRIi64")"),
+				    imm_expr->X_add_number);
 			}
 		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
 		      imm_expr->X_op = O_absent;

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics
  2022-09-30  9:42 ` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics Jan Beulich
@ 2022-09-30 10:13   ` Christoph Müllner
  2022-09-30 14:43   ` Nelson Chu
  1 sibling, 0 replies; 29+ messages in thread
From: Christoph Müllner @ 2022-09-30 10:13 UTC (permalink / raw)
  To: Jan Beulich
  Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

[-- Attachment #1: Type: text/plain, Size: 1795 bytes --]

Hi Jan,

Thanks for pointing that out!
I admit, that I was just following the established pattern in this file.
There are four more identical cases in this file ("improper "... outputs).
I'll take care of them (unless you pick them up as well).

Tested-by: Christoph Müllner <christoph.muellner@vrull.eu>

Thanks,
Christoph

On Fri, Sep 30, 2022 at 11:42 AM Jan Beulich <jbeulich@suse.com> wrote:

> There's no need for such workarounds anymore now that we use C99
> uniformly. This addresses several testsuite failures encountered when
> (cross-)building on a 32-bit host.
>
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -3338,14 +3338,14 @@ riscv_ip (char *str, struct riscv_cl_ins
>                       if (!sign)
>                         {
>                           if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> -                           as_bad (_("improper immediate value (%lu)"),
> -                                   (unsigned long)
> imm_expr->X_add_number);
> +                           as_bad (_("improper immediate value
> (%"PRIu64")"),
> +                                   imm_expr->X_add_number);
>                         }
>                       else
>                         {
>                           if (!VALIDATE_S_IMM (imm_expr->X_add_number, n))
> -                           as_bad (_("improper immediate value (%li)"),
> -                                   (long) imm_expr->X_add_number);
> +                           as_bad (_("improper immediate value
> (%"PRIi64")"),
> +                                   imm_expr->X_add_number);
>                         }
>                       INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
>                       imm_expr->X_op = O_absent;
>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats"
  2022-09-30  9:41 ` [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats" Jan Beulich
@ 2022-09-30 10:26   ` Christoph Müllner
  2022-09-30 22:17     ` Palmer Dabbelt
  0 siblings, 1 reply; 29+ messages in thread
From: Christoph Müllner @ 2022-09-30 10:26 UTC (permalink / raw)
  To: Jan Beulich
  Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu

[-- Attachment #1: Type: text/plain, Size: 2470 bytes --]

Hi Jan,

Thanks for pointing that out!

BR
Christoph

On Fri, Sep 30, 2022 at 11:41 AM Jan Beulich <jbeulich@suse.com> wrote:

> Pre- and post-increment/decrement are side effects, the behavior of
> which is undefined when combined with passing an address of the accessed
> variable in the same function invocation. There's no need for the
> increments here - simply adding 1 achieves the intended effect without
> triggering compiler diagnostics (which are fatal with -Werror).
> ---
> Committing as obvious.
>
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1287,10 +1287,10 @@ validate_riscv_insn (const struct riscv_
>                 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit
> S.  */
>                   goto use_imm;
>                 use_imm:
> -                 n = strtol (++oparg, (char **)&oparg, 10);
> +                 n = strtol (oparg + 1, (char **)&oparg, 10);
>                   if (*oparg != '@')
>                     goto unknown_validate_operand;
> -                 s = strtol (++oparg, (char **)&oparg, 10);
> +                 s = strtol (oparg + 1, (char **)&oparg, 10);
>                   oparg--;
>
>                   USE_IMM (n, s);
> @@ -3327,10 +3327,10 @@ riscv_ip (char *str, struct riscv_cl_ins
>                       sign = false;
>                       goto parse_imm;
>                     parse_imm:
> -                     n = strtol (++oparg, (char **)&oparg, 10);
> +                     n = strtol (oparg + 1, (char **)&oparg, 10);
>                       if (*oparg != '@')
>                         goto unknown_riscv_ip_operand;
> -                     s = strtol (++oparg, (char **)&oparg, 10);
> +                     s = strtol (oparg + 1, (char **)&oparg, 10);
>                       oparg--;
>
>                       my_getExpression (imm_expr, asarg);
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -586,10 +586,10 @@ print_insn_args (const char *oparg, insn
>                   sign = false;
>                   goto print_imm;
>                 print_imm:
> -                 n = strtol (++oparg, (char **)&oparg, 10);
> +                 n = strtol (oparg + 1, (char **)&oparg, 10);
>                   if (*oparg != '@')
>                     goto undefined_modifier;
> -                 s = strtol (++oparg, (char **)&oparg, 10);
> +                 s = strtol (oparg + 1, (char **)&oparg, 10);
>                   oparg--;
>
>                   if (!sign)
>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics
  2022-09-30  9:42 ` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics Jan Beulich
  2022-09-30 10:13   ` Christoph Müllner
@ 2022-09-30 14:43   ` Nelson Chu
  1 sibling, 0 replies; 29+ messages in thread
From: Nelson Chu @ 2022-09-30 14:43 UTC (permalink / raw)
  To: Jan Beulich
  Cc: Binutils, Palmer Dabbelt, Andrew Waterman, Jim Wilson,
	Christoph Müllner

Thanks, please commit.

Nelson

On Fri, Sep 30, 2022 at 5:42 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> There's no need for such workarounds anymore now that we use C99
> uniformly. This addresses several testsuite failures encountered when
> (cross-)building on a 32-bit host.
>
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -3338,14 +3338,14 @@ riscv_ip (char *str, struct riscv_cl_ins
>                       if (!sign)
>                         {
>                           if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> -                           as_bad (_("improper immediate value (%lu)"),
> -                                   (unsigned long) imm_expr->X_add_number);
> +                           as_bad (_("improper immediate value (%"PRIu64")"),
> +                                   imm_expr->X_add_number);
>                         }
>                       else
>                         {
>                           if (!VALIDATE_S_IMM (imm_expr->X_add_number, n))
> -                           as_bad (_("improper immediate value (%li)"),
> -                                   (long) imm_expr->X_add_number);
> +                           as_bad (_("improper immediate value (%"PRIi64")"),
> +                                   imm_expr->X_add_number);
>                         }
>                       INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
>                       imm_expr->X_op = O_absent;

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats"
  2022-09-30 10:26   ` Christoph Müllner
@ 2022-09-30 22:17     ` Palmer Dabbelt
  0 siblings, 0 replies; 29+ messages in thread
From: Palmer Dabbelt @ 2022-09-30 22:17 UTC (permalink / raw)
  To: christoph.muellner
  Cc: jbeulich, binutils, Andrew Waterman, Jim Wilson, nelson

On Fri, 30 Sep 2022 03:26:29 PDT (-0700), christoph.muellner@vrull.eu wrote:
> Hi Jan,
>
> Thanks for pointing that out!
>
> BR
> Christoph
>
> On Fri, Sep 30, 2022 at 11:41 AM Jan Beulich <jbeulich@suse.com> wrote:
>
>> Pre- and post-increment/decrement are side effects, the behavior of
>> which is undefined when combined with passing an address of the accessed
>> variable in the same function invocation. There's no need for the
>> increments here - simply adding 1 achieves the intended effect without
>> triggering compiler diagnostics (which are fatal with -Werror).
>> ---
>> Committing as obvious.

Thanks, sorry we missed this one.

That said: I'd argue that the sscanf() version of these routines were 
much less prone to these sorts of string parsing issues, I re-wrote 
these because I'd run into a handful of issues when trying to 
forward-port the original T-Head patches.  I don't remember exactly what 
the issues were, though (sorry if I missed something during the patch 
review, I've been pretty out of it over the last few weeks).

>>
>> --- a/gas/config/tc-riscv.c
>> +++ b/gas/config/tc-riscv.c
>> @@ -1287,10 +1287,10 @@ validate_riscv_insn (const struct riscv_
>>                 case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit
>> S.  */
>>                   goto use_imm;
>>                 use_imm:
>> -                 n = strtol (++oparg, (char **)&oparg, 10);
>> +                 n = strtol (oparg + 1, (char **)&oparg, 10);
>>                   if (*oparg != '@')
>>                     goto unknown_validate_operand;
>> -                 s = strtol (++oparg, (char **)&oparg, 10);
>> +                 s = strtol (oparg + 1, (char **)&oparg, 10);
>>                   oparg--;
>>
>>                   USE_IMM (n, s);
>> @@ -3327,10 +3327,10 @@ riscv_ip (char *str, struct riscv_cl_ins
>>                       sign = false;
>>                       goto parse_imm;
>>                     parse_imm:
>> -                     n = strtol (++oparg, (char **)&oparg, 10);
>> +                     n = strtol (oparg + 1, (char **)&oparg, 10);
>>                       if (*oparg != '@')
>>                         goto unknown_riscv_ip_operand;
>> -                     s = strtol (++oparg, (char **)&oparg, 10);
>> +                     s = strtol (oparg + 1, (char **)&oparg, 10);
>>                       oparg--;
>>
>>                       my_getExpression (imm_expr, asarg);
>> --- a/opcodes/riscv-dis.c
>> +++ b/opcodes/riscv-dis.c
>> @@ -586,10 +586,10 @@ print_insn_args (const char *oparg, insn
>>                   sign = false;
>>                   goto print_imm;
>>                 print_imm:
>> -                 n = strtol (++oparg, (char **)&oparg, 10);
>> +                 n = strtol (oparg + 1, (char **)&oparg, 10);
>>                   if (*oparg != '@')
>>                     goto undefined_modifier;
>> -                 s = strtol (++oparg, (char **)&oparg, 10);
>> +                 s = strtol (oparg + 1, (char **)&oparg, 10);
>>                   oparg--;
>>
>>                   if (!sign)
>>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2022-09-16  9:53       ` Nelson Chu
@ 2023-07-11 21:02         ` Fangrui Song
       [not found]         ` <DS7PR12MB576580071090C394AECFC618CB31A@DS7PR12MB5765.namprd12.prod.outlook.com>
  1 sibling, 0 replies; 29+ messages in thread
From: Fangrui Song @ 2023-07-11 21:02 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Binutils, Nelson Chu

On Fri, Sep 16, 2022 at 2:53 AM Nelson Chu <nelson@rivosinc.com> wrote:
>
> On Thu, Sep 15, 2022 at 3:42 PM Jan Beulich <jbeulich@suse.com> wrote:
> >
> > On 15.09.2022 04:30, Nelson Chu wrote:
> > > On Tue, Sep 13, 2022 at 9:02 PM Jan Beulich <jbeulich@suse.com> wrote:
> > >> --- a/opcodes/riscv-opc.c
> > >> +++ b/opcodes/riscv-opc.c
> > >> @@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
> > >>  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
> > >>  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
> > >>  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
> > >> +{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
> > >>  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
> > >>  {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
> > >> -{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
> > >>  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
> > >>  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
> > >>  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
> > >> @@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
> > >>  {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
> > >>  {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
> > >>  {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
> > >> -{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> > >> -{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
> > >>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
> > >>  {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
> > >>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> > >>  {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
> > >>  {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
> > >> +{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> > >> +{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
> > >
> > > Doesn't ANDI a base instruction?
> >
> > Of course. Like for all aliases, there is a corresponding base
> > instruction. I guess I simply don't understand what you mean to
> > express with the question.
> >
> > >  The operand "d,s,j" of AND is an
> > > alias of ANDI, so the original order seems correct.  Always dump *.i
> > > instructions to the non-i type looks weird, and llvm-dump seems has
> > > the same behavior as current GNU objdump.
> > >
> > > % cat tmp.s
> > > and a0, a1, 0x10
> > > % riscv64-unknown-elf-as tmp.s -o tmp.o
> > > % riscv64-unknown-elf-objdump -d tmp.o
> > >
> > > tmp.o:     file format elf64-littleriscv
> > >
> > >
> > > Disassembly of section .text:
> > >
> > > 0000000000000000 <.text>:
> > >
> > >    0: 0105f513          and a0,a1,16
> >
> > What's weird about that? And if that's weird, would you mind spelling
> > out the conditions under which aliases are to be preferred over base
> > instructions when disassembling? There actually is a "These aliases are
> > for assembly but not disassembly" comment somewhere in the file,
> > clarifying for two of the aliases that they ought to come after their
> > base insns. But for all other aliases which aren't simply a different
> > (but not shorter) name for the same insn (e.g. "bgt" vs "blt") I'd
> > assume the aliases should be preferred, for the reason stated in the
> > patch description. That said - I can see it being a matter of taste
> > for <insn>i vs <insn>, but if so this should be spelled out somewhere.
>
> Yeah, that's what I worried about.  At the beginning, I think dumping
> a base instruction as another base instruction looks weird.  But these
> days I also noticed that - we also dump compressed instructions as
> base i without "c." prefixes, so why I feel weird is just that I'm
> used to it because of historical behavior.  I have no objection to
> this, so please go ahead if there are no objections for a period of
> time.  But if there are any objections, then we probably can mark
> these aliases by something like INSN_ALIAS_CANNOT_DUMP in the opcode
> table, and that's what Kito suggested to me before, but I didn't think
> it was a serious problem at the time.
>
> Thanks
> Nelson

I apologize as I haven't read all prior discussions. For many
instructions, the "i" form is written in the ISA manual and prevalent.
I wonder whether we can give these add/and/xor/etc without "i" lower
priority so that objdump -d will not show them, even without using -M
no-aliases.

% cat b.s
add a0,a1,13
and a2,a3,4
xor a2,a3,4
or a2,a3,4
sll a2,a3,4
% riscv64-linux-gnu-gcc -c b.s
% ~/Dev/binutils-gdb/out/riscv64/binutils/objdump -d b.o

b.o:     file format elf64-littleriscv


Disassembly of section .text:

0000000000000000 <.text>:
   0:   00d58513                add     a0,a1,13
   4:   0046f613                and     a2,a3,4
   8:   0046c613                xor     a2,a3,4
   c:   0046e613                or      a2,a3,4
  10:   00469613                sll     a2,a3,0x4


When LLVM integrated assembler added these aliases
(https://reviews.llvm.org/D50046), these instructions are assigned a
low priority "let EmitPriority = 0" so llvm-objdump -d will never show
them.

> > > % llvm-objdump -d tmp.o
> > >
> > > tmp.o: file format elf64-littleriscv
> > >
> > > Disassembly of section .text:
> > >
> > > 0000000000000000 <$x>:
> > >        0: 13 f5 05 01  andi a0, a1, 16
> >
> > I don't think I view llvm as a "canonical reference". Perhaps they merely
> > followed the GNU behavior?
> >
> > Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
       [not found]         ` <DS7PR12MB576580071090C394AECFC618CB31A@DS7PR12MB5765.namprd12.prod.outlook.com>
@ 2023-07-12  8:15           ` Jan Beulich
  2023-07-14 21:25             ` Fangrui Song
       [not found]             ` <MN0PR12MB57613B59178FAADE5FCD3837CB34A@MN0PR12MB5761.namprd12.prod.outlook.com>
  0 siblings, 2 replies; 29+ messages in thread
From: Jan Beulich @ 2023-07-12  8:15 UTC (permalink / raw)
  To: Fangrui Song; +Cc: Binutils, Nelson Chu

On 11.07.2023 23:02, Fangrui Song wrote:
> On Fri, Sep 16, 2022 at 2:53 AM Nelson Chu <nelson@rivosinc.com> wrote:
>>
>> On Thu, Sep 15, 2022 at 3:42 PM Jan Beulich <jbeulich@suse.com> wrote:
>>>
>>> On 15.09.2022 04:30, Nelson Chu wrote:
>>>> On Tue, Sep 13, 2022 at 9:02 PM Jan Beulich <jbeulich@suse.com> wrote:
>>>>> --- a/opcodes/riscv-opc.c
>>>>> +++ b/opcodes/riscv-opc.c
>>>>> @@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
>>>>>  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
>>>>>  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
>>>>>  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
>>>>> +{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>>>>>  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
>>>>>  {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
>>>>> -{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>>>>>  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
>>>>>  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
>>>>>  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
>>>>> @@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
>>>>>  {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
>>>>>  {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
>>>>>  {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
>>>>> -{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>>>>> -{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
>>>>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>>>>>  {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>>>>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>>>>>  {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
>>>>>  {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
>>>>> +{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>>>>> +{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
>>>>
>>>> Doesn't ANDI a base instruction?
>>>
>>> Of course. Like for all aliases, there is a corresponding base
>>> instruction. I guess I simply don't understand what you mean to
>>> express with the question.
>>>
>>>>  The operand "d,s,j" of AND is an
>>>> alias of ANDI, so the original order seems correct.  Always dump *.i
>>>> instructions to the non-i type looks weird, and llvm-dump seems has
>>>> the same behavior as current GNU objdump.
>>>>
>>>> % cat tmp.s
>>>> and a0, a1, 0x10
>>>> % riscv64-unknown-elf-as tmp.s -o tmp.o
>>>> % riscv64-unknown-elf-objdump -d tmp.o
>>>>
>>>> tmp.o:     file format elf64-littleriscv
>>>>
>>>>
>>>> Disassembly of section .text:
>>>>
>>>> 0000000000000000 <.text>:
>>>>
>>>>    0: 0105f513          and a0,a1,16
>>>
>>> What's weird about that? And if that's weird, would you mind spelling
>>> out the conditions under which aliases are to be preferred over base
>>> instructions when disassembling? There actually is a "These aliases are
>>> for assembly but not disassembly" comment somewhere in the file,
>>> clarifying for two of the aliases that they ought to come after their
>>> base insns. But for all other aliases which aren't simply a different
>>> (but not shorter) name for the same insn (e.g. "bgt" vs "blt") I'd
>>> assume the aliases should be preferred, for the reason stated in the
>>> patch description. That said - I can see it being a matter of taste
>>> for <insn>i vs <insn>, but if so this should be spelled out somewhere.
>>
>> Yeah, that's what I worried about.  At the beginning, I think dumping
>> a base instruction as another base instruction looks weird.  But these
>> days I also noticed that - we also dump compressed instructions as
>> base i without "c." prefixes, so why I feel weird is just that I'm
>> used to it because of historical behavior.  I have no objection to
>> this, so please go ahead if there are no objections for a period of
>> time.  But if there are any objections, then we probably can mark
>> these aliases by something like INSN_ALIAS_CANNOT_DUMP in the opcode
>> table, and that's what Kito suggested to me before, but I didn't think
>> it was a serious problem at the time.
>>
>> Thanks
>> Nelson
> 
> I apologize as I haven't read all prior discussions. For many
> instructions, the "i" form is written in the ISA manual and prevalent.

Why "prevalent"? The "i"-less forms are mentioned there as well, aren't
they? Then why not use them ...

> I wonder whether we can give these add/and/xor/etc without "i" lower
> priority so that objdump -d will not show them, even without using -M
> no-aliases.

... unless use of aliases was suppressed? In other arches' assembly
that I know (to some degree) and which knows the concept of aliases,
aliases are typically the preferred way of disassembling, for
typically producing easier to grok output.

There are other aspects to consider here, related to the handling of
equates in assembly sources. I did bring this up before, but it feels
like a minefield - it first would need firmly establishing what exactly
assembler behavior is intended to be. Aiui no-one has properly thought
of this, including for the (surprisingly similar) handling in tc-mips.c
(making me guess that RISC-V code may have been derived from that).

Jan

> % cat b.s
> add a0,a1,13
> and a2,a3,4
> xor a2,a3,4
> or a2,a3,4
> sll a2,a3,4
> % riscv64-linux-gnu-gcc -c b.s
> % ~/Dev/binutils-gdb/out/riscv64/binutils/objdump -d b.o
> 
> b.o:     file format elf64-littleriscv
> 
> 
> Disassembly of section .text:
> 
> 0000000000000000 <.text>:
>    0:   00d58513                add     a0,a1,13
>    4:   0046f613                and     a2,a3,4
>    8:   0046c613                xor     a2,a3,4
>    c:   0046e613                or      a2,a3,4
>   10:   00469613                sll     a2,a3,0x4
> 
> 
> When LLVM integrated assembler added these aliases
> (https://reviews.llvm.org/D50046), these instructions are assigned a
> low priority "let EmitPriority = 0" so llvm-objdump -d will never show
> them.


^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2023-07-12  8:15           ` Jan Beulich
@ 2023-07-14 21:25             ` Fangrui Song
       [not found]             ` <MN0PR12MB57613B59178FAADE5FCD3837CB34A@MN0PR12MB5761.namprd12.prod.outlook.com>
  1 sibling, 0 replies; 29+ messages in thread
From: Fangrui Song @ 2023-07-14 21:25 UTC (permalink / raw)
  To: Jan Beulich
  Cc: Binutils, Nelson Chu, Jessica Clarke, Stefan O'Rear, Kito Cheng

On Wed, Jul 12, 2023 at 1:15 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 11.07.2023 23:02, Fangrui Song wrote:
> > On Fri, Sep 16, 2022 at 2:53 AM Nelson Chu <nelson@rivosinc.com> wrote:
> >>
> >> On Thu, Sep 15, 2022 at 3:42 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>>
> >>> On 15.09.2022 04:30, Nelson Chu wrote:
> >>>> On Tue, Sep 13, 2022 at 9:02 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>> --- a/opcodes/riscv-opc.c
> >>>>> +++ b/opcodes/riscv-opc.c
> >>>>> @@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
> >>>>>  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
> >>>>>  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
> >>>>>  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
> >>>>> +{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
> >>>>>  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
> >>>>>  {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
> >>>>> -{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
> >>>>>  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
> >>>>>  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
> >>>>>  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
> >>>>> @@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
> >>>>>  {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
> >>>>>  {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
> >>>>>  {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
> >>>>> -{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> >>>>> -{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
> >>>>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
> >>>>>  {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
> >>>>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> >>>>>  {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
> >>>>>  {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
> >>>>> +{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
> >>>>> +{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
> >>>>
> >>>> Doesn't ANDI a base instruction?
> >>>
> >>> Of course. Like for all aliases, there is a corresponding base
> >>> instruction. I guess I simply don't understand what you mean to
> >>> express with the question.
> >>>
> >>>>  The operand "d,s,j" of AND is an
> >>>> alias of ANDI, so the original order seems correct.  Always dump *.i
> >>>> instructions to the non-i type looks weird, and llvm-dump seems has
> >>>> the same behavior as current GNU objdump.
> >>>>
> >>>> % cat tmp.s
> >>>> and a0, a1, 0x10
> >>>> % riscv64-unknown-elf-as tmp.s -o tmp.o
> >>>> % riscv64-unknown-elf-objdump -d tmp.o
> >>>>
> >>>> tmp.o:     file format elf64-littleriscv
> >>>>
> >>>>
> >>>> Disassembly of section .text:
> >>>>
> >>>> 0000000000000000 <.text>:
> >>>>
> >>>>    0: 0105f513          and a0,a1,16
> >>>
> >>> What's weird about that? And if that's weird, would you mind spelling
> >>> out the conditions under which aliases are to be preferred over base
> >>> instructions when disassembling? There actually is a "These aliases are
> >>> for assembly but not disassembly" comment somewhere in the file,
> >>> clarifying for two of the aliases that they ought to come after their
> >>> base insns. But for all other aliases which aren't simply a different
> >>> (but not shorter) name for the same insn (e.g. "bgt" vs "blt") I'd
> >>> assume the aliases should be preferred, for the reason stated in the
> >>> patch description. That said - I can see it being a matter of taste
> >>> for <insn>i vs <insn>, but if so this should be spelled out somewhere.
> >>
> >> Yeah, that's what I worried about.  At the beginning, I think dumping
> >> a base instruction as another base instruction looks weird.  But these
> >> days I also noticed that - we also dump compressed instructions as
> >> base i without "c." prefixes, so why I feel weird is just that I'm
> >> used to it because of historical behavior.  I have no objection to
> >> this, so please go ahead if there are no objections for a period of
> >> time.  But if there are any objections, then we probably can mark
> >> these aliases by something like INSN_ALIAS_CANNOT_DUMP in the opcode
> >> table, and that's what Kito suggested to me before, but I didn't think
> >> it was a serious problem at the time.
> >>
> >> Thanks
> >> Nelson
> >
> > I apologize as I haven't read all prior discussions. For many
> > instructions, the "i" form is written in the ISA manual and prevalent.
>
> Why "prevalent"? The "i"-less forms are mentioned there as well, aren't
> they? Then why not use them ...

I think aliases like "add rd,rs,imm" (without "i") should be treated
as deprecated aliases that we keep just for compatibility.
We should not endorse the use cases by making objdump -d "prefer" this form.

When I brought up the topic in the #riscv channel on libera.chat, I
got a lot of complaints about having these "deprecated" aliases from
folks, including courmisch, jrtc27, muurkha, sorear.
As I happen to know two folks' email addresses, I have CCed them in this thread.

> > I wonder whether we can give these add/and/xor/etc without "i" lower
> > priority so that objdump -d will not show them, even without using -M
> > no-aliases.
>
> ... unless use of aliases was suppressed? In other arches' assembly
> that I know (to some degree) and which knows the concept of aliases,
> aliases are typically the preferred way of disassembling, for
> typically producing easier to grok output.

AIUI aliases for other architectures are indeeded preferred (use my
understanding of llvm-objdump -d output).
This RISC-V case is not, though.


> There are other aspects to consider here, related to the handling of
> equates in assembly sources. I did bring this up before, but it feels
> like a minefield - it first would need firmly establishing what exactly
> assembler behavior is intended to be. Aiui no-one has properly thought
> of this, including for the (surprisingly similar) handling in tc-mips.c
> (making me guess that RISC-V code may have been derived from that).
>
> Jan

My knowledge about GNU assembler is quite limited...
I hope that other RISC-V folks can answer this question.


> > % cat b.s
> > add a0,a1,13
> > and a2,a3,4
> > xor a2,a3,4
> > or a2,a3,4
> > sll a2,a3,4
> > % riscv64-linux-gnu-gcc -c b.s
> > % ~/Dev/binutils-gdb/out/riscv64/binutils/objdump -d b.o
> >
> > b.o:     file format elf64-littleriscv
> >
> >
> > Disassembly of section .text:
> >
> > 0000000000000000 <.text>:
> >    0:   00d58513                add     a0,a1,13
> >    4:   0046f613                and     a2,a3,4
> >    8:   0046c613                xor     a2,a3,4
> >    c:   0046e613                or      a2,a3,4
> >   10:   00469613                sll     a2,a3,0x4
> >
> >
> > When LLVM integrated assembler added these aliases
> > (https://reviews.llvm.org/D50046), these instructions are assigned a
> > low priority "let EmitPriority = 0" so llvm-objdump -d will never show
> > them.
>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
       [not found]             ` <MN0PR12MB57613B59178FAADE5FCD3837CB34A@MN0PR12MB5761.namprd12.prod.outlook.com>
@ 2023-07-14 22:08               ` Stefan O'Rear
  2023-07-17  6:50                 ` Jan Beulich
  0 siblings, 1 reply; 29+ messages in thread
From: Stefan O'Rear @ 2023-07-14 22:08 UTC (permalink / raw)
  To: Fangrui Song, Jan Beulich
  Cc: Binutils, Nelson Chu, Jessica Clarke, kito.cheng

On Fri, Jul 14, 2023, at 5:25 PM, Fangrui Song wrote:
> On Wed, Jul 12, 2023 at 1:15 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 11.07.2023 23:02, Fangrui Song wrote:
>> > On Fri, Sep 16, 2022 at 2:53 AM Nelson Chu <nelson@rivosinc.com> wrote:
>> >>
>> >> On Thu, Sep 15, 2022 at 3:42 PM Jan Beulich <jbeulich@suse.com> wrote:
>> >>>
>> >>> On 15.09.2022 04:30, Nelson Chu wrote:
>> >>>> On Tue, Sep 13, 2022 at 9:02 PM Jan Beulich <jbeulich@suse.com> wrote:
>> >>>>> --- a/opcodes/riscv-opc.c
>> >>>>> +++ b/opcodes/riscv-opc.c
>> >>>>> @@ -290,9 +290,9 @@ const struct riscv_opcode riscv_opcodes[
>> >>>>>  {"jalr",        0, INSN_CLASS_I, "d,s,j",     MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
>> >>>>>  {"j",           0, INSN_CLASS_C, "Ca",        MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
>> >>>>>  {"j",           0, INSN_CLASS_I, "a",         MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
>> >>>>> +{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>> >>>>>  {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
>> >>>>>  {"jal",        32, INSN_CLASS_C, "Ca",        MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR },
>> >>>>> -{"jal",         0, INSN_CLASS_I, "a",         MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
>> >>>>>  {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
>> >>>>>  {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
>> >>>>>  {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
>> >>>>> @@ -310,13 +310,13 @@ const struct riscv_opcode riscv_opcodes[
>> >>>>>  {"move",        0, INSN_CLASS_C, "d,CV",      MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
>> >>>>>  {"move",        0, INSN_CLASS_I, "d,s",       MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
>> >>>>>  {"zext.b",      0, INSN_CLASS_I, "d,s",       MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
>> >>>>> -{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>> >>>>> -{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
>> >>>>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>> >>>>>  {"and",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
>> >>>>>  {"and",         0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>> >>>>>  {"and",         0, INSN_CLASS_I, "d,s,t",     MATCH_AND, MASK_AND, match_opcode, 0 },
>> >>>>>  {"and",         0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
>> >>>>> +{"andi",        0, INSN_CLASS_C, "Cs,Cw,Co",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
>> >>>>> +{"andi",        0, INSN_CLASS_I, "d,s,j",     MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
>> >>>>
>> >>>> Doesn't ANDI a base instruction?
>> >>>
>> >>> Of course. Like for all aliases, there is a corresponding base
>> >>> instruction. I guess I simply don't understand what you mean to
>> >>> express with the question.
>> >>>
>> >>>>  The operand "d,s,j" of AND is an
>> >>>> alias of ANDI, so the original order seems correct.  Always dump *.i
>> >>>> instructions to the non-i type looks weird, and llvm-dump seems has
>> >>>> the same behavior as current GNU objdump.
>> >>>>
>> >>>> % cat tmp.s
>> >>>> and a0, a1, 0x10
>> >>>> % riscv64-unknown-elf-as tmp.s -o tmp.o
>> >>>> % riscv64-unknown-elf-objdump -d tmp.o
>> >>>>
>> >>>> tmp.o:     file format elf64-littleriscv
>> >>>>
>> >>>>
>> >>>> Disassembly of section .text:
>> >>>>
>> >>>> 0000000000000000 <.text>:
>> >>>>
>> >>>>    0: 0105f513          and a0,a1,16
>> >>>
>> >>> What's weird about that? And if that's weird, would you mind spelling
>> >>> out the conditions under which aliases are to be preferred over base
>> >>> instructions when disassembling? There actually is a "These aliases are
>> >>> for assembly but not disassembly" comment somewhere in the file,
>> >>> clarifying for two of the aliases that they ought to come after their
>> >>> base insns. But for all other aliases which aren't simply a different
>> >>> (but not shorter) name for the same insn (e.g. "bgt" vs "blt") I'd
>> >>> assume the aliases should be preferred, for the reason stated in the
>> >>> patch description. That said - I can see it being a matter of taste
>> >>> for <insn>i vs <insn>, but if so this should be spelled out somewhere.
>> >>
>> >> Yeah, that's what I worried about.  At the beginning, I think dumping
>> >> a base instruction as another base instruction looks weird.  But these
>> >> days I also noticed that - we also dump compressed instructions as
>> >> base i without "c." prefixes, so why I feel weird is just that I'm
>> >> used to it because of historical behavior.  I have no objection to
>> >> this, so please go ahead if there are no objections for a period of
>> >> time.  But if there are any objections, then we probably can mark
>> >> these aliases by something like INSN_ALIAS_CANNOT_DUMP in the opcode
>> >> table, and that's what Kito suggested to me before, but I didn't think
>> >> it was a serious problem at the time.
>> >>
>> >> Thanks
>> >> Nelson
>> >
>> > I apologize as I haven't read all prior discussions. For many
>> > instructions, the "i" form is written in the ISA manual and prevalent.
>>
>> Why "prevalent"? The "i"-less forms are mentioned there as well, aren't
>> they? Then why not use them ...
>
> I think aliases like "add rd,rs,imm" (without "i") should be treated
> as deprecated aliases that we keep just for compatibility.
> We should not endorse the use cases by making objdump -d "prefer" this form.
>
> When I brought up the topic in the #riscv channel on libera.chat, I
> got a lot of complaints about having these "deprecated" aliases from
> folks, including courmisch, jrtc27, muurkha, sorear.
> As I happen to know two folks' email addresses, I have CCed them in this thread.
>
>> > I wonder whether we can give these add/and/xor/etc without "i" lower
>> > priority so that objdump -d will not show them, even without using -M
>> > no-aliases.
>>
>> ... unless use of aliases was suppressed? In other arches' assembly
>> that I know (to some degree) and which knows the concept of aliases,
>> aliases are typically the preferred way of disassembling, for
>> typically producing easier to grok output.
>
> AIUI aliases for other architectures are indeeded preferred (use my
> understanding of llvm-objdump -d output).
> This RISC-V case is not, though.

The aliases that are documented in [1] are preferred for use in disassembly.
The other aliases, which gas supports for compatibility with old versions of
itself but which were never part of any spec, are not preferred.

-s

[1]: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md

>> There are other aspects to consider here, related to the handling of
>> equates in assembly sources. I did bring this up before, but it feels
>> like a minefield - it first would need firmly establishing what exactly
>> assembler behavior is intended to be. Aiui no-one has properly thought
>> of this, including for the (surprisingly similar) handling in tc-mips.c
>> (making me guess that RISC-V code may have been derived from that).
>>
>> Jan
>
> My knowledge about GNU assembler is quite limited...
> I hope that other RISC-V folks can answer this question.
>
>
>> > % cat b.s
>> > add a0,a1,13
>> > and a2,a3,4
>> > xor a2,a3,4
>> > or a2,a3,4
>> > sll a2,a3,4
>> > % riscv64-linux-gnu-gcc -c b.s
>> > % ~/Dev/binutils-gdb/out/riscv64/binutils/objdump -d b.o
>> >
>> > b.o:     file format elf64-littleriscv
>> >
>> >
>> > Disassembly of section .text:
>> >
>> > 0000000000000000 <.text>:
>> >    0:   00d58513                add     a0,a1,13
>> >    4:   0046f613                and     a2,a3,4
>> >    8:   0046c613                xor     a2,a3,4
>> >    c:   0046e613                or      a2,a3,4
>> >   10:   00469613                sll     a2,a3,0x4
>> >
>> >
>> > When LLVM integrated assembler added these aliases
>> > (https://reviews.llvm.org/D50046), these instructions are assigned a
>> > low priority "let EmitPriority = 0" so llvm-objdump -d will never show
>> > them.
>>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2023-07-14 22:08               ` Stefan O'Rear
@ 2023-07-17  6:50                 ` Jan Beulich
  2023-07-21 22:16                   ` Song Fangrui
       [not found]                   ` <DS7PR12MB57658EF28577B41BF35C5E7CCB3FA@DS7PR12MB5765.namprd12.prod.outlook.com>
  0 siblings, 2 replies; 29+ messages in thread
From: Jan Beulich @ 2023-07-17  6:50 UTC (permalink / raw)
  To: Stefan O'Rear, Fangrui Song
  Cc: Binutils, Nelson Chu, Jessica Clarke, kito.cheng

On 15.07.2023 00:08, Stefan O'Rear wrote:
> On Fri, Jul 14, 2023, at 5:25 PM, Fangrui Song wrote:
>> On Wed, Jul 12, 2023 at 1:15 AM Jan Beulich <jbeulich@suse.com> wrote:
>>> On 11.07.2023 23:02, Fangrui Song wrote:
>>>> I apologize as I haven't read all prior discussions. For many
>>>> instructions, the "i" form is written in the ISA manual and prevalent.
>>>
>>> Why "prevalent"? The "i"-less forms are mentioned there as well, aren't
>>> they? Then why not use them ...
>>
>> I think aliases like "add rd,rs,imm" (without "i") should be treated
>> as deprecated aliases that we keep just for compatibility.

That's a matter of taste, I'm inclined to say. But see below.

>> We should not endorse the use cases by making objdump -d "prefer" this form.
>>
>> When I brought up the topic in the #riscv channel on libera.chat, I
>> got a lot of complaints about having these "deprecated" aliases from
>> folks, including courmisch, jrtc27, muurkha, sorear.
>> As I happen to know two folks' email addresses, I have CCed them in this thread.
>>
>>>> I wonder whether we can give these add/and/xor/etc without "i" lower
>>>> priority so that objdump -d will not show them, even without using -M
>>>> no-aliases.
>>>
>>> ... unless use of aliases was suppressed? In other arches' assembly
>>> that I know (to some degree) and which knows the concept of aliases,
>>> aliases are typically the preferred way of disassembling, for
>>> typically producing easier to grok output.
>>
>> AIUI aliases for other architectures are indeeded preferred (use my
>> understanding of llvm-objdump -d output).
>> This RISC-V case is not, though.
> 
> The aliases that are documented in [1] are preferred for use in disassembly.
> The other aliases, which gas supports for compatibility with old versions of
> itself but which were never part of any spec, are not preferred.

This would be a fair policy, as long as there's a not overly troublesome
way of getting further entries on that list (whenever obvious instances
turn up). My main goal, after all, is consistency. What exact policy
underlies this is secondary to me.

Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2023-07-17  6:50                 ` Jan Beulich
@ 2023-07-21 22:16                   ` Song Fangrui
  2023-07-22 15:14                     ` Jeff Law
       [not found]                   ` <DS7PR12MB57658EF28577B41BF35C5E7CCB3FA@DS7PR12MB5765.namprd12.prod.outlook.com>
  1 sibling, 1 reply; 29+ messages in thread
From: Song Fangrui @ 2023-07-21 22:16 UTC (permalink / raw)
  To: Jan Beulich, Nelson Chu
  Cc: Stefan O'Rear, Binutils, Jessica Clarke, kito.cheng

On Sun, Jul 16, 2023 at 11:50 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 15.07.2023 00:08, Stefan O'Rear wrote:
> > On Fri, Jul 14, 2023, at 5:25 PM, Fangrui Song wrote:
> >> On Wed, Jul 12, 2023 at 1:15 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>> On 11.07.2023 23:02, Fangrui Song wrote:
> >>>> I apologize as I haven't read all prior discussions. For many
> >>>> instructions, the "i" form is written in the ISA manual and prevalent.
> >>>
> >>> Why "prevalent"? The "i"-less forms are mentioned there as well, aren't
> >>> they? Then why not use them ...
> >>
> >> I think aliases like "add rd,rs,imm" (without "i") should be treated
> >> as deprecated aliases that we keep just for compatibility.
>
> That's a matter of taste, I'm inclined to say. But see below.
>
> >> We should not endorse the use cases by making objdump -d "prefer" this form.
> >>
> >> When I brought up the topic in the #riscv channel on libera.chat, I
> >> got a lot of complaints about having these "deprecated" aliases from
> >> folks, including courmisch, jrtc27, muurkha, sorear.
> >> As I happen to know two folks' email addresses, I have CCed them in this thread.
> >>
> >>>> I wonder whether we can give these add/and/xor/etc without "i" lower
> >>>> priority so that objdump -d will not show them, even without using -M
> >>>> no-aliases.
> >>>
> >>> ... unless use of aliases was suppressed? In other arches' assembly
> >>> that I know (to some degree) and which knows the concept of aliases,
> >>> aliases are typically the preferred way of disassembling, for
> >>> typically producing easier to grok output.
> >>
> >> AIUI aliases for other architectures are indeeded preferred (use my
> >> understanding of llvm-objdump -d output).
> >> This RISC-V case is not, though.
> >
> > The aliases that are documented in [1] are preferred for use in disassembly.
> > The other aliases, which gas supports for compatibility with old versions of
> > itself but which were never part of any spec, are not preferred.
>
> This would be a fair policy, as long as there's a not overly troublesome
> way of getting further entries on that list (whenever obvious instances
> turn up). My main goal, after all, is consistency. What exact policy
> underlies this is secondary to me.
>
> Jan

Jan and Nelson, If this is agreed that we should use "addi" instead of
the gas alias "add" in situations like addi x0, x0, 1, can either of
you make a change to restore the old behavior? Thanks!

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2023-07-21 22:16                   ` Song Fangrui
@ 2023-07-22 15:14                     ` Jeff Law
  2023-07-22 16:55                       ` Andrew Waterman
  0 siblings, 1 reply; 29+ messages in thread
From: Jeff Law @ 2023-07-22 15:14 UTC (permalink / raw)
  To: Song Fangrui, Jan Beulich, Nelson Chu
  Cc: Stefan O'Rear, Binutils, Jessica Clarke, kito.cheng



On 7/21/23 16:16, Song Fangrui wrote:
> On Sun, Jul 16, 2023 at 11:50 PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 15.07.2023 00:08, Stefan O'Rear wrote:
>>> On Fri, Jul 14, 2023, at 5:25 PM, Fangrui Song wrote:
>>>> On Wed, Jul 12, 2023 at 1:15 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>> On 11.07.2023 23:02, Fangrui Song wrote:
>>>>>> I apologize as I haven't read all prior discussions. For many
>>>>>> instructions, the "i" form is written in the ISA manual and prevalent.
>>>>>
>>>>> Why "prevalent"? The "i"-less forms are mentioned there as well, aren't
>>>>> they? Then why not use them ...
>>>>
>>>> I think aliases like "add rd,rs,imm" (without "i") should be treated
>>>> as deprecated aliases that we keep just for compatibility.
>>
>> That's a matter of taste, I'm inclined to say. But see below.
>>
>>>> We should not endorse the use cases by making objdump -d "prefer" this form.
>>>>
>>>> When I brought up the topic in the #riscv channel on libera.chat, I
>>>> got a lot of complaints about having these "deprecated" aliases from
>>>> folks, including courmisch, jrtc27, muurkha, sorear.
>>>> As I happen to know two folks' email addresses, I have CCed them in this thread.
>>>>
>>>>>> I wonder whether we can give these add/and/xor/etc without "i" lower
>>>>>> priority so that objdump -d will not show them, even without using -M
>>>>>> no-aliases.
>>>>>
>>>>> ... unless use of aliases was suppressed? In other arches' assembly
>>>>> that I know (to some degree) and which knows the concept of aliases,
>>>>> aliases are typically the preferred way of disassembling, for
>>>>> typically producing easier to grok output.
>>>>
>>>> AIUI aliases for other architectures are indeeded preferred (use my
>>>> understanding of llvm-objdump -d output).
>>>> This RISC-V case is not, though.
>>>
>>> The aliases that are documented in [1] are preferred for use in disassembly.
>>> The other aliases, which gas supports for compatibility with old versions of
>>> itself but which were never part of any spec, are not preferred.
>>
>> This would be a fair policy, as long as there's a not overly troublesome
>> way of getting further entries on that list (whenever obvious instances
>> turn up). My main goal, after all, is consistency. What exact policy
>> underlies this is secondary to me.
>>
>> Jan
> 
> Jan and Nelson, If this is agreed that we should use "addi" instead of
> the gas alias "add" in situations like addi x0, x0, 1, can either of
> you make a change to restore the old behavior? Thanks!
Given the ISA docs use "addi", we should follow that.  While GAS does 
provide aliases which allow things like "add" with an immediate operand, 
those are non-standard and should not be preferred.

In an ideal world the output of objdump should be compatible with what 
GAS accepts as well as what the LLVM toolchain accepts -- while we may 
not be there, there's no good reason to introduce additional 
inconsistencies across the tools.

So as Stefan noted, there are a set of aliases defined by the RISC-V 
assembly reference.  Those are the only ones that should be preferred.

> https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md


jeff


^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2023-07-22 15:14                     ` Jeff Law
@ 2023-07-22 16:55                       ` Andrew Waterman
  0 siblings, 0 replies; 29+ messages in thread
From: Andrew Waterman @ 2023-07-22 16:55 UTC (permalink / raw)
  To: Jeff Law
  Cc: Song Fangrui, Jan Beulich, Nelson Chu, Stefan O'Rear,
	Binutils, Jessica Clarke, kito.cheng

Just as a reminder, the official aliases are not engraved on stone
tablets.  I suspect that, as we go through this exercise, we'll find
cases where we really should retain the aliases, in which case we
should just update the official document.

Aside from that comment, this all sounds fine to me (provided, of
course, the assembler will continue to accept these aliases in
perpetuity).


On Sat, Jul 22, 2023 at 8:15 AM Jeff Law via Binutils
<binutils@sourceware.org> wrote:
>
>
>
> On 7/21/23 16:16, Song Fangrui wrote:
> > On Sun, Jul 16, 2023 at 11:50 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 15.07.2023 00:08, Stefan O'Rear wrote:
> >>> On Fri, Jul 14, 2023, at 5:25 PM, Fangrui Song wrote:
> >>>> On Wed, Jul 12, 2023 at 1:15 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>> On 11.07.2023 23:02, Fangrui Song wrote:
> >>>>>> I apologize as I haven't read all prior discussions. For many
> >>>>>> instructions, the "i" form is written in the ISA manual and prevalent.
> >>>>>
> >>>>> Why "prevalent"? The "i"-less forms are mentioned there as well, aren't
> >>>>> they? Then why not use them ...
> >>>>
> >>>> I think aliases like "add rd,rs,imm" (without "i") should be treated
> >>>> as deprecated aliases that we keep just for compatibility.
> >>
> >> That's a matter of taste, I'm inclined to say. But see below.
> >>
> >>>> We should not endorse the use cases by making objdump -d "prefer" this form.
> >>>>
> >>>> When I brought up the topic in the #riscv channel on libera.chat, I
> >>>> got a lot of complaints about having these "deprecated" aliases from
> >>>> folks, including courmisch, jrtc27, muurkha, sorear.
> >>>> As I happen to know two folks' email addresses, I have CCed them in this thread.
> >>>>
> >>>>>> I wonder whether we can give these add/and/xor/etc without "i" lower
> >>>>>> priority so that objdump -d will not show them, even without using -M
> >>>>>> no-aliases.
> >>>>>
> >>>>> ... unless use of aliases was suppressed? In other arches' assembly
> >>>>> that I know (to some degree) and which knows the concept of aliases,
> >>>>> aliases are typically the preferred way of disassembling, for
> >>>>> typically producing easier to grok output.
> >>>>
> >>>> AIUI aliases for other architectures are indeeded preferred (use my
> >>>> understanding of llvm-objdump -d output).
> >>>> This RISC-V case is not, though.
> >>>
> >>> The aliases that are documented in [1] are preferred for use in disassembly.
> >>> The other aliases, which gas supports for compatibility with old versions of
> >>> itself but which were never part of any spec, are not preferred.
> >>
> >> This would be a fair policy, as long as there's a not overly troublesome
> >> way of getting further entries on that list (whenever obvious instances
> >> turn up). My main goal, after all, is consistency. What exact policy
> >> underlies this is secondary to me.
> >>
> >> Jan
> >
> > Jan and Nelson, If this is agreed that we should use "addi" instead of
> > the gas alias "add" in situations like addi x0, x0, 1, can either of
> > you make a change to restore the old behavior? Thanks!
> Given the ISA docs use "addi", we should follow that.  While GAS does
> provide aliases which allow things like "add" with an immediate operand,
> those are non-standard and should not be preferred.
>
> In an ideal world the output of objdump should be compatible with what
> GAS accepts as well as what the LLVM toolchain accepts -- while we may
> not be there, there's no good reason to introduce additional
> inconsistencies across the tools.
>
> So as Stefan noted, there are a set of aliases defined by the RISC-V
> assembly reference.  Those are the only ones that should be preferred.
>
> > https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
>
>
> jeff
>

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
       [not found]                   ` <DS7PR12MB57658EF28577B41BF35C5E7CCB3FA@DS7PR12MB5765.namprd12.prod.outlook.com>
@ 2023-07-24  7:23                     ` Jan Beulich
  2023-08-30  3:14                       ` Fangrui Song
  0 siblings, 1 reply; 29+ messages in thread
From: Jan Beulich @ 2023-07-24  7:23 UTC (permalink / raw)
  To: Song Fangrui
  Cc: Stefan O'Rear, Binutils, Jessica Clarke, kito.cheng, Nelson Chu

On 22.07.2023 00:15, Song Fangrui wrote:
> Jan and Nelson, If this is agreed that we should use "addi" instead of
> the gas alias "add" in situations like addi x0, x0, 1, can either of
> you make a change to restore the old behavior? Thanks!

I've added an item to my todo list. No promises as to a timeline, though
(but we have some time now that 2.41 is about to be cut, and this isn't
a change I would see us trying to still force into there).

Jan

^ permalink raw reply	[flat|nested] 29+ messages in thread

* Re: [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling
  2023-07-24  7:23                     ` Jan Beulich
@ 2023-08-30  3:14                       ` Fangrui Song
  0 siblings, 0 replies; 29+ messages in thread
From: Fangrui Song @ 2023-08-30  3:14 UTC (permalink / raw)
  To: Jan Beulich
  Cc: Stefan O'Rear, Binutils, Jessica Clarke, kito.cheng, Nelson Chu

On Mon, Jul 24, 2023 at 12:23 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 22.07.2023 00:15, Song Fangrui wrote:
> > Jan and Nelson, If this is agreed that we should use "addi" instead of
> > the gas alias "add" in situations like addi x0, x0, 1, can either of
> > you make a change to restore the old behavior? Thanks!
>
> I've added an item to my todo list. No promises as to a timeline, though
> (but we have some time now that 2.41 is about to be cut, and this isn't
> a change I would see us trying to still force into there).
>
> Jan

Thank you! binutils 2.41 has been out. I hope that this alias problem
can be fixed for 2.42...

^ permalink raw reply	[flat|nested] 29+ messages in thread

end of thread, other threads:[~2023-08-30  3:23 UTC | newest]

Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
2022-09-13 13:02 ` [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling Jan Beulich
2022-09-15  2:30   ` Nelson Chu
2022-09-15  7:42     ` Jan Beulich
2022-09-16  9:53       ` Nelson Chu
2023-07-11 21:02         ` Fangrui Song
     [not found]         ` <DS7PR12MB576580071090C394AECFC618CB31A@DS7PR12MB5765.namprd12.prod.outlook.com>
2023-07-12  8:15           ` Jan Beulich
2023-07-14 21:25             ` Fangrui Song
     [not found]             ` <MN0PR12MB57613B59178FAADE5FCD3837CB34A@MN0PR12MB5761.namprd12.prod.outlook.com>
2023-07-14 22:08               ` Stefan O'Rear
2023-07-17  6:50                 ` Jan Beulich
2023-07-21 22:16                   ` Song Fangrui
2023-07-22 15:14                     ` Jeff Law
2023-07-22 16:55                       ` Andrew Waterman
     [not found]                   ` <DS7PR12MB57658EF28577B41BF35C5E7CCB3FA@DS7PR12MB5765.namprd12.prod.outlook.com>
2023-07-24  7:23                     ` Jan Beulich
2023-08-30  3:14                       ` Fangrui Song
2022-09-13 13:03 ` [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags Jan Beulich
2022-09-15  2:43   ` Nelson Chu
2022-09-13 13:04 ` [PATCH 3/3] RISC-V: add alias for SLLI.UW Jan Beulich
2022-09-13 14:54 ` [PATCH 0/3] RISC-V: alias insn adjustments Tsukasa OI
2022-09-13 16:11   ` Jan Beulich
2022-09-13 16:58     ` Tsukasa OI
2022-09-14  6:26       ` Jan Beulich
2022-09-30  9:41 ` [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats" Jan Beulich
2022-09-30 10:26   ` Christoph Müllner
2022-09-30 22:17     ` Palmer Dabbelt
2022-09-30  9:42 ` [PATCH] RISC-V: fallout from "re-arrange opcode table for consistent alias handling" Jan Beulich
2022-09-30  9:42 ` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics Jan Beulich
2022-09-30 10:13   ` Christoph Müllner
2022-09-30 14:43   ` Nelson Chu

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