From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x2d.google.com (mail-oa1-x2d.google.com [IPv6:2001:4860:4864:20::2d]) by sourceware.org (Postfix) with ESMTPS id 435513850211 for ; Fri, 16 Sep 2022 09:36:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 435513850211 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-127dca21a7dso51274718fac.12 for ; Fri, 16 Sep 2022 02:36:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date; bh=SaBHrI9ydKSipdIcJvJY2LB/D0tD08Wi/nPPKCO6mIg=; b=ywQbmU4XqYA8+Reb6gvHNmAXxDwNPBv8uYAhgWgR2m0aetGE2bqsSzD2bI8TO/sn3w sJtLWDTmlyNBqZCFxUeHUCjNPnCiidN3Z5WDCgxIlfFb3ui8kgwOWEI2cKlKdWgzIsbi N+1nBPJyyhvTMxCtH4drnLym3PKP9sVJQDCVm/W+OOcvTG34UAMRm9dM39Zsn5vTklu5 roBwIL9GEWIRwJAeAIfpAnKul0uyh9mg9c3N7H71UZvBh4/4OVqkvzIgaT+ZhFmAjyAz 4HiznfmELvwiK2MfUOXktDsToUFDDQC6hIAwnZHHFyRgLa6AWLgzOt5lAJlnz0GSOSAn SFqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date; bh=SaBHrI9ydKSipdIcJvJY2LB/D0tD08Wi/nPPKCO6mIg=; b=BqJn1aKq19PqVvmzDTadfLJBs8Nh7i/ppPB1FQDiZzjPeCWUAj2s9Zv3Vv92SfBval nDcxIB++OJpzDAC0F/2d35gpWr9tCfH+jTw7VRdsB3qZY43ck7C9b43vcUNuoYSxp6My aqzdG6YAHUuWo7+l8yB2+dsxs1L7do5SviDYmLiWUAdHMrFHGs8sK+Ug0QO4Ath4J971 xTEeMaIQyIdTioK9iqPramO7Z9A8AS4PJ520zkUeTFXHA2vNP1VZdC6qTFUJsmA2KRC9 09tCaIpYPYmAp+DI9/f5/2TB8naQ8rzcPPYmwjzndtXZk/QyxXfiM0FUz7U44OY5NOXs r+zw== X-Gm-Message-State: ACrzQf0hgv/6WC7GFEqErjT+Rr6vYbQVEwX51y344a7fSFCe/Jo6UZxD Y3L3RoY/8k4HUmce2jCwJ2GHXtWywxJ1bQ75szcGCnrj4HUOnw== X-Google-Smtp-Source: AMsMyM6x+JHybY3cCJpdzKfyt+eVIhCrsZ5tkqRSv5X3nr82aXS0c8tSApieAfypxHIB/EDpgjCb/9/4P9/X5d05x3o= X-Received: by 2002:a05:6870:831f:b0:11c:dfe3:ef6d with SMTP id p31-20020a056870831f00b0011cdfe3ef6dmr2241669oae.107.1663321002711; Fri, 16 Sep 2022 02:36:42 -0700 (PDT) MIME-Version: 1.0 References: <20220906122213.1243129-1-christoph.muellner@vrull.eu> In-Reply-To: <20220906122213.1243129-1-christoph.muellner@vrull.eu> From: Nelson Chu Date: Fri, 16 Sep 2022 17:36:32 +0800 Message-ID: Subject: Re: [PATCH 00/13] Add support for the T-Head vendor extensions To: Christoph Muellner Cc: binutils@sourceware.org, Kito Cheng , Jim Wilson , Philipp Tomsich , Palmer Dabbelt , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Christoph, On Tue, Sep 6, 2022 at 8:22 PM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This series introduces support for the T-Head vendor extensions, > which are implemented e.g. in the XuanTie C906 and XuanTie C910 > processors: > * XTheadBa > * XTheadBb > * XTheadBs > * XTheadCmo > * XTheadCondMov > * XTheadFMemIdx > * XTheadMac > * XTheadMemIdx > * XTheadMemPair > * XTheadSync > > The xthead* extensions are documented here: > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0= .0/xthead-2022-09-05-2.0.0.pdf > > The "th." instruction prefix prevents future conflicts with standard > extensions and has been documentented in a PR for the RISC-V toolchain > conventions: > https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 > > The goal of this patchset is to provide access to these instruction > so that compilers/users can optimize SW accordingly. > > Note, that the T-Head vendor extensions do not contain all > vendor-specific > functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are > included). > Instead the extensions cover coherent functionality, that is exposed to > S and U mode. > > To enable the extensions above, the following two methods are possible: > * add the extension to the arch string (e.g. > * -march=3Drv64gc_xtheadcmo_xtheadsync) > * implicitly select the extensions via CPU selection (e.g. > * -mcpu=3Dthead-c910) > > The patchset attempts to minimize code changes in generic/infrastructure > code. All patches in this series come with tests to avoid future regressi= ons. > > Christoph M=C3=BCllner (13): > RISC-V: Add generic support for vendor extensions > RISC-V: Add T-Head CMO vendor extension > RISC-V: Add T-Head SYNC vendor extension > RISC-V: Add support for arbitrary immediate encoding formats > RISC-V: Add T-Head Bitmanip vendor extension > RISC-V: Add T-Head CondMov vendor extension > RISC-V: Add T-Head MAC vendor extension > RISC-V: Add T-Head FMemIdx vendor extension > RISC-V: Add T-Head MemIdx vendor extension > RISC-V: Add support for literal instruction arguments > RISC-V: Add T-Head MemPair vendor extension There are three minor issues, 1. Probably need to add new extension support in riscv_multi_subset_supports_ext, although it is just used for reporting better error messages. 2. The operand L seems only to be used for t-head for now, so it should be still a vendor operand, named with the X prefix probably better. 3. I remember Lifang mentioned before that we should add these vendor stuff based on the vendor infra in the integration branch, and that's what I asked him to rebase his patches to there before, since the previous policy cannot accept vendor stuff on master branch. But now I think most of us agree to accept t-head extensions on mainline directly, so I figured these things cannot be blocked by the vendor infra and cannot be committed. That doesn't mean we don't need the vendor infra, that means we can support the vendor infra later if me or someone have time to move them back to mainline. Therefore, these patches look good to me for now, thank you very much for spending so much time to implement these. But personally, I think we should get the approval from the T-Head guys at least. Btw, If these implementations are referred to and based on the integration branch, then I think it would be better to keep at least the co-authors there in the commit message here; if these patches are re-write without referring to the implementation from the integration branch, then I need to apologize to them, because I asked them to rewrite their patches over there, and cannot be committed to mainline at that time... > riscv: gas: Add command line option '-mcpu=3D' to specify the CPU > riscv: Add T-Head entries for the -mcpu=3D flag Not sure if it is necessary to add -mcpu in assembler, since the compiler should recognize -mcpu, and will expand it to the correct extensions to assembler. If there are no objections for a period of time, then please go ahead and commit these. Thank you very much Nelson > bfd/elfxx-riscv.c | 39 ++- > gas/config/tc-riscv.c | 127 +++++++ > gas/doc/c-riscv.texi | 70 ++++ > gas/testsuite/gas/riscv/mcpu-fail-unknown.d | 3 + > gas/testsuite/gas/riscv/mcpu-fail-unknown.l | 2 + > gas/testsuite/gas/riscv/mcpu-ok-c906.d | 6 + > gas/testsuite/gas/riscv/mcpu-ok-c910.d | 6 + > gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 + > gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 + > gas/testsuite/gas/riscv/x-thead-ba.d | 13 + > gas/testsuite/gas/riscv/x-thead-ba.s | 6 + > gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 + > gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 + > gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++ > gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++ > gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 + > gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 + > gas/testsuite/gas/riscv/x-thead-bs.d | 14 + > gas/testsuite/gas/riscv/x-thead-bs.s | 6 + > gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++ > gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++ > gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++ > gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++ > gas/testsuite/gas/riscv/x-thead-condmov.d | 11 + > gas/testsuite/gas/riscv/x-thead-condmov.s | 3 + > .../gas/riscv/x-thead-fmemidx-fail.d | 3 + > .../gas/riscv/x-thead-fmemidx-fail.l | 18 + > .../gas/riscv/x-thead-fmemidx-fail.s | 17 + > gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++ > gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 + > gas/testsuite/gas/riscv/x-thead-mac.d | 15 + > gas/testsuite/gas/riscv/x-thead-mac.s | 7 + > gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 + > gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 + > gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++ > gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++ > .../gas/riscv/x-thead-mempair-fail.d | 3 + > .../gas/riscv/x-thead-mempair-fail.l | 30 ++ > .../gas/riscv/x-thead-mempair-fail.s | 30 ++ > gas/testsuite/gas/riscv/x-thead-mempair.d | 14 + > gas/testsuite/gas/riscv/x-thead-mempair.s | 6 + > gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 + > gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 + > gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 + > gas/testsuite/gas/riscv/x-thead-sync.d | 14 + > gas/testsuite/gas/riscv/x-thead-sync.s | 6 + > include/opcode/riscv-opc.h | 326 ++++++++++++++++++ > include/opcode/riscv.h | 27 ++ > opcodes/riscv-dis.c | 44 +++ > opcodes/riscv-opc.c | 155 +++++++++ > 55 files changed, 1394 insertions(+), 2 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.d > create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.l > create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c906.d > create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c910.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s > > -- > 2.37.2 >