From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x231.google.com (mail-oi1-x231.google.com [IPv6:2607:f8b0:4864:20::231]) by sourceware.org (Postfix) with ESMTPS id 1908C3858D28 for ; Tue, 29 Nov 2022 02:42:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1908C3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oi1-x231.google.com with SMTP id v82so13789881oib.4 for ; Mon, 28 Nov 2022 18:42:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=jh6DqVN5VilkJGUmy19isgGof9MFWU5cTIzMD25SMKI=; b=5lb1BjGMDieVO/XKGjuo9m6gi6YDLWTfLP/SpJ1zwDxCEx8kF7tog4Yo5exEdssDWr NPembaH/bmKJlMhUpG6wujcyaVLdDKtYuXdqk7wc7u0MJdmZoFbIb7bDgpa6TA9WcjAD qFcPX2Pij9rkn7tkuGdU1Mpe5u1ryIdkSnbQEx0BqyHWD+qoX64UZzI3KA11KNZ+A0+P ZQciVQuaFki0OrrYKVI3y1HzoNR3BOi7vfUYeSE7RVQO1AQCcK8b2XUKjJ5RVorhqaAp THw9upRGyANoFs03cO8nToNKzcOm5QmPDTKvoy2wfUCuqJ4E6PttWcpru8NbcNcW+xoM M/Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jh6DqVN5VilkJGUmy19isgGof9MFWU5cTIzMD25SMKI=; b=tslZAc50EeqnBeDd4A94+t4JhQZjCA+XUFcFoglKaQwb+CcIcTTlJ6jfPPyZM2Tpsn DUwl42NqCD15Vz4wf27KqQihP0tkmPhdxi8dmt4YZA4NMlS212wo0COPjZ1j5CaRW2JL alZeWRNKtinM/9j/wPSu7V8Z3EJkqywp3LUFwrKRcbcBP0h1NCFGcrombDrDJynG1cxw b0moyJ/ELOO4owJSMjp0Hf4wi7xn7Vta/cy7uL+YNTBBBYc2j+5MTcCLbQrfaLf4PVfb BXxr3pyO+FkY3qIZMY7vKpVxZxSQKZXBbQ3QnNuC/HbjdHD1w4jVv22LOkkncs/SiWUW YY2w== X-Gm-Message-State: ANoB5plfU7pXukKuziwbIaEmqJFQFg81QaJ74jk1d8htCzKaFsavAEet 9zKn3BoKN1qtsiUe7Ds3gHIS/gJZBbKSIcUgkBghbQ== X-Google-Smtp-Source: AA0mqf5wAo6UdyC8U3JtW3/DdHDAmnQbZx4sThLi55tPU3zSGo7Y4PUHYsRCzF+JbXJG20Gp6ofBTfHkihoEfiZXwI0= X-Received: by 2002:a05:6808:14c1:b0:351:4e41:819e with SMTP id f1-20020a05680814c100b003514e41819emr16651603oiw.82.1669689744404; Mon, 28 Nov 2022 18:42:24 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Tue, 29 Nov 2022 10:42:13 +0800 Message-ID: Subject: Re: [PATCH 1/3] RISC-V: Allocate "various" operand type To: Tsukasa OI Cc: Kito Cheng , Palmer Dabbelt , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 28, 2022 at 2:39 PM Tsukasa OI wrote: > > From: Tsukasa OI > > This commit intends to move operands that require very special handling or > operand types that are so minor (e.g. only useful on a few instructions) > under "W". I also intend this "W" to be "temporary" operand storage until > we can find good two character (or less) operand type. > > In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved > to "Wif" because of its special handling (and allocating single character > "f" for this operand type seemed too much). > > Current expected allocation guideline is as follows: > > 1. 'W' > 2. The most closely related single-letter extension in lowercase > (strongly recommended but not mandatory) > 3. Identify operand type > > The author currently plans to allocate following three-character operand > types (for operands including instructions from unratified extensions). > > 1. "Wif" ('Zicbop': fetch offset) Maybe just "if" without the W? W seems redundant. If the offset is immediate then using "i + " seems more clear to understand. > 2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions) We probably also need to modify other old operand names to comply with the new naming rules. But for now the current operand names seem enough, maybe we can find better naming rules in the future, it's not urgent. > 3. "Wfm" / "WfM" > 'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling > solely for widening conversion instructions. I still think these similar checks, including the rounding mode checks, should be checked in different match_opcode functions, that should be enough. There is no way to make assembly wrong until you are using the .insn directives, and we don't need to check if the operands are valid or not for them, since .insn is used to allow users to write an unsupported instruction. Please don't continue trying to add various operand names to support these, it is really hard to maintain. I should have already said that, so this is the last time I mention it. Nelson > gas/ChangeLog: > > * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from > "f" to "Wif". > > opcodes/ChangeLog: > > * riscv-dis.c (print_insn_args): Move from "f" to "Wif". > * riscv-opc.c (riscv_opcodes): Reflect new operand type. > --- > gas/config/tc-riscv.c | 64 +++++++++++++++++++++++++++++++------------ > opcodes/riscv-dis.c | 26 ++++++++++++++---- > opcodes/riscv-opc.c | 6 ++-- > 3 files changed, 71 insertions(+), 25 deletions(-) > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 0682eb355241..bb0e18ac8d52 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -1359,7 +1359,6 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) > case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; > case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; > case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; > - case 'f': /* Fall through. */ > case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; > case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; > case 'z': break; /* Zero immediate. */ > @@ -1386,6 +1385,21 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) > goto unknown_validate_operand; > } > break; > + case 'W': /* Various operands. */ > + switch (*++oparg) > + { > + case 'i': > + switch (*++oparg) > + { > + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break; > + default: > + goto unknown_validate_operand; > + } > + break; > + default: > + goto unknown_validate_operand; > + } > + break; > case 'X': /* Integer immediate. */ > { > size_t n; > @@ -3401,22 +3415,37 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, > imm_expr->X_op = O_absent; > continue; > > - case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */ > - if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) > - continue; > - my_getExpression (imm_expr, asarg); > - check_absolute_expr (ip, imm_expr, false); > - if (((unsigned) (imm_expr->X_add_number) & 0x1fU) > - || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2 > - || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2) > - as_bad (_("improper prefetch offset (%ld)"), > - (long) imm_expr->X_add_number); > - ip->insn_opcode |= > - ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) & > - ~ 0x1fU); > - imm_expr->X_op = O_absent; > - asarg = expr_end; > - continue; > + case 'W': /* Various operands. */ > + switch (*++oparg) > + { > + case 'i': > + switch (*++oparg) > + { > + case 'f': > + /* Prefetch offset for 'Zicbop' extension. > + pseudo S-type but lower 5-bits zero. */ > + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) > + continue; > + my_getExpression (imm_expr, asarg); > + check_absolute_expr (ip, imm_expr, false); > + if (((unsigned) (imm_expr->X_add_number) & 0x1fU) > + || imm_expr->X_add_number >= RISCV_IMM_REACH / 2 > + || imm_expr->X_add_number < -RISCV_IMM_REACH / 2) > + as_bad (_ ("improper prefetch offset (%ld)"), > + (long) imm_expr->X_add_number); > + ip->insn_opcode |= ENCODE_STYPE_IMM ( > + (unsigned) (imm_expr->X_add_number) & ~0x1fU); > + imm_expr->X_op = O_absent; > + asarg = expr_end; > + continue; > + default: > + goto unknown_riscv_ip_operand; > + } > + break; > + default: > + goto unknown_riscv_ip_operand; > + } > + break; > > case 'X': /* Integer immediate. */ > { > @@ -3469,6 +3498,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, > } > } > break; > + > default: > unknown_riscv_ip_operand: > as_fatal (_("internal: unknown argument type `%s'"), > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index 0e1f3b4610aa..1e6716e8e58c 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -473,11 +473,6 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > (int)EXTRACT_STYPE_IMM (l)); > break; > > - case 'f': > - print (info->stream, dis_style_address_offset, "%d", > - (int)EXTRACT_STYPE_IMM (l)); > - break; > - > case 'a': > info->target = EXTRACT_JTYPE_IMM (l) + pc; > (*info->print_address_func) (info->target, info); > @@ -582,6 +577,27 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > print (info->stream, dis_style_immediate, "%d", rs1); > break; > > + case 'W': /* Various operands. */ > + { > + switch (*++oparg) > + { > + case 'i': > + switch (*++oparg) > + { > + case 'f': > + print (info->stream, dis_style_address_offset, "%d", > + (int) EXTRACT_STYPE_IMM (l)); > + break; > + default: > + goto undefined_modifier; > + } > + break; > + default: > + goto undefined_modifier; > + } > + } > + break; > + > case 'X': /* Integer immediate. */ > { > size_t n; > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 0e691544f9bc..653eb60f2a58 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -313,9 +313,9 @@ const struct riscv_opcode riscv_opcodes[] = > /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ > > /* Standard hints. */ > -{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > -{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > -{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > {"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, > > /* Basic RVI instructions and aliases. */ > -- > 2.38.1 >