From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc2d.google.com (mail-oo1-xc2d.google.com [IPv6:2607:f8b0:4864:20::c2d]) by sourceware.org (Postfix) with ESMTPS id 109863858C66 for ; Thu, 7 Sep 2023 04:37:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 109863858C66 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oo1-xc2d.google.com with SMTP id 006d021491bc7-575f45e255dso307287eaf.2 for ; Wed, 06 Sep 2023 21:37:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694061469; x=1694666269; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Fl0PYSV0MP0nToRP1Q+EbX1zzzFRS6AXANWQTMWLK0U=; b=zqlPNmn28+qM6kchZlImZqeaVlcMFmFDSLVDf0Zpp3eR80Bc2YzUOFC/CW5vcCZJ/Y NJ3e55uKhBXAkNdhsyp7kvv8NJuZV4UgoLpqFLH8KKUO4j/+VuXQ+fSaB+bee3QQHXpg 8mX7Q2fsvrBqAOnxs+wgnA1VfVc5ldW7LXT53fKas0bIpM77z2fSCPc0T6k4RDsEptr7 XcXjYP56jYhUZcWyJVhKvdeUGphCAVI7lSFxaLy/ATarigEM9f2jHG1OJ3cBLRSZWpVC M9r4m5Wsl+BprDQmhOQ34QWVU+hsy79Mj6x2QQqy4DFyFXMfDplXYp6xeLng8yURHGVD 7YGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694061469; x=1694666269; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Fl0PYSV0MP0nToRP1Q+EbX1zzzFRS6AXANWQTMWLK0U=; b=VyyqgF977HjwSvg9F88N5/fR4TvqzMOtOAOGUxK+7PxfBCHRxYJnrrfXHkgrEfvCDY s+Y6Ow+8AwGQP9HuEN46Tqe+Rk9NGfPwCdtyAtmwwgZa5aNVe+yi2xTwISxu8/rjtCtT yFfSsOWZqOtjEuLjUVq/62ktTlQF1/r7E8pkRPem4BqQipBy49kG1a3Eaeo59zbfClpn pXzcvcym2szwKvEcMhEh7D3F4AKPVIiV0VzaRkNvLpj/QuLH/StfS0m4memr4rxhnP4F vUMTa3YbibG6vvJmsJ8TSUdvUL2514iuA/yqVfPV9mQL6wocLtHRWs13UpU/foWezbQ2 C2oA== X-Gm-Message-State: AOJu0YzIkcRWEjJJu3efTD7R8xs5s06kYAJOn/oJHwLNILHFkFpzF/Wj 6ArcH7osRswj9s5UT5a9gvBPzNxhDIM5kSVEifJFXVkmvJbw/Wh9QM8= X-Google-Smtp-Source: AGHT+IGSDBK4zVK8aSEulSpAx97WmYGEh4iBsh+U9sRaXoh+Xn3ii9qETKoKI3m/cW0q41WiSGY9duBuflRzmPqxpr0= X-Received: by 2002:a4a:3906:0:b0:573:2ac5:43b4 with SMTP id m6-20020a4a3906000000b005732ac543b4mr15703493ooa.5.1694061469020; Wed, 06 Sep 2023 21:37:49 -0700 (PDT) MIME-Version: 1.0 References: <20230905145300.652455-1-mary.bennett@embecosm.com> <20230905145300.652455-3-mary.bennett@embecosm.com> In-Reply-To: <20230905145300.652455-3-mary.bennett@embecosm.com> From: Nelson Chu Date: Thu, 7 Sep 2023 12:37:37 +0800 Message-ID: Subject: Re: [PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P To: Mary Bennett Cc: binutils@sourceware.org Content-Type: multipart/alternative; boundary="00000000000016ce900604bd6c56" X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SCC_10_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000016ce900604bd6c56 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Okay, except using X to replace x for vendor core-v operands, otherwise looks good. Thanks Nelson On Tue, Sep 5, 2023 at 10:54=E2=80=AFPM Mary Bennett wrote: > Spec: > https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/inst= ruction_set_extensions.html > > Contributors: > Mary Bennett > Nandni Jamnadas > Pietra Ferreira > Charlie Keaney > Jessica Mills > Craig Blackmore > Simon Cook > Jeremy Bennett > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` > instruction class. > (riscv_multi_subset_supports_ext): Likewise. > > gas/ChangeLog: > > * config/tc-riscv.c (validate_riscv_insn): Added the necessary > operands for the extension. > (riscv_ip): Likewise. > * doc/c-riscv.texi: Noted XCValu as an additional ISA extension > for CORE-V. > * testsuite/gas/riscv/cv-alu-boundaries.d: New test. > * testsuite/gas/riscv/cv-alu-boundaries.l: New test. > * testsuite/gas/riscv/cv-alu-boundaries.s: New test. > * testsuite/gas/riscv/cv-alu-fail-march.d: New test. > * testsuite/gas/riscv/cv-alu-fail-march.l: New test. > * testsuite/gas/riscv/cv-alu-fail-march.s: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. > * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. > * testsuite/gas/riscv/cv-alu-insns.d: New test. > * testsuite/gas/riscv/cv-alu-insns.s: New test. > > opcodes/ChangeLog: > > * riscv-dis.c (print_insn_args): Disassemble xcb operand. > * riscv-opc.c: Defined the MASK and added XCValu instructions. > > include/ChangeLog: > > * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros > for XCValu. > * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros > for XCValu. > (enum riscv_insn_class): Added the XCValu instruction class. > --- > bfd/elfxx-riscv.c | 5 + > gas/config/tc-riscv.c | 17 ++- > gas/doc/c-riscv.texi | 5 + > gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 + > gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++ > gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 ++++ > gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 + > gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 +++++ > gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 +++++ > .../gas/riscv/cv-alu-fail-operand-01.d | 3 + > .../gas/riscv/cv-alu-fail-operand-01.l | 32 +++++ > .../gas/riscv/cv-alu-fail-operand-01.s | 33 +++++ > .../gas/riscv/cv-alu-fail-operand-02.d | 3 + > .../gas/riscv/cv-alu-fail-operand-02.l | 32 +++++ > .../gas/riscv/cv-alu-fail-operand-02.s | 33 +++++ > .../gas/riscv/cv-alu-fail-operand-03.d | 3 + > .../gas/riscv/cv-alu-fail-operand-03.l | 25 ++++ > .../gas/riscv/cv-alu-fail-operand-03.s | 26 ++++ > .../gas/riscv/cv-alu-fail-operand-04.d | 3 + > .../gas/riscv/cv-alu-fail-operand-04.l | 3 + > .../gas/riscv/cv-alu-fail-operand-04.s | 4 + > .../gas/riscv/cv-alu-fail-operand-05.d | 3 + > .../gas/riscv/cv-alu-fail-operand-05.l | 9 ++ > .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++ > .../gas/riscv/cv-alu-fail-operand-06.d | 3 + > .../gas/riscv/cv-alu-fail-operand-06.l | 9 ++ > .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++ > .../gas/riscv/cv-alu-fail-operand-07.d | 3 + > .../gas/riscv/cv-alu-fail-operand-07.l | 33 +++++ > .../gas/riscv/cv-alu-fail-operand-07.s | 34 +++++ > gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++++ > gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++++++ > include/opcode/riscv-opc.h | 35 +++++ > include/opcode/riscv.h | 5 + > opcodes/riscv-dis.c | 24 ++-- > opcodes/riscv-opc.c | 35 +++++ > 36 files changed, 767 insertions(+), 11 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index a3c32941866..411f9976ffe 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1349,6 +1349,7 @@ static struct riscv_supported_ext > riscv_supported_vendor_x_ext[] =3D > { > /* CORE-V ISA extension spec: > https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/inst= ruction_set_extensions.html > */ > {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -2543,6 +2544,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t > *rps, > return riscv_subset_supports (rps, "h"); > case INSN_CLASS_XCVMAC: > return riscv_subset_supports (rps, "xcvmac"); > + case INSN_CLASS_XCVALU: > + return riscv_subset_supports (rps, "xcvalu"); > case INSN_CLASS_XTHEADBA: > return riscv_subset_supports (rps, "xtheadba"); > case INSN_CLASS_XTHEADBB: > @@ -2785,6 +2788,8 @@ riscv_multi_subset_supports_ext > (riscv_parse_subset_t *rps, > return _("h"); > case INSN_CLASS_XCVMAC: > return "xcvmac"; > + case INSN_CLASS_XCVALU: > + return "xcvalu"; > case INSN_CLASS_XTHEADBA: > return "xtheadba"; > case INSN_CLASS_XTHEADBB: > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 3100a2e135f..4c201e02b80 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -1477,7 +1477,12 @@ validate_riscv_insn (const struct riscv_opcode > *opc, int length) > case 'c': > switch (*++oparg) > { > + case '2': > + /* ls2[4:0] */ > + used_bits |=3D ENCODE_CV_IS2_UIMM5 (-1U); > + break; > case '3': > + /* ls3[4:0] */ > used_bits |=3D ENCODE_CV_IS3_UIMM5 (-1U); > break; > default: > @@ -3695,6 +3700,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, > expressionS *imm_expr, > case 'c': > switch (*++oparg) > { > + case '2': > + my_getExpression (imm_expr, asarg); > + check_absolute_expr (ip, imm_expr, FALSE); > + asarg =3D expr_parse_end; > + if (imm_expr->X_add_number<0 > + || imm_expr->X_add_number>31) > + break; > + ip->insn_opcode > + |=3D ENCODE_CV_IS2_UIMM5 > (imm_expr->X_add_number); > + continue; > case '3': > my_getExpression (imm_expr, asarg); > check_absolute_expr (ip, imm_expr, FALSE); > @@ -3712,7 +3727,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, > expressionS *imm_expr, > default: > goto unknown_riscv_ip_operand; > } > - break; > + break; > > default: > unknown_riscv_ip_operand: > diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi > index 1dcdeeb7b36..61e744ae633 100644 > --- a/gas/doc/c-riscv.texi > +++ b/gas/doc/c-riscv.texi > @@ -750,6 +750,11 @@ The Xcvmac extension provides instructions for > multiply-accumulate operations. > > It is documented in @url{ > https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/inst= ruction_set_extensions.html > } > > +@item Xcvalu > +The Xcvalu extension provides instructions for general ALU operations. > + > +It is documented in @url{ > https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/inst= ruction_set_extensions.html > } > + > @item XTheadBa > The XTheadBa extension provides instructions for address calculations. > > diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.d > b/gas/testsuite/gas/riscv/cv-alu-boundaries.d > new file mode 100644 > index 00000000000..907b043aebc > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-boundaries.s > +#error_output: cv-alu-boundaries.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.l > b/gas/testsuite/gas/riscv/cv-alu-boundaries.l > new file mode 100644 > index 00000000000..fae4022244c > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.l > @@ -0,0 +1,14 @@ > +.*: Assembler messages: > +.*: Error: illegal operands `cv.subnr 10,t3,t6' > +.*: Error: illegal operands `cv.addrnr t4,26,t6' > +.*: Error: illegal operands `cv.subunr t6,t3,15' > +.*: Error: instruction cv.clipu requires absolute expression > +.*: Error: instruction cv.addn requires absolute expression > +.*: Error: illegal operands `cv.clipu t0,t3,-10' > +.*: Error: illegal operands `cv.clipu t0,t3,500' > +.*: Error: illegal operands `cv.addn t0,t3,t6,-60' > +.*: Error: illegal operands `cv.addn t0,t3,t6,302' > +.*: Error: illegal operands `cv.clipu t0,t3,-1' > +.*: Error: illegal operands `cv.clipu t0,t3,32' > +.*: Error: illegal operands `cv.addn t0,t3,t6,-1' > +.*: Error: illegal operands `cv.addn t0,t3,t6,32' > diff --git a/gas/testsuite/gas/riscv/cv-alu-boundaries.s > b/gas/testsuite/gas/riscv/cv-alu-boundaries.s > new file mode 100644 > index 00000000000..bb4da949b4a > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-boundaries.s > @@ -0,0 +1,27 @@ > +# Destination must be of type register > +target: > + cv.subnr 10, t3, t6 > +# Source 1 must be of type register > + cv.addrnr t4, 26, t6 > +# Source 2 must be of type register > + cv.subunr t6, t3, 15 > +# Five bit immediate must be an absolute value > + cv.clipu t0, t3, t6 > +# Five bit immediate must be an absolute value > + cv.addn t0, t3, t6, t2 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.clipu t0, t3, -10 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.clipu t0, t3, 500 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.addn t0, t3, t6, -60 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.addn t0, t3, t6, 302 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.clipu t0, t3, -1 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.clipu t0, t3, 32 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.addn t0, t3, t6, -1 > +# Five bit immediate must be an absolute value in range [0, 31] > + cv.addn t0, t3, t6, 32 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.d > b/gas/testsuite/gas/riscv/cv-alu-fail-march.d > new file mode 100644 > index 00000000000..963aa4012da > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i > +#source: cv-alu-fail-march.s > +#error_output: cv-alu-fail-march.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.l > b/gas/testsuite/gas/riscv/cv-alu-fail-march.l > new file mode 100644 > index 00000000000..11e5a7cd279 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.l > @@ -0,0 +1,32 @@ > +.*: Assembler messages: > +.*: Error: unrecognized opcode `cv.abs t4,t2', extension `xcvalu' requir= ed > +.*: Error: unrecognized opcode `cv.slet t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.sletu t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.min t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.minu t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.max t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.maxu t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.exths t4,t2', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.exthz t4,t2', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.extbs t4,t2', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.extbz t4,t2', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.clip t4,t2,5', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.clipu t4,t2,5', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.clipr t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.clipur t4,t2,t6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.addn t4,t2,t0,4', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.addun t4,t2,t0,4', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.addrn t6,t0,t3,9', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.addurn t6,t0,t3,14', extension > `xcvalu' required > +.*: Error: unrecognized opcode `cv.addnr t6,t0,t3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.addunr t6,t0,t3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.addrnr t6,t0,t3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.addurnr t6,t0,t3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.subn t6,t0,t3,6', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.subun t6,t0,t3,24', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.subrn t6,t0,t3,21', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.suburn t6,t0,t3,3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.subnr t6,t0,t3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.subunr t6,t0,t3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.subrnr t6,t0,t3', extension `xcvalu' > required > +.*: Error: unrecognized opcode `cv.suburnr t6,t0,t3', extension `xcvalu' > required > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-march.s > b/gas/testsuite/gas/riscv/cv-alu-fail-march.s > new file mode 100644 > index 00000000000..8dd39b7301f > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-march.s > @@ -0,0 +1,33 @@ > +# Absence of xcv or xcvalu march option disables all CORE-V general ALU > ops extensions > +target: > + cv.abs t4,t2 > + cv.slet t4,t2,t6 > + cv.sletu t4,t2,t6 > + cv.min t4,t2,t6 > + cv.minu t4,t2,t6 > + cv.max t4,t2,t6 > + cv.maxu t4,t2,t6 > + cv.exths t4,t2 > + cv.exthz t4,t2 > + cv.extbs t4,t2 > + cv.extbz t4,t2 > + cv.clip t4,t2,5 > + cv.clipu t4,t2,5 > + cv.clipr t4,t2,t6 > + cv.clipur t4,t2,t6 > + cv.addn t4, t2, t0, 4 > + cv.addun t4, t2, t0, 4 > + cv.addrn t6, t0, t3, 9 > + cv.addurn t6, t0, t3, 14 > + cv.addnr t6, t0, t3 > + cv.addunr t6, t0, t3 > + cv.addrnr t6, t0, t3 > + cv.addurnr t6, t0, t3 > + cv.subn t6, t0, t3, 6 > + cv.subun t6, t0, t3, 24 > + cv.subrn t6, t0, t3, 21 > + cv.suburn t6, t0, t3, 3 > + cv.subnr t6, t0, t3 > + cv.subunr t6, t0, t3 > + cv.subrnr t6, t0, t3 > + cv.suburnr t6, t0, t3 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d > new file mode 100644 > index 00000000000..81b17348c32 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-fail-operand-01.s > +#error_output: cv-alu-fail-operand-01.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l > new file mode 100644 > index 00000000000..f670e4341fa > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l > @@ -0,0 +1,32 @@ > +.*: Assembler messages: > +.*: Error: illegal operands `cv.abs 5,t2' > +.*: Error: illegal operands `cv.slet 10,t2,t6' > +.*: Error: illegal operands `cv.sletu 11,t2,t6' > +.*: Error: illegal operands `cv.min 15,t2,t6' > +.*: Error: illegal operands `cv.minu 16,t2,t6' > +.*: Error: illegal operands `cv.max 8,t2,t6' > +.*: Error: illegal operands `cv.maxu 3,t2,t6' > +.*: Error: illegal operands `cv.exths 2,t2' > +.*: Error: illegal operands `cv.exthz 6,t2' > +.*: Error: illegal operands `cv.extbs 4,t2' > +.*: Error: illegal operands `cv.extbz 7,t2' > +.*: Error: illegal operands `cv.clip 17,t2,5' > +.*: Error: illegal operands `cv.clipu 11,t2,5' > +.*: Error: illegal operands `cv.clipr 16,t2,t6' > +.*: Error: illegal operands `cv.clipur 15,t2,t6' > +.*: Error: illegal operands `cv.addn 9,t2,t0,4' > +.*: Error: illegal operands `cv.addun 30,t2,t0,4' > +.*: Error: illegal operands `cv.addrn 21,t0,t3,9' > +.*: Error: illegal operands `cv.addurn 6,t0,t3,14' > +.*: Error: illegal operands `cv.addnr 2,t0,t3' > +.*: Error: illegal operands `cv.addunr 26,t0,t3' > +.*: Error: illegal operands `cv.addrnr 3,t0,t3' > +.*: Error: illegal operands `cv.addurnr 14,t0,t3' > +.*: Error: illegal operands `cv.subn 15,t0,t3,6' > +.*: Error: illegal operands `cv.subun 9,t0,t3,24' > +.*: Error: illegal operands `cv.subrn 24,t0,t3,21' > +.*: Error: illegal operands `cv.suburn 25,t0,t3,3' > +.*: Error: illegal operands `cv.subnr 3,t0,t3' > +.*: Error: illegal operands `cv.subunr 12,t0,t3' > +.*: Error: illegal operands `cv.subrnr 13,t0,t3' > +.*: Error: illegal operands `cv.suburnr 8,t0,t3' > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s > new file mode 100644 > index 00000000000..7920ebd53ec > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s > @@ -0,0 +1,33 @@ > +# Destination must be of type register > +target: > + cv.abs 5,t2 > + cv.slet 10,t2,t6 > + cv.sletu 11,t2,t6 > + cv.min 15,t2,t6 > + cv.minu 16,t2,t6 > + cv.max 8,t2,t6 > + cv.maxu 3,t2,t6 > + cv.exths 2,t2 > + cv.exthz 6,t2 > + cv.extbs 4,t2 > + cv.extbz 7,t2 > + cv.clip 17,t2,5 > + cv.clipu 11,t2,5 > + cv.clipr 16,t2,t6 > + cv.clipur 15,t2,t6 > + cv.addn 9,t2,t0,4 > + cv.addun 30,t2,t0,4 > + cv.addrn 21,t0,t3,9 > + cv.addurn 6,t0,t3,14 > + cv.addnr 2,t0,t3 > + cv.addunr 26,t0,t3 > + cv.addrnr 3,t0,t3 > + cv.addurnr 14,t0,t3 > + cv.subn 15,t0,t3,6 > + cv.subun 9,t0,t3,24 > + cv.subrn 24,t0,t3,21 > + cv.suburn 25,t0,t3,3 > + cv.subnr 3,t0,t3 > + cv.subunr 12,t0,t3 > + cv.subrnr 13,t0,t3 > + cv.suburnr 8,t0,t3 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d > new file mode 100644 > index 00000000000..46645aaf864 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-fail-operand-02.s > +#error_output: cv-alu-fail-operand-02.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l > new file mode 100644 > index 00000000000..0a888c7251b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l > @@ -0,0 +1,32 @@ > +.*: Assembler messages: > +.*: Error: illegal operands `cv.abs t4,5' > +.*: Error: illegal operands `cv.slet t4,7,t6' > +.*: Error: illegal operands `cv.sletu t4,3,t6' > +.*: Error: illegal operands `cv.min t4,5,t6' > +.*: Error: illegal operands `cv.minu t4,3,t6' > +.*: Error: illegal operands `cv.max t4,4,t6' > +.*: Error: illegal operands `cv.maxu t4,6,t6' > +.*: Error: illegal operands `cv.exths t4,30' > +.*: Error: illegal operands `cv.exthz t4,23' > +.*: Error: illegal operands `cv.extbs t4,25' > +.*: Error: illegal operands `cv.extbz t4,21' > +.*: Error: illegal operands `cv.clip t4,2,5' > +.*: Error: illegal operands `cv.clipu t4,16,5' > +.*: Error: illegal operands `cv.clipr t4,17,t6' > +.*: Error: illegal operands `cv.clipur t4,14,t6' > +.*: Error: illegal operands `cv.addn t4,5,t0,4' > +.*: Error: illegal operands `cv.addun t4,18,t0,4' > +.*: Error: illegal operands `cv.addrn t6,19,t3,9' > +.*: Error: illegal operands `cv.addurn t6,4,t3,14' > +.*: Error: illegal operands `cv.addnr t6,6,t3' > +.*: Error: illegal operands `cv.addunr t6,7,t3' > +.*: Error: illegal operands `cv.addrnr t6,9,t3' > +.*: Error: illegal operands `cv.addurnr t6,5,t3' > +.*: Error: illegal operands `cv.subn t6,11,t3,6' > +.*: Error: illegal operands `cv.subun t6,14,t3,24' > +.*: Error: illegal operands `cv.subrn t6,15,t3,21' > +.*: Error: illegal operands `cv.suburn t6,24,t3,3' > +.*: Error: illegal operands `cv.subnr t6,4,t3' > +.*: Error: illegal operands `cv.subunr t6,8,t3' > +.*: Error: illegal operands `cv.subrnr t6,7,t3' > +.*: Error: illegal operands `cv.suburnr t6,6,t3' > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s > new file mode 100644 > index 00000000000..6083f1f5044 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s > @@ -0,0 +1,33 @@ > +# Source 1 must be of type register > +target: > + cv.abs t4,5 > + cv.slet t4,7,t6 > + cv.sletu t4,3,t6 > + cv.min t4,5,t6 > + cv.minu t4,3,t6 > + cv.max t4,4,t6 > + cv.maxu t4,6,t6 > + cv.exths t4,30 > + cv.exthz t4,23 > + cv.extbs t4,25 > + cv.extbz t4,21 > + cv.clip t4,2,5 > + cv.clipu t4,16,5 > + cv.clipr t4,17,t6 > + cv.clipur t4,14,t6 > + cv.addn t4,5,t0,4 > + cv.addun t4,18,t0,4 > + cv.addrn t6,19,t3,9 > + cv.addurn t6,4,t3,14 > + cv.addnr t6,6,t3 > + cv.addunr t6,7,t3 > + cv.addrnr t6,9,t3 > + cv.addurnr t6,5,t3 > + cv.subn t6,11,t3,6 > + cv.subun t6,14,t3,24 > + cv.subrn t6,15,t3,21 > + cv.suburn t6,24,t3,3 > + cv.subnr t6,4,t3 > + cv.subunr t6,8,t3 > + cv.subrnr t6,7,t3 > + cv.suburnr t6,6,t3 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d > new file mode 100644 > index 00000000000..6f681289d12 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-fail-operand-03.s > +#error_output: cv-alu-fail-operand-03.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l > new file mode 100644 > index 00000000000..c7a11184996 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l > @@ -0,0 +1,25 @@ > +.*: Assembler messages: > +.*: Error: illegal operands `cv.slet t4,t2,3' > +.*: Error: illegal operands `cv.sletu t4,t2,4' > +.*: Error: illegal operands `cv.min t4,t2,13' > +.*: Error: illegal operands `cv.minu t4,t2,7' > +.*: Error: illegal operands `cv.max t4,t2,17' > +.*: Error: illegal operands `cv.maxu t4,t2,30' > +.*: Error: illegal operands `cv.clipr t4,t2,18' > +.*: Error: illegal operands `cv.clipur t4,t2,29' > +.*: Error: illegal operands `cv.addn t4,t2,24,4' > +.*: Error: illegal operands `cv.addun t4,t2,6,4' > +.*: Error: illegal operands `cv.addrn t6,t0,7,9' > +.*: Error: illegal operands `cv.addurn t6,t0,18,14' > +.*: Error: illegal operands `cv.addnr t6,t0,15' > +.*: Error: illegal operands `cv.addunr t6,t0,24' > +.*: Error: illegal operands `cv.addrnr t6,t0,3' > +.*: Error: illegal operands `cv.addurnr t6,t0,2' > +.*: Error: illegal operands `cv.subn t6,t0,1,6' > +.*: Error: illegal operands `cv.subun t6,t0,8,24' > +.*: Error: illegal operands `cv.subrn t6,t0,18,21' > +.*: Error: illegal operands `cv.suburn t6,t0,25,3' > +.*: Error: illegal operands `cv.subnr t6,t0,14' > +.*: Error: illegal operands `cv.subunr t6,t0,7' > +.*: Error: illegal operands `cv.subrnr t6,t0,18' > +.*: Error: illegal operands `cv.suburnr t6,t0,26' > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s > new file mode 100644 > index 00000000000..64ee8703579 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s > @@ -0,0 +1,26 @@ > +# Source 2 must be of type register > +target: > + cv.slet t4,t2,3 > + cv.sletu t4,t2,4 > + cv.min t4,t2,13 > + cv.minu t4,t2,7 > + cv.max t4,t2,17 > + cv.maxu t4,t2,30 > + cv.clipr t4,t2,18 > + cv.clipur t4,t2,29 > + cv.addn t4,t2,24,4 > + cv.addun t4,t2,6,4 > + cv.addrn t6,t0,7,9 > + cv.addurn t6,t0,18,14 > + cv.addnr t6,t0,15 > + cv.addunr t6,t0,24 > + cv.addrnr t6,t0,3 > + cv.addurnr t6,t0,2 > + cv.subn t6,t0,1,6 > + cv.subun t6,t0,8,24 > + cv.subrn t6,t0,18,21 > + cv.suburn t6,t0,25,3 > + cv.subnr t6,t0,14 > + cv.subunr t6,t0,7 > + cv.subrnr t6,t0,18 > + cv.suburnr t6,t0,26 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d > new file mode 100644 > index 00000000000..634d9bfe091 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-fail-operand-04.s > +#error_output: cv-alu-fail-operand-04.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l > new file mode 100644 > index 00000000000..d6fd960f9e0 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l > @@ -0,0 +1,3 @@ > +.*: Assembler messages: > +.*: Error: instruction cv.clip requires absolute expression > +.*: Error: instruction cv.clipu requires absolute expression > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s > new file mode 100644 > index 00000000000..b97d52a77ab > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s > @@ -0,0 +1,4 @@ > +# Five bit immediate must be an absolute value > +target: > + cv.clip t4,t2,t3 > + cv.clipu t4,t2,t3 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d > new file mode 100644 > index 00000000000..1b90d3e5757 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-fail-operand-05.s > +#error_output: cv-alu-fail-operand-05.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l > new file mode 100644 > index 00000000000..05b5289e743 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l > @@ -0,0 +1,9 @@ > +.*: Assembler messages: > +.*: Error: instruction cv.addn requires absolute expression > +.*: Error: instruction cv.addun requires absolute expression > +.*: Error: instruction cv.addrn requires absolute expression > +.*: Error: instruction cv.addurn requires absolute expression > +.*: Error: instruction cv.subn requires absolute expression > +.*: Error: instruction cv.subun requires absolute expression > +.*: Error: instruction cv.subrn requires absolute expression > +.*: Error: instruction cv.suburn requires absolute expression > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s > new file mode 100644 > index 00000000000..1b0ac6f2d59 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s > @@ -0,0 +1,10 @@ > +# Five bit immediate must be an absolute value > +target: > + cv.addn t4,t2,t0,t3 > + cv.addun t4,t2,t0,t3 > + cv.addrn t6,t0,t3,t2 > + cv.addurn t6,t0,t3,t2 > + cv.subn t6,t0,t3,t2 > + cv.subun t6,t0,t3,t2 > + cv.subrn t6,t0,t3,t2 > + cv.suburn t6,t0,t3,t2 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d > new file mode 100644 > index 00000000000..0a49e682c85 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-fail-operand-06.s > +#error_output: cv-alu-fail-operand-06.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l > new file mode 100644 > index 00000000000..d8059cb5e3a > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l > @@ -0,0 +1,9 @@ > +.*: Assembler messages: > +.*: Error: illegal operands `cv.clip t0,t3,-1' > +.*: Error: illegal operands `cv.clipu t0,t3,-1' > +.*: Error: illegal operands `cv.clip t0,t3,-400' > +.*: Error: illegal operands `cv.clipu t0,t3,-985' > +.*: Error: illegal operands `cv.clip t0,t3,32' > +.*: Error: illegal operands `cv.clipu t0,t3,32' > +.*: Error: illegal operands `cv.clip t0,t3,859' > +.*: Error: illegal operands `cv.clipu t0,t3,7283' > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s > new file mode 100644 > index 00000000000..1b810bdda55 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s > @@ -0,0 +1,10 @@ > +# Five bit immediate must be an absolute value in range [0, 31] > +target: > + cv.clip t0,t3,-1 > + cv.clipu t0,t3,-1 > + cv.clip t0,t3,-400 > + cv.clipu t0,t3,-985 > + cv.clip t0,t3,32 > + cv.clipu t0,t3,32 > + cv.clip t0,t3,859 > + cv.clipu t0,t3,7283 > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d > new file mode 100644 > index 00000000000..06d17fede7c > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvalu > +#source: cv-alu-fail-operand-07.s > +#error_output: cv-alu-fail-operand-07.l > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l > new file mode 100644 > index 00000000000..5a34156afc3 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l > @@ -0,0 +1,33 @@ > +.*: Assembler messages: > +.*: Error: illegal operands `cv.addn t4,t2,t0,-1' > +.*: Error: illegal operands `cv.addun t4,t2,t0,-1' > +.*: Error: illegal operands `cv.addrn t6,t0,t3,-1' > +.*: Error: illegal operands `cv.addurn t6,t0,t3,-1' > +.*: Error: illegal operands `cv.subn t6,t0,t3,-1' > +.*: Error: illegal operands `cv.subun t6,t0,t3,-1' > +.*: Error: illegal operands `cv.subrn t6,t0,t3,-1' > +.*: Error: illegal operands `cv.suburn t6,t0,t3,-1' > +.*: Error: illegal operands `cv.addn t4,t2,t0,-34' > +.*: Error: illegal operands `cv.addun t4,t2,t0,-3556' > +.*: Error: illegal operands `cv.addrn t6,t0,t3,-212' > +.*: Error: illegal operands `cv.addurn t6,t0,t3,-6584' > +.*: Error: illegal operands `cv.subn t6,t0,t3,-89' > +.*: Error: illegal operands `cv.subun t6,t0,t3,-9034' > +.*: Error: illegal operands `cv.subrn t6,t0,t3,-234' > +.*: Error: illegal operands `cv.suburn t6,t0,t3,-284' > +.*: Error: illegal operands `cv.addn t4,t2,t0,32' > +.*: Error: illegal operands `cv.addun t4,t2,t0,32' > +.*: Error: illegal operands `cv.addrn t6,t0,t3,32' > +.*: Error: illegal operands `cv.addurn t6,t0,t3,32' > +.*: Error: illegal operands `cv.subn t6,t0,t3,32' > +.*: Error: illegal operands `cv.subun t6,t0,t3,32' > +.*: Error: illegal operands `cv.subrn t6,t0,t3,32' > +.*: Error: illegal operands `cv.suburn t6,t0,t3,32' > +.*: Error: illegal operands `cv.addn t4,t2,t0,320' > +.*: Error: illegal operands `cv.addun t4,t2,t0,34534' > +.*: Error: illegal operands `cv.addrn t6,t0,t3,254' > +.*: Error: illegal operands `cv.addurn t6,t0,t3,398' > +.*: Error: illegal operands `cv.subn t6,t0,t3,89' > +.*: Error: illegal operands `cv.subun t6,t0,t3,3489' > +.*: Error: illegal operands `cv.subrn t6,t0,t3,143' > +.*: Error: illegal operands `cv.suburn t6,t0,t3,234' > diff --git a/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s > b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s > new file mode 100644 > index 00000000000..04788f69ddd > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s > @@ -0,0 +1,34 @@ > +# Five bit immediate must be an absolute value in range [0, 31] > +target: > + cv.addn t4,t2,t0,-1 > + cv.addun t4,t2,t0,-1 > + cv.addrn t6,t0,t3,-1 > + cv.addurn t6,t0,t3,-1 > + cv.subn t6,t0,t3,-1 > + cv.subun t6,t0,t3,-1 > + cv.subrn t6,t0,t3,-1 > + cv.suburn t6,t0,t3,-1 > + cv.addn t4,t2,t0,-34 > + cv.addun t4,t2,t0,-3556 > + cv.addrn t6,t0,t3,-212 > + cv.addurn t6,t0,t3,-6584 > + cv.subn t6,t0,t3,-89 > + cv.subun t6,t0,t3,-9034 > + cv.subrn t6,t0,t3,-234 > + cv.suburn t6,t0,t3,-284 > + cv.addn t4,t2,t0,32 > + cv.addun t4,t2,t0,32 > + cv.addrn t6,t0,t3,32 > + cv.addurn t6,t0,t3,32 > + cv.subn t6,t0,t3,32 > + cv.subun t6,t0,t3,32 > + cv.subrn t6,t0,t3,32 > + cv.suburn t6,t0,t3,32 > + cv.addn t4,t2,t0,320 > + cv.addun t4,t2,t0,34534 > + cv.addrn t6,t0,t3,254 > + cv.addurn t6,t0,t3,398 > + cv.subn t6,t0,t3,89 > + cv.subun t6,t0,t3,3489 > + cv.subrn t6,t0,t3,143 > + cv.suburn t6,t0,t3,234 > diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.d > b/gas/testsuite/gas/riscv/cv-alu-insns.d > new file mode 100644 > index 00000000000..784cf5ca6cb > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-insns.d > @@ -0,0 +1,102 @@ > +#as: -march=3Drv32i_xcvalu > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+0:[ ]+500332ab[ ]+cv.abs[ ]+t0,t1 > +[ ]+4:[ ]+5003beab[ ]+cv.abs[ ]+t4,t2 > +[ ]+8:[ ]+500f3e2b[ ]+cv.abs[ ]+t3,t5 > +[ ]+c:[ ]+81fe32ab[ ]+cv.addnr[ ]+t0,t3,t6 > +[ ]+10:[ ]+81c2bfab[ ]+cv.addnr[ ]+t6,t0,t3 > +[ ]+14:[ ]+805fbe2b[ ]+cv.addnr[ ]+t3,t6,t0 > +[ ]+18:[ ]+007322db[ ]+cv.addn[ ]+t0,t1,t2,0 > +[ ]+1c:[ ]+0853aedb[ ]+cv.addn[ ]+t4,t2,t0,4 > +[ ]+20:[ ]+3e6f2e5b[ ]+cv.addn[ ]+t3,t5,t1,31 > +[ ]+24:[ ]+85fe32ab[ ]+cv.addrnr[ ]+t0,t3,t6 > +[ ]+28:[ ]+85c2bfab[ ]+cv.addrnr[ ]+t6,t0,t3 > +[ ]+2c:[ ]+845fbe2b[ ]+cv.addrnr[ ]+t3,t6,t0 > +[ ]+30:[ ]+81fe22db[ ]+cv.addrn[ ]+t0,t3,t6,0 > +[ ]+34:[ ]+93c2afdb[ ]+cv.addrn[ ]+t6,t0,t3,9 > +[ ]+38:[ ]+be5fae5b[ ]+cv.addrn[ ]+t3,t6,t0,31 > +[ ]+3c:[ ]+83fe32ab[ ]+cv.addunr[ ]+t0,t3,t6 > +[ ]+40:[ ]+83c2bfab[ ]+cv.addunr[ ]+t6,t0,t3 > +[ ]+44:[ ]+825fbe2b[ ]+cv.addunr[ ]+t3,t6,t0 > +[ ]+48:[ ]+407322db[ ]+cv.addun[ ]+t0,t1,t2,0 > +[ ]+4c:[ ]+4853aedb[ ]+cv.addun[ ]+t4,t2,t0,4 > +[ ]+50:[ ]+7e6f2e5b[ ]+cv.addun[ ]+t3,t5,t1,31 > +[ ]+54:[ ]+87fe32ab[ ]+cv.addurnr[ ]+t0,t3,t6 > +[ ]+58:[ ]+87c2bfab[ ]+cv.addurnr[ ]+t6,t0,t3 > +[ ]+5c:[ ]+865fbe2b[ ]+cv.addurnr[ ]+t3,t6,t0 > +[ ]+60:[ ]+c1fe22db[ ]+cv.addurn[ ]+t0,t3,t6,0 > +[ ]+64:[ ]+ddc2afdb[ ]+cv.addurn[ ]+t6,t0,t3,14 > +[ ]+68:[ ]+fe5fae5b[ ]+cv.addurn[ ]+t3,t6,t0,31 > +[ ]+6c:[ ]+747332ab[ ]+cv.clipr[ ]+t0,t1,t2 > +[ ]+70:[ ]+75f3beab[ ]+cv.clipr[ ]+t4,t2,t6 > +[ ]+74:[ ]+746f3e2b[ ]+cv.clipr[ ]+t3,t5,t1 > +[ ]+78:[ ]+700332ab[ ]+cv.clip[ ]+t0,t1,0 > +[ ]+7c:[ ]+7053beab[ ]+cv.clip[ ]+t4,t2,5 > +[ ]+80:[ ]+71ff3e2b[ ]+cv.clip[ ]+t3,t5,31 > +[ ]+84:[ ]+767332ab[ ]+cv.clipur[ ]+t0,t1,t2 > +[ ]+88:[ ]+77f3beab[ ]+cv.clipur[ ]+t4,t2,t6 > +[ ]+8c:[ ]+766f3e2b[ ]+cv.clipur[ ]+t3,t5,t1 > +[ ]+90:[ ]+720332ab[ ]+cv.clipu[ ]+t0,t1,0 > +[ ]+94:[ ]+7253beab[ ]+cv.clipu[ ]+t4,t2,5 > +[ ]+98:[ ]+73ff3e2b[ ]+cv.clipu[ ]+t3,t5,31 > +[ ]+9c:[ ]+640332ab[ ]+cv.extbs[ ]+t0,t1 > +[ ]+a0:[ ]+6403beab[ ]+cv.extbs[ ]+t4,t2 > +[ ]+a4:[ ]+640f3e2b[ ]+cv.extbs[ ]+t3,t5 > +[ ]+a8:[ ]+660332ab[ ]+cv.extbz[ ]+t0,t1 > +[ ]+ac:[ ]+6603beab[ ]+cv.extbz[ ]+t4,t2 > +[ ]+b0:[ ]+660f3e2b[ ]+cv.extbz[ ]+t3,t5 > +[ ]+b4:[ ]+600332ab[ ]+cv.exths[ ]+t0,t1 > +[ ]+b8:[ ]+6003beab[ ]+cv.exths[ ]+t4,t2 > +[ ]+bc:[ ]+600f3e2b[ ]+cv.exths[ ]+t3,t5 > +[ ]+c0:[ ]+620332ab[ ]+cv.exthz[ ]+t0,t1 > +[ ]+c4:[ ]+6203beab[ ]+cv.exthz[ ]+t4,t2 > +[ ]+c8:[ ]+620f3e2b[ ]+cv.exthz[ ]+t3,t5 > +[ ]+cc:[ ]+5a7332ab[ ]+cv.max[ ]+t0,t1,t2 > +[ ]+d0:[ ]+5bf3beab[ ]+cv.max[ ]+t4,t2,t6 > +[ ]+d4:[ ]+5a6f3e2b[ ]+cv.max[ ]+t3,t5,t1 > +[ ]+d8:[ ]+5c7332ab[ ]+cv.maxu[ ]+t0,t1,t2 > +[ ]+dc:[ ]+5df3beab[ ]+cv.maxu[ ]+t4,t2,t6 > +[ ]+e0:[ ]+5c6f3e2b[ ]+cv.maxu[ ]+t3,t5,t1 > +[ ]+e4:[ ]+567332ab[ ]+cv.min[ ]+t0,t1,t2 > +[ ]+e8:[ ]+57f3beab[ ]+cv.min[ ]+t4,t2,t6 > +[ ]+ec:[ ]+566f3e2b[ ]+cv.min[ ]+t3,t5,t1 > +[ ]+f0:[ ]+587332ab[ ]+cv.minu[ ]+t0,t1,t2 > +[ ]+f4:[ ]+59f3beab[ ]+cv.minu[ ]+t4,t2,t6 > +[ ]+f8:[ ]+586f3e2b[ ]+cv.minu[ ]+t3,t5,t1 > +[ ]+fc:[ ]+527332ab[ ]+cv.sle[ ]+t0,t1,t2 > +[ ]+100:[ ]+53f3beab[ ]+cv.sle[ ]+t4,t2,t6 > +[ ]+104:[ ]+526f3e2b[ ]+cv.sle[ ]+t3,t5,t1 > +[ ]+108:[ ]+547332ab[ ]+cv.sleu[ ]+t0,t1,t2 > +[ ]+10c:[ ]+55f3beab[ ]+cv.sleu[ ]+t4,t2,t6 > +[ ]+110:[ ]+546f3e2b[ ]+cv.sleu[ ]+t3,t5,t1 > +[ ]+114:[ ]+89fe32ab[ ]+cv.subnr[ ]+t0,t3,t6 > +[ ]+118:[ ]+89c2bfab[ ]+cv.subnr[ ]+t6,t0,t3 > +[ ]+11c:[ ]+885fbe2b[ ]+cv.subnr[ ]+t3,t6,t0 > +[ ]+120:[ ]+01fe32db[ ]+cv.subn[ ]+t0,t3,t6,0 > +[ ]+124:[ ]+0dc2bfdb[ ]+cv.subn[ ]+t6,t0,t3,6 > +[ ]+128:[ ]+3e5fbe5b[ ]+cv.subn[ ]+t3,t6,t0,31 > +[ ]+12c:[ ]+8dfe32ab[ ]+cv.subrnr[ ]+t0,t3,t6 > +[ ]+130:[ ]+8dc2bfab[ ]+cv.subrnr[ ]+t6,t0,t3 > +[ ]+134:[ ]+8c5fbe2b[ ]+cv.subrnr[ ]+t3,t6,t0 > +[ ]+138:[ ]+81fe32db[ ]+cv.subrn[ ]+t0,t3,t6,0 > +[ ]+13c:[ ]+abc2bfdb[ ]+cv.subrn[ ]+t6,t0,t3,21 > +[ ]+140:[ ]+be5fbe5b[ ]+cv.subrn[ ]+t3,t6,t0,31 > +[ ]+144:[ ]+8bfe32ab[ ]+cv.subunr[ ]+t0,t3,t6 > +[ ]+148:[ ]+8bc2bfab[ ]+cv.subunr[ ]+t6,t0,t3 > +[ ]+14c:[ ]+8a5fbe2b[ ]+cv.subunr[ ]+t3,t6,t0 > +[ ]+150:[ ]+41fe32db[ ]+cv.subun[ ]+t0,t3,t6,0 > +[ ]+154:[ ]+71c2bfdb[ ]+cv.subun[ ]+t6,t0,t3,24 > +[ ]+158:[ ]+7e5fbe5b[ ]+cv.subun[ ]+t3,t6,t0,31 > +[ ]+15c:[ ]+8ffe32ab[ ]+cv.suburnr[ ]+t0,t3,t6 > +[ ]+160:[ ]+8fc2bfab[ ]+cv.suburnr[ ]+t6,t0,t3 > +[ ]+164:[ ]+8e5fbe2b[ ]+cv.suburnr[ ]+t3,t6,t0 > +[ ]+168:[ ]+c1fe32db[ ]+cv.suburn[ ]+t0,t3,t6,0 > +[ ]+16c:[ ]+c7c2bfdb[ ]+cv.suburn[ ]+t6,t0,t3,3 > +[ ]+170:[ ]+fe5fbe5b[ ]+cv.suburn[ ]+t3,t6,t0,31 > diff --git a/gas/testsuite/gas/riscv/cv-alu-insns.s > b/gas/testsuite/gas/riscv/cv-alu-insns.s > new file mode 100644 > index 00000000000..82ea0c3b98d > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-alu-insns.s > @@ -0,0 +1,124 @@ > +target: > + cv.abs t0,t1 > + cv.abs t4,t2 > + cv.abs t3,t5 > + > + cv.addnr t0, t3, t6 > + cv.addnr t6, t0, t3 > + cv.addnr t3, t6, t0 > + > + cv.addn t0, t1, t2, 0 > + cv.addn t4, t2, t0, 4 > + cv.addn t3, t5, t1, 31 > + > + cv.addrnr t0, t3, t6 > + cv.addrnr t6, t0, t3 > + cv.addrnr t3, t6, t0 > + > + cv.addrn t0, t3, t6, 0 > + cv.addrn t6, t0, t3, 9 > + cv.addrn t3, t6, t0, 31 > + > + cv.addunr t0, t3, t6 > + cv.addunr t6, t0, t3 > + cv.addunr t3, t6, t0 > + > + cv.addun t0, t1, t2, 0 > + cv.addun t4, t2, t0, 4 > + cv.addun t3, t5, t1, 31 > + > + cv.addurnr t0, t3, t6 > + cv.addurnr t6, t0, t3 > + cv.addurnr t3, t6, t0 > + > + cv.addurn t0, t3, t6, 0 > + cv.addurn t6, t0, t3, 14 > + cv.addurn t3, t6, t0, 31 > + > + cv.clipr t0,t1,t2 > + cv.clipr t4,t2,t6 > + cv.clipr t3,t5,t1 > + > + cv.clip t0,t1,0 > + cv.clip t4,t2,5 > + cv.clip t3,t5,31 > + > + cv.clipur t0,t1,t2 > + cv.clipur t4,t2,t6 > + cv.clipur t3,t5,t1 > + > + cv.clipu t0,t1,0 > + cv.clipu t4,t2,5 > + cv.clipu t3,t5,31 > + > + cv.extbs t0,t1 > + cv.extbs t4,t2 > + cv.extbs t3,t5 > + > + cv.extbz t0,t1 > + cv.extbz t4,t2 > + cv.extbz t3,t5 > + > + cv.exths t0,t1 > + cv.exths t4,t2 > + cv.exths t3,t5 > + > + cv.exthz t0,t1 > + cv.exthz t4,t2 > + cv.exthz t3,t5 > + > + cv.max t0,t1,t2 > + cv.max t4,t2,t6 > + cv.max t3,t5,t1 > + > + cv.maxu t0,t1,t2 > + cv.maxu t4,t2,t6 > + cv.maxu t3,t5,t1 > + > + cv.min t0,t1,t2 > + cv.min t4,t2,t6 > + cv.min t3,t5,t1 > + > + cv.minu t0,t1,t2 > + cv.minu t4,t2,t6 > + cv.minu t3,t5,t1 > + > + cv.sle t0,t1,t2 > + cv.sle t4,t2,t6 > + cv.sle t3,t5,t1 > + > + cv.sleu t0,t1,t2 > + cv.sleu t4,t2,t6 > + cv.sleu t3,t5,t1 > + > + cv.subnr t0, t3, t6 > + cv.subnr t6, t0, t3 > + cv.subnr t3, t6, t0 > + > + cv.subn t0, t3, t6, 0 > + cv.subn t6, t0, t3, 6 > + cv.subn t3, t6, t0, 31 > + > + cv.subrnr t0, t3, t6 > + cv.subrnr t6, t0, t3 > + cv.subrnr t3, t6, t0 > + > + cv.subrn t0, t3, t6, 0 > + cv.subrn t6, t0, t3, 21 > + cv.subrn t3, t6, t0, 31 > + > + cv.subunr t0, t3, t6 > + cv.subunr t6, t0, t3 > + cv.subunr t3, t6, t0 > + > + cv.subun t0, t3, t6, 0 > + cv.subun t6, t0, t3, 24 > + cv.subun t3, t6, t0, 31 > + > + cv.suburnr t0, t3, t6 > + cv.suburnr t6, t0, t3 > + cv.suburnr t3, t6, t0 > + > + cv.suburn t0, t3, t6, 0 > + cv.suburn t6, t0, t3, 3 > + cv.suburn t3, t6, t0, 31 > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index 199ae63585f..9e0e090a8a7 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2341,6 +2341,41 @@ > #define MATCH_CV_MACURN 0x8000705b > #define MATCH_CV_MACHHURN 0xc000705b > #define MASK_CV_MULMACN 0xc000707f > +/* Vendor-specific (CORE-V) Xcvalu instructions. */ > +#define MATCH_CV_ABS 0x5000302b > +#define MASK_CV_ABS 0xfff0707f > +#define MATCH_CV_SLET 0x5200302b > +#define MASK_CV_SLET 0xfe00707f > +#define MATCH_CV_SLETU 0x5400302b > +#define MATCH_CV_MIN 0x5600302b > +#define MATCH_CV_MINU 0x5800302b > +#define MATCH_CV_MAX 0x5a00302b > +#define MATCH_CV_MAXU 0x5c00302b > +#define MATCH_CV_EXTHS 0x6000302b > +#define MATCH_CV_EXTHZ 0x6200302b > +#define MATCH_CV_EXTBS 0x6400302b > +#define MATCH_CV_EXTBZ 0x6600302b > +#define MATCH_CV_CLIP 0x7000302b > +#define MATCH_CV_CLIPU 0x7200302b > +#define MATCH_CV_CLIPR 0x7400302b > +#define MATCH_CV_CLIPUR 0x7600302b > +#define MATCH_CV_ADDNR 0x8000302b > +#define MATCH_CV_ADDUNR 0x8200302b > +#define MATCH_CV_ADDRNR 0x8400302b > +#define MATCH_CV_ADDURNR 0x8600302b > +#define MATCH_CV_SUBNR 0x8800302b > +#define MATCH_CV_SUBUNR 0x8a00302b > +#define MATCH_CV_SUBRNR 0x8c00302b > +#define MATCH_CV_SUBURNR 0x8e00302b > +#define MATCH_CV_ADDN 0x205b > +#define MASK_CV_ADDN 0xc000707f > +#define MATCH_CV_ADDUN 0x4000205b > +#define MATCH_CV_ADDRN 0x8000205b > +#define MATCH_CV_ADDURN 0xc000205b > +#define MATCH_CV_SUBN 0x305b > +#define MATCH_CV_SUBUN 0x4000305b > +#define MATCH_CV_SUBRN 0x8000305b > +#define MATCH_CV_SUBURN 0xc000305b > /* Vendor-specific (T-Head) XTheadBa instructions. */ > #define MATCH_TH_ADDSL 0x0000100b > #define MASK_TH_ADDSL 0xf800707f > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index 5097d2cf6c1..18236a6150c 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -113,6 +113,8 @@ static inline unsigned int riscv_insn_length (insn_t > insn) > #define EXTRACT_ZCB_HALFWORD_UIMM(x) \ > (RV_X(x, 5, 1) << 1) > /* Vendor-specific (CORE-V) extract macros. */ > +#define EXTRACT_CV_IS2_UIMM5(x) \ > + (RV_X(x, 20, 5)) > #define EXTRACT_CV_IS3_UIMM5(x) \ > (RV_X(x, 25, 5)) > > @@ -167,6 +169,8 @@ static inline unsigned int riscv_insn_length (insn_t > insn) > #define ENCODE_ZCB_HALFWORD_UIMM(x) \ > (RV_X(x, 1, 1) << 5) > /* Vendor-specific (CORE-V) encode macros. */ > +#define ENCODE_CV_IS2_UIMM5(x) \ > + (RV_X(x, 0, 5) << 20) > #define ENCODE_CV_IS3_UIMM5(x) \ > (RV_X(x, 0, 5) << 25) > > @@ -450,6 +454,7 @@ enum riscv_insn_class > INSN_CLASS_ZICBOZ, > INSN_CLASS_H, > INSN_CLASS_XCVMAC, > + INSN_CLASS_XCVALU, > INSN_CLASS_XTHEADBA, > INSN_CLASS_XTHEADBB, > INSN_CLASS_XTHEADBS, > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index b16db5113b1..d10a1e393e7 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -432,16 +432,20 @@ print_insn_args (const char *oparg, insn_t l, > bfd_vma pc, disassemble_info *info > case 'x': /* Vendor-specific operands. */ > switch (*++oparg) > { > - /* Vendor-specific (CORE-V) operands. */ > - case 'c': > - switch (*++oparg) > - { > - case '3': > - print (info->stream, dis_style_immediate, "%d", > - ((int) EXTRACT_CV_IS3_UIMM5 (l))); > - break; > - } > - break; > + /* Vendor-specific (CORE-V) operands. */ > + case 'c': > + switch (*++oparg) > + { > + case '2': > + print (info->stream, dis_style_immediate, "%d", > + ((int) EXTRACT_CV_IS2_UIMM5 (l))); > + break; > + case '3': > + print (info->stream, dis_style_immediate, "%d", > + ((int) EXTRACT_CV_IS3_UIMM5 (l))); > + break; > + } > + break; > } > break; > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 1b2023b96bd..0b4b4b7dd4d 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -2065,6 +2065,41 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"cv.macurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACURN, > MASK_CV_MULMACN, match_opcode, 0}, > {"cv.machhurn", 0, INSN_CLASS_XCVMAC, "d,s,t,xc3", MATCH_CV_MACHHURN, > MASK_CV_MULMACN, match_opcode, 0}, > > +/* Vendor-specific (CORE-V) Xcvalu instructions. */ > +{"cv.abs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_ABS, > MASK_CV_ABS, match_opcode, 0}, > +{"cv.exths", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHS, > MASK_CV_ABS, match_opcode, 0}, > +{"cv.exthz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHZ, > MASK_CV_ABS, match_opcode, 0}, > +{"cv.extbs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBS, > MASK_CV_ABS, match_opcode, 0}, > +{"cv.extbz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBZ, > MASK_CV_ABS, match_opcode, 0}, > +{"cv.sle", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.slet", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, > MASK_CV_SLET, match_opcode, INSN_ALIAS}, > +{"cv.sleu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.sletu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, > MASK_CV_SLET, match_opcode, INSN_ALIAS}, > +{"cv.min", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MIN, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.minu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MINU, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.max", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAX, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.maxu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAXU, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.clip", 0, INSN_CLASS_XCVALU, "d,s,xc2", MATCH_CV_CLIP, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.clipu", 0, INSN_CLASS_XCVALU, "d,s,xc2", MATCH_CV_CLIPU, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.clipr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.clipur", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPUR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.addn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.addun", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDUN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.addunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDUNR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.addrn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDRN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.addurn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_ADDURN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.addnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDNR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.addrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDRNR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.addurnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDURNR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.subn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.subun", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBUN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.subrn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBRN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.suburn", 0, INSN_CLASS_XCVALU, "d,s,t,xc3", MATCH_CV_SUBURN, > MASK_CV_ADDN, match_opcode, 0}, > +{"cv.subnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBNR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.subunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBUNR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, > MASK_CV_SLET, match_opcode, 0}, > +{"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, > MASK_CV_SLET, match_opcode, 0}, > + > /* Vendor-specific (T-Head) XTheadBa instructions. */ > {"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", > MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0}, > > -- > 2.34.1 > > --00000000000016ce900604bd6c56--