From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) by sourceware.org (Postfix) with ESMTPS id ED8F63858D28 for ; Tue, 20 Sep 2022 08:27:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org ED8F63858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1278624b7c4so3166807fac.5 for ; Tue, 20 Sep 2022 01:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=Zv0sOpTLBSezYySHTlrytq9ESJYmELi+OPzM3xrTGjk=; b=q5E+etxlj7aVCqoNiw++eUR4ZvQ5NyG9LGDAQ4TzBfwQN/sW/xWHf6Op0/lAI9Y8GN k8bFufrYq53LU/aHFkkcVQac4ty7uU5xtULjvWdlls99ve7mTwK3dvA4P7XPXWMpsX23 EX7JsE0tgp5CZvbZbTrxmjjs1zqVKJzG2EXLkcDmL3uPa8UaVLv2RaXP8I8AsURYnCID iZsJ2h2arVAGeyn/Zn7vZTZFchgoVdcAS0ugLsF9u1TQeyoy9QUCAReeDz74n4ttSvmb soaLNxFv/xGvUqGg6edcNmP87UjZlIffNrbCTA50c9+jANXwUHPqy7qy1LtBIS1BhEEl Scjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=Zv0sOpTLBSezYySHTlrytq9ESJYmELi+OPzM3xrTGjk=; b=QdhB4z1ZsVy3WzD1rgHGhqblqqrFdtZH+AcQceXEWpAfYJXl5CjhcMIG14RMxsjwrv oX/KC4wOMtO+vhVQzLbNJ5z7zLXHBw0QheT0Kv9mF3cDdfiuF1VVyHAhBGRWQ4mP6eik SdwsLfkT0FCxmf9+b1HNkF2koUzfLu0Ktb3eYDJUyF6ZHN0Odvm0jYwY/QbR1UBJG9Zu zBYh+LR2qef6wa17V3yehpNnKU7tcYw0ddjlMq2dsyC14rS7WKorqwG7gOich2tRtOWo Obu9q0PRHS3hUqSFR25QcUr39nagkQ7+HFafgweG56zvWjejZssOuhYf7iZY/pq1vU3y 6h2A== X-Gm-Message-State: ACrzQf3+2gixFfsEtBOgt/O8rRY1OUt9AzRfi6ap29dVi0zSGtCPWyic 2krhDC6QCFQU8dOWN51dgwRGy0YuuSQuTZd5tHwfww== X-Google-Smtp-Source: AMsMyM7AyOCAZhbIf4Nk1FDV7p/tdaZ22dlJOxIuaGnyxHAzw0e6LhhQnWAqO0NrZTfBJYyTFf5y+a5jWiaFQal+3xE= X-Received: by 2002:a05:6870:831f:b0:11c:dfe3:ef6d with SMTP id p31-20020a056870831f00b0011cdfe3ef6dmr1313301oae.107.1663662471295; Tue, 20 Sep 2022 01:27:51 -0700 (PDT) MIME-Version: 1.0 References: <20220920021855.2279-1-shihua@iscas.ac.cn> In-Reply-To: <20220920021855.2279-1-shihua@iscas.ac.cn> From: Nelson Chu Date: Tue, 20 Sep 2022 16:27:40 +0800 Message-ID: Subject: Re: [PATCH V3]RISC-V: Implement Ztso extension To: shihua@iscas.ac.cn Cc: binutils@sourceware.org, kito.cheng@sifive.com, vineetg@rivosinc.com, research_trasio@irq.a4lg.com, christoph.muellner@vrull.eu, palmer@dabbelt.com, jiawei@iscas.ac.cn Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Sep 20, 2022 at 10:19 AM wrote: > > From: Shihua > > This patch support ZTSO extension. It will turn on the tso flag for elf_flags once we have enabled Ztso extension. > This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. > > V3: > According to Tsukasa OI's feedback ( https://sourceware.org/pipermail/binutils/2022-September/122915.html ), > * remove CLASS_INSN_ZTSO because it is not used. > * remove testsuite attribute-015.d, because it is not necessary. > * add testsuite ztso.d, to verify whether the flag TSO is generated. > > > bfd\ChangeLog: > > * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag. > * elfxx-riscv.c: Add Ztso's arch > > binutils\ChangeLog: > > * readelf.c (get_machine_flags):Set TSO flag. > > gas\ChangeLog: > > * config/tc-riscv.c (struct riscv_set_options):Set TSO flag. > (riscv_set_tso):Set TSO flag. > (riscv_set_arch):Set TSO flag. > * testsuite/gas/riscv/ztso.d: New test. > > include\ChangeLog: > > * elf/riscv.h (EF_RISCV_TSO) Set TSO flag. > > --- > bfd/elfnn-riscv.c | 3 +++ > bfd/elfxx-riscv.c | 1 + > binutils/readelf.c | 3 +++ > gas/config/tc-riscv.c | 18 ++++++++++++++++++ > gas/testsuite/gas/riscv/ztso.d | 8 ++++++++ > include/elf/riscv.h | 3 +++ > 6 files changed, 36 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/ztso.d > > diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c > index 0e0a0b09e24..3d2ddf4e651 100644 > --- a/bfd/elfnn-riscv.c > +++ b/bfd/elfnn-riscv.c > @@ -3872,6 +3872,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) > /* Allow linking RVC and non-RVC, and keep the RVC flag. */ > elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC; > > + /* Allow linking TSO and non-TSO, and keep the TSO flag. */ > + elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_TSO; > + > return true; > > fail: > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index e03b312a381..3de8865a228 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1204,6 +1204,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ztso", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, > {NULL, 0, 0, 0, 0} > }; > > diff --git a/binutils/readelf.c b/binutils/readelf.c > index cafba9a4f56..b1dbcad06f5 100644 > --- a/binutils/readelf.c > +++ b/binutils/readelf.c > @@ -4079,6 +4079,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) > if (e_flags & EF_RISCV_RVE) > strcat (buf, ", RVE"); > > + if (e_flags & EF_RISCV_TSO) > + strcat (buf, ", TSO"); > + > switch (e_flags & EF_RISCV_FLOAT_ABI) > { > case EF_RISCV_FLOAT_ABI_SOFT: > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 2f5ee18e451..c025890ea74 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -234,6 +234,7 @@ struct riscv_set_options > int relax; /* Emit relocs the linker is allowed to relax. */ > int arch_attr; /* Emit architecture and privileged elf attributes. */ > int csr_check; /* Enable the CSR checking. */ > + int tso; /* Use tso model. */ > }; > > static struct riscv_set_options riscv_opts = > @@ -243,6 +244,7 @@ static struct riscv_set_options riscv_opts = > 1, /* relax */ > DEFAULT_RISCV_ATTR, /* arch_attr */ > 0, /* csr_check */ > + 0, /* tso */ > }; Should we need to support tso for the .option directive? Otherwise, LGTM. Thanks Nelson > /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag > @@ -257,6 +259,18 @@ riscv_set_rvc (bool rvc_value) > riscv_opts.rvc = rvc_value; > } > > +/* Enable or disable the tso flags for riscv_opts. Turn on the tso flag > + for elf_flags once we have enabled ztso extension. */ > + > +static void > +riscv_set_tso (bool tso_value) > +{ > + if (tso_value) > + elf_flags |= EF_RISCV_TSO; > + > + riscv_opts.tso = tso_value; Likewise. > +} > + > /* This linked list records all enabled extensions, which are parsed from > the architecture string. The architecture string can be set by the > -march option, the elf architecture attributes, and the --with-arch > @@ -307,6 +321,10 @@ riscv_set_arch (const char *s) > riscv_set_rvc (false); > if (riscv_subset_supports (&riscv_rps_as, "c")) > riscv_set_rvc (true); > + > + riscv_set_tso (false); > + if (riscv_subset_supports (&riscv_rps_as, "ztso")) > + riscv_set_tso (true); > } > > /* Indicate -mabi option is explictly set. */ > diff --git a/gas/testsuite/gas/riscv/ztso.d b/gas/testsuite/gas/riscv/ztso.d > new file mode 100644 > index 00000000000..cb038db89d3 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/ztso.d > @@ -0,0 +1,8 @@ > +#as: -march=rv64i_ztso > +#readelf: -h > +#source: empty.s > + > +ELF Header: > +#... > +[ ]+Flags:[ ]+0x10, TSO.* > +#... > \ No newline at end of file > diff --git a/include/elf/riscv.h b/include/elf/riscv.h > index 9b3ea376ff3..d7b5c09d5c3 100644 > --- a/include/elf/riscv.h > +++ b/include/elf/riscv.h > @@ -121,6 +121,9 @@ END_RELOC_NUMBERS (R_RISCV_max) > /* RISC-V specific values for st_other. */ > #define STO_RISCV_VARIANT_CC 0x80 > > +/* File uses the TSO model. */ > +#define EF_RISCV_TSO 0x0010 > + > /* Additional section types. */ > #define SHT_RISCV_ATTRIBUTES 0x70000003 /* Section holds attributes. */ > > -- > 2.37.1.windows.1 >