From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x244.google.com (mail-oi1-x244.google.com [IPv6:2607:f8b0:4864:20::244]) by sourceware.org (Postfix) with ESMTPS id 9DD183852776 for ; Wed, 24 Aug 2022 11:35:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9DD183852776 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oi1-x244.google.com with SMTP id n124so8321112oih.7 for ; Wed, 24 Aug 2022 04:35:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=Fsg1SSIV9AwxaK1jzFzEjV30mKs6+mWepQkD86H7odA=; b=NZWZh614wpqZHS20P22G0sSJyO6YE3jsESVSMQV51YkNO7Vyl9JpEUm5U0669QqJX2 veWFla+Q8mhuNGgLoLrUaGXx7S0NvSMe5hN1akrrB5NWJ9fbTSGjy0ZkOENBTJAq3eyi EjgohNcT5QsBwRoTwVxlyMKJT76kXhQ8HhYn6krGTxhUsFbMWxHXr60nDqThoCJKChId fphxUlQNpFErsVVpKLGDvhXoOSnOloI+7LYxkTkCdRWvsPKenEbwDa1simGi+EUg9DWo nv5f0UdonbIykC0LFXZnVK38+JTEYs7WgiPvsUDjGw0F9ygVEzUnsIaOP6uxmdbDK8NC 9xFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=Fsg1SSIV9AwxaK1jzFzEjV30mKs6+mWepQkD86H7odA=; b=tt3tkvcTGJ80paale4bGlCb2dC0d1yB/Xw8R0DdWZyRtsJHtvQ2X1W6qIB2QfLOcAX ThdqOwx/OIsSa89T5a/EhJHHbaR6e/mpD8yxaw7jRqx/X+Sz1re7F4U8NMoIa1LHvnRY on7Km4MqZEoCJxpUEUGY6zjH8rJvn3EhXyxbXMVbRsQC+2WQv6TOkPo6A7u8AzBC12bp E7skBVQHsPuiRU+MP3Iw1SDDPRPljr0tMCVpkJBnxCwAvl79jNpaAhdiE3ckIXdMyrdr RPgIJQOfFHO2EWW/wQRUpHepvAgZAyhw2sw9YAwDolzqShHPbSlbNuEa6VQQeH/ZHe92 oRCQ== X-Gm-Message-State: ACgBeo1V08K9ThDZd8++9IXQxWZJbTL5ssPAtwS+S6nNzfMEE6ASGLEq TJXWfZJ25IdPdY4TiYWGkXnVd8D9zprwLmMB8ysd7A== X-Google-Smtp-Source: AA6agR7FZ4qm5QxaTJkMLRW+/2QcVNRQOEym4yPFS5vOpLMHo0DmLcC780i2VppzerFIrHxj/CAc56buCYho8XmI/j4= X-Received: by 2002:a05:6808:f89:b0:344:cab1:14e9 with SMTP id o9-20020a0568080f8900b00344cab114e9mr3051609oiw.82.1661340948034; Wed, 24 Aug 2022 04:35:48 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Wed, 24 Aug 2022 19:35:37 +0800 Message-ID: Subject: Re: [PATCH v7 2/5] RISC-V: Fix RV32 disassembler address computation To: Tsukasa OI Cc: "H . Peter Anvin" , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Aug 24, 2022 at 9:28 AM Tsukasa OI via Binutils wrote: > > If either the base register is `zero', `tp' or `gp' and XLEN is 32, an > incorrectly sign-extended address is produced when printing. This commit > fixes this bug (including PR29342) by fitting an address into a 32-bit value > on RV32. > > gas/ChangeLog: > > * testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix. > > opcodes/ChangeLog: > > * riscv-dis.c (maybe_print_address): Clarify the role of the `wide' > argument and rename to `is_addiw'. Fit the address into 32-bit on > RV32. (print_insn_args): Reflect bool type of `is_addiw'. Probably no need to change this. > --- > gas/testsuite/gas/riscv/lla32.d | 2 +- > opcodes/riscv-dis.c | 24 ++++++++++++++---------- > 2 files changed, 15 insertions(+), 11 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d > index 9d875629064..8e9324c1c96 100644 > --- a/gas/testsuite/gas/riscv/lla32.d > +++ b/gas/testsuite/gas/riscv/lla32.d > @@ -14,6 +14,6 @@ Disassembly of section .text: > 10: 00001537 lui a0,0x1 > 14: fff50513 addi a0,a0,-1 # fff > 18: 80000537 lui a0,0x80000 > - 1c: fff50513 addi a0,a0,-1 # 7fffffff > + 1c: fff50513 addi a0,a0,-1 # 7fffffff > 20: 00000513 li a0,0 > 24: fff00513 li a0,-1 > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index c6d80c3ba49..419c4746db9 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val, > > static void > maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, > - int wide) > + bool is_addiw) > { > if (pd->hi_addr[base_reg] != (bfd_vma)-1) > { > @@ -187,9 +187,13 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, > return; > pd->to_print_addr = true; > > - /* Sign-extend a 32-bit value to a 64-bit value. */ > - if (wide) > + /* On ADDIW, Sign-extend a 32-bit value to a 64-bit value. */ > + if (is_addiw) > pd->print_addr = (bfd_vma)(int32_t) pd->print_addr; > + > + /* Fit into a 32-bit value on RV32. */ > + if (xlen == 32) > + pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr; These three lines should resolve PR29342, so it looks good to me. > } > > /* Print insn arguments for 32/64-bit code. */ > @@ -239,10 +243,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > case 'o': > case 'j': > if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0) > - maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0); > + maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), false); > if (info->mach == bfd_mach_riscv64 > && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0) > - maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1); > + maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), true); > print (info->stream, dis_style_immediate, "%d", > (int)EXTRACT_CITYPE_IMM (l)); > break; > @@ -402,7 +406,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > case 'b': > case 's': > if ((l & MASK_JALR) == MATCH_JALR) > - maybe_print_address (pd, rs1, 0, 0); > + maybe_print_address (pd, rs1, 0, false); > print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]); > break; > > @@ -432,21 +436,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > break; > > case 'o': > - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); > + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false); > /* Fall through. */ > case 'j': > if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) > || (l & MASK_JALR) == MATCH_JALR) > - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); > + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false); > if (info->mach == bfd_mach_riscv64 > && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0) > - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1); > + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), true); > print (info->stream, dis_style_immediate, "%d", > (int)EXTRACT_ITYPE_IMM (l)); > break; > > case 'q': > - maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0); > + maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), false); > print (info->stream, dis_style_address_offset, "%d", > (int)EXTRACT_STYPE_IMM (l)); > break; > -- > 2.34.1 >