From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 2518C3858D1E for ; Wed, 8 May 2024 04:37:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2518C3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2518C3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::632 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715143048; cv=none; b=lOd7Dsm5uo6pe+6TGpSByLcni100Q0GhuEe4YqH6l7cLwurAN4iQzZIWLH19RvcDGdxLdl2iVs1jfR7ZaIM1OlWjt2ShPdRSCR9vHRcy9dhhBNeOgdDoacqM6MmK6+8E5g5fUIj0NDEqj59gzPFYMuKXXIXtlp1Fvdx6QyQ6+SY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715143048; c=relaxed/simple; bh=wK5o8tlV4hSZFf1tE7hrvjS6VjeHcJsIzY7Y6aMNtmU=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=oulk/OPW1/gaYtPav4Fq68ULdjKgP/USEN3Sh3xawNuWDquQIFaMcsE+W/dfVjMp6plMv5u0nxqEIpg26X8JEN6V6erVe+pFDHZhwG5+FGJVywmf9lRAZ9hcffaxPCi4JhVkDUntWOcGAAAOkEVmHiCmzGbPo2oY8RnivDqjBsU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a59c5c9c6aeso782170666b.2 for ; Tue, 07 May 2024 21:37:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1715143038; x=1715747838; darn=sourceware.org; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=zKq3QJme2BwQFv8RWkuueZMnOQK7sLuEIVhSvYlo25E=; b=j5Tp/fNRTqGrHMois/KMjGHPWZiO0I9VC7OrOgyAC467LTnWhQozMDCTji5HAE8NUk cs01pv1kcm8V83ED+gvDMtLyA0NltQZauxubgp0Kk1v1c3ICCKpyx5FtmevRs2eR5XmH plFjO2go4WsePVZhXYZxKNdi7z6gxE7bsb18HiKMgJZCmMEFJDdhrPoZ9XRt7LvPRmD3 7J66BK8XXXdVHDM/cgzd8/RWQil2t5b/pYWI6ZNeFPT+8YiHXw2wP3wisFn35GMDhCV6 FNUQOSgNT/Wusjva176UvlXBcpdA3nYNYSJYq9hpjQ/TPfbJwCd7f9KQWoVMVO4HNuiQ CyVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715143038; x=1715747838; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=zKq3QJme2BwQFv8RWkuueZMnOQK7sLuEIVhSvYlo25E=; b=HnItyeKCkOy+q6meYjNbARH4gFAU1GyGJXWt/f21Up0w5BXMZO0zJu2HKc15nkyrS2 fFXcHoUP13Ru7TFqLqT50jBGZC1T80y29wSVLR+DeCOkP4fFuYw2zbPYD7b68JzO8Qf7 zkiV1Dz16rKKl9EbbJrirrPaMMJ+eGSQshe2q/4sRvwypiGtmkeR5WajX1Xte2ij9Che XiJzFz6/A6scWY/mFzZ4w4GUs/+CIIw9+B80s3Ebtc7WkTRDI8f/VClhNPuSbhztoLBG NjH4msCMJewbpXxDuxFxMkRFwFFUIoK4U4Yzcky0r10k3bvZPmzyeoG4ndQKnADWcOVH 2wIg== X-Gm-Message-State: AOJu0Yzjs9Mki5G5RlD5fsIDkWtr/Af0Qk4X6Qh+VgtHUXJ6PH3OMSka a6/UXTm5lshyO6uUWm8LVK3pH3mj09KldefqXAOfG3a1HOdYrdXELbExgHKH+EvG19hRSRdprD8 ea6nt0T+lybr4ybzvlgN/9w1LI8Eal2hVcLnCt5GQBn5Am0SM X-Google-Smtp-Source: AGHT+IHVMXXcGOoZPX4HtxWLNjZXAR+yE0WLFExmVyOkSKBcePBy497VvyszM+EspsHcgbvLyacXygpTJFQg/GP1z0U= X-Received: by 2002:a50:9b4f:0:b0:572:a723:f1f4 with SMTP id 4fb4d7f45d1cf-5731d9b78afmr1085323a12.3.1715143037497; Tue, 07 May 2024 21:37:17 -0700 (PDT) MIME-Version: 1.0 References: <20240205013937.95317-1-nelson@rivosinc.com> In-Reply-To: <20240205013937.95317-1-nelson@rivosinc.com> From: Nelson Chu Date: Wed, 8 May 2024 12:37:06 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Support B, Zaamo and Zalrsc extensions. To: binutils@sourceware.org Content-Type: multipart/alternative; boundary="0000000000007d4dbd0617e9dbf0" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000007d4dbd0617e9dbf0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Committed since these are ratified. Thanks Nelson On Mon, Feb 5, 2024 at 9:39=E2=80=AFAM Nelson Chu wro= te: > * https://github.com/riscv/riscv-b/tags > Added standard B extension back, which implies Zba, Zbb and Zbs extension= s. > > * https://github.com/riscv/riscv-zaamo-zalrsc/tags > Splited standard A extension into two new extensions, Zaamo and Zalrsc. > The A extension implies Zaamo and Zalrsc extensions. > > Not sure if we need to do the similar check as i and zicsr/zifencei. > > Passed riscv[32|64]-[elf/linux] binutils testcases. > > bfd/ > * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules > for A and B extensions. The A implies Zaamo and Zalrsc, the > B implies Zba, Zbb and Zbs. > (riscv_supported_std_ext): Supported B extension with v1.0. > (riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0. > (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): > Updated. > include/ > * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added > INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC. > opcodes/ > * riscv-opc.c (riscv_opcodes): Splited standard A extension into > two > new extensions, Zaamo and Zalrsc. > gas/ > * testsuite/gas/riscv/march-imply-a.d: New testcase. > * testsuite/gas/riscv/march-imply-b.d: New testcase. > * testsuite/gas/riscv/attribute-01.d: Updated. > * testsuite/gas/riscv/attribute-02.d: Updated. > * testsuite/gas/riscv/attribute-03.d: Updated. > * testsuite/gas/riscv/attribute-04.d: Updated. > * testsuite/gas/riscv/attribute-05.d: Updated. > * testsuite/gas/riscv/attribute-10.d: Updated. > * testsuite/gas/riscv/mapping-symbols.d: Updated. > * testsuite/gas/riscv/march-imply-g.d: Updated. > * testsuite/gas/riscv/march-imply-unsupported.d: Updated. > * testsuite/gas/riscv/march-ok-reorder.d: Updated. > ld/ > * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated. > * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated. > * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated. > * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated. > --- > bfd/elfxx-riscv.c | 20 +- > gas/testsuite/gas/riscv/attribute-01.d | 2 +- > gas/testsuite/gas/riscv/attribute-02.d | 2 +- > gas/testsuite/gas/riscv/attribute-03.d | 2 +- > gas/testsuite/gas/riscv/attribute-04.d | 2 +- > gas/testsuite/gas/riscv/attribute-05.d | 2 +- > gas/testsuite/gas/riscv/attribute-10.d | 2 +- > gas/testsuite/gas/riscv/mapping-symbols.d | 2 +- > gas/testsuite/gas/riscv/march-imply-a.d | 6 + > gas/testsuite/gas/riscv/march-imply-b.d | 6 + > gas/testsuite/gas/riscv/march-imply-g.d | 2 +- > .../gas/riscv/march-imply-unsupported.d | 2 +- > gas/testsuite/gas/riscv/march-ok-reorder.d | 2 +- > include/opcode/riscv.h | 3 +- > .../ld-riscv-elf/attr-merge-arch-01.d | 2 +- > .../ld-riscv-elf/attr-merge-arch-02.d | 2 +- > .../ld-riscv-elf/attr-merge-arch-03.d | 2 +- > .../ld-riscv-elf/attr-merge-user-ext-01.d | 2 +- > opcodes/riscv-opc.c | 176 +++++++++--------- > 19 files changed, 132 insertions(+), 107 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/march-imply-a.d > create mode 100644 gas/testsuite/gas/riscv/march-imply-b.d > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 9a121b47121..d608e1a98d2 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1202,6 +1202,11 @@ static struct riscv_implicit_subset > riscv_implicit_subsets[] =3D > {"ssstateen", "zicsr", check_implicit_always}, > {"sstc", "zicsr", check_implicit_always}, > {"svadu", "zicsr", check_implicit_always}, > + {"b", "zba", check_implicit_always}, > + {"b", "zbb", check_implicit_always}, > + {"b", "zbs", check_implicit_always}, > + {"a", "zaamo", check_implicit_always}, > + {"a", "zalrsc", check_implicit_always}, > > {"xsfvcp", "zve32x", check_implicit_always}, > {NULL, NULL, NULL} > @@ -1254,6 +1259,7 @@ static struct riscv_supported_ext > riscv_supported_std_ext[] =3D > {"c", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, > {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, > {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 }, > + {"b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"v", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"h", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {NULL, 0, 0, 0, 0} > @@ -1274,6 +1280,8 @@ static struct riscv_supported_ext > riscv_supported_std_z_ext[] =3D > {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, > {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, > {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -2435,8 +2443,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t > *rps, > return riscv_subset_supports (rps, "m"); > case INSN_CLASS_ZMMUL: > return riscv_subset_supports (rps, "zmmul"); > - case INSN_CLASS_A: > - return riscv_subset_supports (rps, "a"); > + case INSN_CLASS_ZAAMO: > + return riscv_subset_supports (rps, "zaamo"); > + case INSN_CLASS_ZALRSC: > + return riscv_subset_supports (rps, "zalrsc"); > case INSN_CLASS_ZAWRS: > return riscv_subset_supports (rps, "zawrs"); > case INSN_CLASS_F: > @@ -2657,8 +2667,10 @@ riscv_multi_subset_supports_ext > (riscv_parse_subset_t *rps, > return "m"; > case INSN_CLASS_ZMMUL: > return _ ("m' or `zmmul"); > - case INSN_CLASS_A: > - return "a"; > + case INSN_CLASS_ZAAMO: > + return "zaamo"; > + case INSN_CLASS_ZALRSC: > + return "zalrsc"; > case INSN_CLASS_ZAWRS: > return "zawrs"; > case INSN_CLASS_F: > diff --git a/gas/testsuite/gas/riscv/attribute-01.d > b/gas/testsuite/gas/riscv/attribute-01.d > index 612305765ab..5615d590866 100644 > --- a/gas/testsuite/gas/riscv/attribute-01.d > +++ b/gas/testsuite/gas/riscv/attribute-01.d > @@ -3,4 +3,4 @@ > #source: empty.s > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" > + Tag_RISCV_arch: > "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" > diff --git a/gas/testsuite/gas/riscv/attribute-02.d > b/gas/testsuite/gas/riscv/attribute-02.d > index 324fd9f2171..134cc41b825 100644 > --- a/gas/testsuite/gas/riscv/attribute-02.d > +++ b/gas/testsuite/gas/riscv/attribute-02.d > @@ -3,4 +3,4 @@ > #source: empty.s > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0" > + Tag_RISCV_arch: > "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0" > diff --git a/gas/testsuite/gas/riscv/attribute-03.d > b/gas/testsuite/gas/riscv/attribute-03.d > index 6e1c2fbc592..70e07e3b55c 100644 > --- a/gas/testsuite/gas/riscv/attribute-03.d > +++ b/gas/testsuite/gas/riscv/attribute-03.d > @@ -3,4 +3,4 @@ > #source: empty.s > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: > "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0_xfoo3p0" > + Tag_RISCV_arch: > "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0_xfoo3= p0" > diff --git a/gas/testsuite/gas/riscv/attribute-04.d > b/gas/testsuite/gas/riscv/attribute-04.d > index f64494a798d..21575b4a632 100644 > --- a/gas/testsuite/gas/riscv/attribute-04.d > +++ b/gas/testsuite/gas/riscv/attribute-04.d > @@ -3,4 +3,4 @@ > #source: attribute-04.s > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" > + Tag_RISCV_arch: > "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" > diff --git a/gas/testsuite/gas/riscv/attribute-05.d > b/gas/testsuite/gas/riscv/attribute-05.d > index 9507b43976d..4a2d6ca8c9e 100644 > --- a/gas/testsuite/gas/riscv/attribute-05.d > +++ b/gas/testsuite/gas/riscv/attribute-05.d > @@ -4,7 +4,7 @@ > Attribute Section: riscv > File Attributes > Tag_RISCV_stack_align: 16-bytes > - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" > + Tag_RISCV_arch: > "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" > Tag_RISCV_unaligned_access: Unaligned access > Tag_RISCV_priv_spec: 1 > Tag_RISCV_priv_spec_minor: 9 > diff --git a/gas/testsuite/gas/riscv/attribute-10.d > b/gas/testsuite/gas/riscv/attribute-10.d > index f46692275f1..04c322ab1dd 100644 > --- a/gas/testsuite/gas/riscv/attribute-10.d > +++ b/gas/testsuite/gas/riscv/attribute-10.d > @@ -3,4 +3,4 @@ > #source: empty.s > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: > "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0" > + Tag_RISCV_arch: > "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0= _zalrsc1p0" > diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d > b/gas/testsuite/gas/riscv/mapping-symbols.d > index 40df3409736..6af825d8ad3 100644 > --- a/gas/testsuite/gas/riscv/mapping-symbols.d > +++ b/gas/testsuite/gas/riscv/mapping-symbols.d > @@ -37,7 +37,7 @@ SYMBOL TABLE: > 0+04 l .text.last.section 0+00 \$d > 0+00 l d .text.section.padding 0+00 .text.section.padding > 0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0 > -0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0 > +0+04 l .text.section.padding 0+00 > \$xrv32i2p1_a2p1_c2p0_zaamo1p0_zalrsc1p0 > 0+06 l .text.section.padding 0+00 \$d > 0+00 l d .text.relax.align 0+00 .text.relax.align > 0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 > diff --git a/gas/testsuite/gas/riscv/march-imply-a.d > b/gas/testsuite/gas/riscv/march-imply-a.d > new file mode 100644 > index 00000000000..b2cbfcf8376 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/march-imply-a.d > @@ -0,0 +1,6 @@ > +#as: -march=3Drv32ia -march-attr -misa-spec=3D20191213 > +#readelf: -A > +#source: empty.s > +Attribute Section: riscv > +File Attributes > + Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" > diff --git a/gas/testsuite/gas/riscv/march-imply-b.d > b/gas/testsuite/gas/riscv/march-imply-b.d > new file mode 100644 > index 00000000000..82506c9a3e1 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/march-imply-b.d > @@ -0,0 +1,6 @@ > +#as: -march=3Drv32ib -march-attr -misa-spec=3D20191213 > +#readelf: -A > +#source: empty.s > +Attribute Section: riscv > +File Attributes > + Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" > diff --git a/gas/testsuite/gas/riscv/march-imply-g.d > b/gas/testsuite/gas/riscv/march-imply-g.d > index 239b717fd7f..7e7a96785bf 100644 > --- a/gas/testsuite/gas/riscv/march-imply-g.d > +++ b/gas/testsuite/gas/riscv/march-imply-g.d > @@ -3,4 +3,4 @@ > #source: empty.s > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: > "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0" > + Tag_RISCV_arch: > "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalr= sc1p0" > diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d > b/gas/testsuite/gas/riscv/march-imply-unsupported.d > index 612305765ab..5615d590866 100644 > --- a/gas/testsuite/gas/riscv/march-imply-unsupported.d > +++ b/gas/testsuite/gas/riscv/march-imply-unsupported.d > @@ -3,4 +3,4 @@ > #source: empty.s > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" > + Tag_RISCV_arch: > "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" > diff --git a/gas/testsuite/gas/riscv/march-ok-reorder.d > b/gas/testsuite/gas/riscv/march-ok-reorder.d > index 030f8b15018..712c1bdff4d 100644 > --- a/gas/testsuite/gas/riscv/march-ok-reorder.d > +++ b/gas/testsuite/gas/riscv/march-ok-reorder.d > @@ -4,4 +4,4 @@ > > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: > "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zba1p0_x= bar2p0_xfoo2p0" > + Tag_RISCV_arch: > "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0= _zalrsc1p0_zba1p0_xbar2p0_xfoo2p0" > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index adea7dbc794..1a14a5ecba0 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -407,7 +407,6 @@ enum riscv_insn_class > > INSN_CLASS_I, > INSN_CLASS_C, > - INSN_CLASS_A, > INSN_CLASS_M, > INSN_CLASS_F, > INSN_CLASS_D, > @@ -421,6 +420,8 @@ enum riscv_insn_class > INSN_CLASS_ZIHINTNTL_AND_C, > INSN_CLASS_ZIHINTPAUSE, > INSN_CLASS_ZMMUL, > + INSN_CLASS_ZAAMO, > + INSN_CLASS_ZALRSC, > INSN_CLASS_ZAWRS, > INSN_CLASS_F_INX, > INSN_CLASS_D_INX, > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d > b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d > index de87f600387..0fb655c7239 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d > @@ -6,4 +6,4 @@ > > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p1_a2p0" > + Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0" > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d > b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d > index 381ef850d97..10d01b1b7be 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d > @@ -6,4 +6,4 @@ > > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p1_a2p0" > + Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0" > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d > b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d > index 6419fe89791..9649931d937 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d > @@ -6,4 +6,4 @@ > > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p1_a2p0_xbar2p0_xfoo2p0" > + Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0_xbar2p0_xfoo2p0" > diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d > b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d > index f4012dcf90d..d71dd56820e 100644 > --- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d > +++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d > @@ -6,4 +6,4 @@ > > Attribute Section: riscv > File Attributes > - Tag_RISCV_arch: "rv32i2p1_a2p1" > + Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index fdd05ac75dc..c3a0502f810 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -570,94 +570,94 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, > match_opcode, 0 }, > > /* Atomic memory operation instruction subset. */ > -{"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, > MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, > MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, > MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoswap.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W, > MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoand.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W, > MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W, > MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoxor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W, > MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomax.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W, > MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomaxu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W, > MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomin.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W, > MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amominu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W, > MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"lr.w.aq", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQ, > MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"sc.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQ, > MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, > MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amoand.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, > MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, > MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, > MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomax.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, > MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amomin.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, > MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amominu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"lr.w.rl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_RL, > MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"sc.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_RL, > MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, > MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, > MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoand.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, > MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, > MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, > MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomax.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, > MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, > MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amomin.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, > MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amominu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, > MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"lr.w.aqrl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQRL, > MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"sc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQRL, > MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, > MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > -{"amoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"amominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > -{"lr.d", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D, > MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"sc.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D, > MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoadd.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D, > MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoswap.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D, > MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoand.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D, > MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D, > MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoxor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D, > MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomax.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D, > MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomaxu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D, > MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomin.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D, > MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amominu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D, > MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"lr.d.aq", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQ, > MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"sc.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQ, > MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoadd.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, > MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoswap.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amoand.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, > MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, > MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoxor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, > MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomax.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, > MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomaxu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amomin.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, > MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amominu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"lr.d.rl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_RL, > MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"sc.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_RL, > MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoadd.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, > MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoswap.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, > MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoand.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, > MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, > MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoxor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, > MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomax.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, > MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomaxu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, > MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amomin.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, > MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amominu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, > MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"lr.d.aqrl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQRL, > MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"sc.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQRL, > MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoadd.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amoswap.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amoand.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amoor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, > MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > -{"amoxor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amomax.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amomaxu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > -{"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", > MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"lr.w", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W, > MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"sc.w", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W, > MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amoadd.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W, > MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amoswap.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W, > MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amoand.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W, > MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amoor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W, > MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amoxor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W, > MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amomax.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W, > MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amomaxu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W, > MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amomin.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W, > MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amominu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W, > MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"lr.w.aq", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W|MASK_AQ, > MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"sc.w.aq", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W|MASK_AQ, > MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amoadd.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoswap.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoand.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoxor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomax.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomaxu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomin.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amominu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"lr.w.rl", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W|MASK_RL, > MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"sc.w.rl", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W|MASK_RL, > MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, > +{"amoadd.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoswap.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoand.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoxor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomax.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomaxu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomin.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amominu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"lr.w.aqrl", 0, INSN_CLASS_ZALRSC,"d,0(s)", > MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"sc.w.aqrl", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", > MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoadd.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoswap.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoand.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amoxor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomax.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomaxu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amomin.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"amominu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, > INSN_DREF|INSN_4_BYTE }, > +{"lr.d", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D, > MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"sc.d", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D, > MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amoadd.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D, > MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amoswap.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D, > MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amoand.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D, > MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amoor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D, > MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amoxor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D, > MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amomax.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D, > MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amomaxu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D, > MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amomin.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D, > MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amominu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D, > MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"lr.d.aq", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D|MASK_AQ, > MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"sc.d.aq", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D|MASK_AQ, > MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amoadd.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoswap.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoand.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoxor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomax.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomaxu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomin.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amominu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"lr.d.rl", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D|MASK_RL, > MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"sc.d.rl", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D|MASK_RL, > MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > +{"amoadd.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoswap.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoand.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoxor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomax.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomaxu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomin.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amominu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"lr.d.aqrl", 64, INSN_CLASS_ZALRSC,"d,0(s)", > MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"sc.d.aqrl", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", > MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoadd.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoswap.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoand.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amoxor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomax.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomaxu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amomin.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > +{"amominu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", > MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, > INSN_DREF|INSN_8_BYTE }, > > /* Multiply/Divide instruction subset. */ > {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, > MASK_C_MUL, match_opcode, INSN_ALIAS }, > -- > 2.39.3 (Apple Git-145) > > --0000000000007d4dbd0617e9dbf0--