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From: Nelson Chu <nelson@rivosinc.com>
Date: Mon, 28 Nov 2022 09:53:58 +0800
Message-ID: <CAPpQWtCEUeRGKVH56wy==5B6hhfixDd=Nh=S314vRvUXD9dzTg@mail.gmail.com>
Subject: Re: [PATCH v4 0/3] RISC-V: Better support for long instructions (64 <
 x <= 176 [bits])
To: Jan Beulich <jbeulich@suse.com>
Cc: Tsukasa OI <research_trasio@irq.a4lg.com>, binutils@sourceware.org
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On Fri, Nov 25, 2022 at 9:08 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 25.11.2022 12:42, Tsukasa OI wrote:
> > Tsukasa OI (3):
> >   RISC-V: Better support for long instructions (disassembler)
> >   RISC-V: Better support for long instructions (assembler)
> >   RISC-V: Better support for long instructions (tests)
>
> LGTM, but again please wait a day or two with committing in case Nelson
> wants to take another look. And thanks for being patient with me.

Hey Jan, thanks for your reply to clarify the roles of us.  FYI, the
.insn test cases were not so stricter because we haven't had any
dis-assembler improvements at that time, so not sure which the
dis-assembler results are better for those cases where the
instructions are not supported.  Anyway, I have seen the details,
which look good to me, too, so please commit these three patches.

Thanks for both of your support, Jan and Tsukasa
Nelson