From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) by sourceware.org (Postfix) with ESMTPS id 7351B3858D32 for ; Wed, 9 Nov 2022 02:47:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7351B3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-ot1-x32e.google.com with SMTP id l42-20020a9d1b2d000000b0066c6366fbc3so9433514otl.3 for ; Tue, 08 Nov 2022 18:47:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=3PRuL3cT5jd3MPU5YNfb2TVUSaXw3nTZY4Ng1JIv72s=; b=GupCkIsQZZQxHTPhklkrTeaF9lHRry3M6DzchePl0n4gVvvv69XVInfINdACwolrPQ whvlCnvqHmZ7Nuz0VZKJDTzq2T4NfT7YXubAZNNhaDzfirsmazdpwAmWa62jyk+jR13t f+097gsW+avkRwjs0rcrThtrBYuxV702AqwfwMbzSuI/4pIsVInymaQ4WtQWgGNr7//l oWbM9FfMaZr/VXVdLi3b82HgIGv+Edfg5l+g2zYeesZFtbqXpAR7Q6PkcK5hQT0qKw2V m2CPc5bSGcwEGuh4F97dFsfHqjNNesQQ9w5nCraZVM2LYVxt8PK98/TsQA5sBFtp2CkT neCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3PRuL3cT5jd3MPU5YNfb2TVUSaXw3nTZY4Ng1JIv72s=; b=BAyARijccr2EXi0hKPxGZDafA7DuogsnrxpkQK6i7PzjZ4mTZbLkbq5mcuITIxSGg1 BBDqQZSdghk97ajYlYsnA7aqaUAF0pDkyG4r4jp69kZb9cRQ9zAXU2CaP0L6WoGlaBay MmJgrnJ+d5RcVnghsRjj2esi8DxfOaYmYGJqLwpsLp/LyBsLoy+ztF7xz5lae+lJxx6a et3UpIspKZ8QAmVSIUtH3foIjZw6Bg5tPzS0w6KtklBeKnU7/2dC5Hyw3RrjS4La93VP rv8shSzXqnxOwFcUiimuYetxCwEYC8taGhyMQA+02pEhFRFmmt9GYEtC1X1lAJv2m6Wh bHuw== X-Gm-Message-State: ACrzQf18Xhf7KtP0mbBXZTQrz45L+GxyMLmm0Ole3iO+zZreBu+9MPZp XiEbCtp8RuHVJ0zjMa+He9DjaI7yby/6bRQk2CwKCQ== X-Google-Smtp-Source: AMsMyM4+TbSielM1gT3dvmLs2uSRNVlrcBz4EQh2XEGxpwx8pnmROwx+4txtIQ/OkNpmilTjHb/s56ezfc6voRwwNac= X-Received: by 2002:a9d:6847:0:b0:66c:7132:1bb1 with SMTP id c7-20020a9d6847000000b0066c71321bb1mr729244oto.320.1667962072659; Tue, 08 Nov 2022 18:47:52 -0800 (PST) MIME-Version: 1.0 References: <20221107124620.1271470-1-christoph.muellner@vrull.eu> In-Reply-To: <20221107124620.1271470-1-christoph.muellner@vrull.eu> From: Nelson Chu Date: Wed, 9 Nov 2022 10:47:41 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: xtheadfmemidx: Use fp register in mnemonics To: Christoph Muellner Cc: binutils@sourceware.org, Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed with ChangLogs, thanks! Nelson On Mon, Nov 7, 2022 at 8:46 PM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > Although the encoding for scalar and fp registers is identical, > we should follow common pratice and use fp register names > when referencing fp registers. > > The xtheadmemidx extension consists of indirect load/store instructions > which all load to or store from fp registers. > Let's use fp register names in this case and adjust the test cases > accordingly. > > Signed-off-by: Christoph M=C3=BCllner > --- > .../gas/riscv/x-thead-fmemidx-fail.l | 1 + > .../gas/riscv/x-thead-fmemidx-fail.s | 33 ++++++++++--------- > gas/testsuite/gas/riscv/x-thead-fmemidx.d | 32 +++++++++--------- > gas/testsuite/gas/riscv/x-thead-fmemidx.s | 32 +++++++++--------- > opcodes/riscv-opc.c | 16 ++++----- > 5 files changed, 58 insertions(+), 56 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l b/gas/testsui= te/gas/riscv/x-thead-fmemidx-fail.l > index ef28f047b41..33cddac856e 100644 > --- a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l > +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l > @@ -1,4 +1,5 @@ > .*: Assembler messages: > +.*: Error: illegal operands `th.flrd a0,a1,a2,0' > .*: Error: improper immediate value \(18446744073709551615\) > .*: Error: improper immediate value \(4\) > .*: Error: improper immediate value \(18446744073709551615\) > diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s b/gas/testsui= te/gas/riscv/x-thead-fmemidx-fail.s > index e486c6a1423..8c6ee0cda4c 100644 > --- a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s > +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s > @@ -1,17 +1,18 @@ > target: > - th.flrd a0, a1, a2, -1 > - th.flrd a0, a1, a2, 4 > - th.flrw a0, a1, a2, -1 > - th.flrw a0, a1, a2, 4 > - th.flurd a0, a1, a2, -1 > - th.flurd a0, a1, a2, 4 > - th.flurw a0, a1, a2, -1 > - th.flurw a0, a1, a2, 4 > - th.fsrd a0, a1, a2, -1 > - th.fsrd a0, a1, a2, 4 > - th.fsrw a0, a1, a2, -1 > - th.fsrw a0, a1, a2, 4 > - th.fsurd a0, a1, a2, -1 > - th.fsurd a0, a1, a2, 4 > - th.fsurw a0, a1, a2, -1 > - th.fsurw a0, a1, a2, 4 > + th.flrd a0, a1, a2, 0 > + th.flrd fa0, a1, a2, -1 > + th.flrd fa0, a1, a2, 4 > + th.flrw fa0, a1, a2, -1 > + th.flrw fa0, a1, a2, 4 > + th.flurd fa0, a1, a2, -1 > + th.flurd fa0, a1, a2, 4 > + th.flurw fa0, a1, a2, -1 > + th.flurw fa0, a1, a2, 4 > + th.fsrd fa0, a1, a2, -1 > + th.fsrd fa0, a1, a2, 4 > + th.fsrw fa0, a1, a2, -1 > + th.fsrw fa0, a1, a2, 4 > + th.fsurd fa0, a1, a2, -1 > + th.fsurd fa0, a1, a2, 4 > + th.fsurw fa0, a1, a2, -1 > + th.fsurw fa0, a1, a2, 4 > diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.d b/gas/testsuite/ga= s/riscv/x-thead-fmemidx.d > index dfa477c8fc4..e8d53a33951 100644 > --- a/gas/testsuite/gas/riscv/x-thead-fmemidx.d > +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.d > @@ -7,19 +7,19 @@ > Disassembly of section .text: > > 0+000 : > -[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+a0,a1,a2,3 > -[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+a0,a1,a2,3 > -[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+a0,a1,a2,3 > -[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+a0,a1,a2,3 > -[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,3 > -[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,3 > -[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,3 > -[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,0 > -[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+fa0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+fa0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+fa0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+fa0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+fa0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+fa0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+fa0,a1,a2,3 > +[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+fa0,a1,a2,0 > +[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+fa0,a1,a2,3 > diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.s b/gas/testsuite/ga= s/riscv/x-thead-fmemidx.s > index 0d70bb7e799..f26bdc332c8 100644 > --- a/gas/testsuite/gas/riscv/x-thead-fmemidx.s > +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.s > @@ -1,17 +1,17 @@ > target: > - th.flrd a0, a1, a2, 0 > - th.flrd a0, a1, a2, 3 > - th.flrw a0, a1, a2, 0 > - th.flrw a0, a1, a2, 3 > - th.flurd a0, a1, a2, 0 > - th.flurd a0, a1, a2, 3 > - th.flurw a0, a1, a2, 0 > - th.flurw a0, a1, a2, 3 > - th.fsrd a0, a1, a2, 0 > - th.fsrd a0, a1, a2, 3 > - th.fsrw a0, a1, a2, 0 > - th.fsrw a0, a1, a2, 3 > - th.fsurd a0, a1, a2, 0 > - th.fsurd a0, a1, a2, 3 > - th.fsurw a0, a1, a2, 0 > - th.fsurw a0, a1, a2, 3 > + th.flrd fa0, a1, a2, 0 > + th.flrd fa0, a1, a2, 3 > + th.flrw fa0, a1, a2, 0 > + th.flrw fa0, a1, a2, 3 > + th.flurd fa0, a1, a2, 0 > + th.flurd fa0, a1, a2, 3 > + th.flurw fa0, a1, a2, 0 > + th.flurw fa0, a1, a2, 3 > + th.fsrd fa0, a1, a2, 0 > + th.fsrd fa0, a1, a2, 3 > + th.fsrw fa0, a1, a2, 0 > + th.fsrw fa0, a1, a2, 3 > + th.fsurd fa0, a1, a2, 0 > + th.fsurd fa0, a1, a2, 3 > + th.fsurw fa0, a1, a2, 0 > + th.fsurw fa0, a1, a2, 3 > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 4029c1881b8..599486fdf03 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1922,14 +1922,14 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNE= Z, MASK_TH_MVNEZ, match_opcode, 0}, > > /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ > -{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLR= D, MASK_TH_FLRD, match_opcode, 0}, > -{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLR= W, MASK_TH_FLRW, match_opcode, 0}, > -{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLU= RD, MASK_TH_FLURD, match_opcode, 0}, > -{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLU= RW, MASK_TH_FLURW, match_opcode, 0}, > -{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSR= D, MASK_TH_FSRD, match_opcode, 0}, > -{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSR= W, MASK_TH_FSRW, match_opcode, 0}, > -{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSU= RD, MASK_TH_FSURD, match_opcode, 0}, > -{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSU= RW, MASK_TH_FSURW, match_opcode, 0}, > +{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLR= D, MASK_TH_FLRD, match_opcode, 0}, > +{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLR= W, MASK_TH_FLRW, match_opcode, 0}, > +{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLU= RD, MASK_TH_FLURD, match_opcode, 0}, > +{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLU= RW, MASK_TH_FLURW, match_opcode, 0}, > +{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSR= D, MASK_TH_FSRD, match_opcode, 0}, > +{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSR= W, MASK_TH_FSRW, match_opcode, 0}, > +{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSU= RD, MASK_TH_FSURD, match_opcode, 0}, > +{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSU= RW, MASK_TH_FSURW, match_opcode, 0}, > > /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ > {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_T= H_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, > -- > 2.38.1 >