From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x22d.google.com (mail-oi1-x22d.google.com [IPv6:2607:f8b0:4864:20::22d]) by sourceware.org (Postfix) with ESMTPS id 28A343858409 for ; Tue, 29 Aug 2023 07:59:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 28A343858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-3a9ee3c7dbbso26440b6e.1 for ; Tue, 29 Aug 2023 00:59:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1693295963; x=1693900763; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=jmM7wQ/nCsHXdIwmamG+yLaklagk8lWq/W1CMuW+BOs=; b=Hz11czu/UcWfvw6ED+Gzyd8XEoB+vMupKV+wbtQeVH8dN9nb7lg3CP0ghb4wWi7mB6 jkhHXsmM9SVpOEx7F5EGvqy+LqNt1CZ+O+YX/GrkJJzDLDo6C6jCDuc4BWbOIT0IhdWi lmlzA1kr/6molj/oihsgxyLbBeNkWfSz642hvAsdHSu8PVjTEoq6tqPDYaRKEG8UKiyR eFW6eJCwKqvq3AQTb2XMPci9NCIfg875OJUOzPL5npHZvA6SSuN3dvMe9nFeq4+DspE9 Bcf2fr79YKysNZhH35+7MS6bcAJdeFbX8mpzsfF1xem/dKnJyA5cYBVkh+wIs/cyToet SZtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693295963; x=1693900763; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jmM7wQ/nCsHXdIwmamG+yLaklagk8lWq/W1CMuW+BOs=; b=iCPpUY3WbxNUfyvEjHDw1As58A19kfT/FpEbl2dLcVJim6yiCr+NElc6nKqYBJame3 lbc/xVfnsxKIYHB4w/u/6925/uzQKQWyO++o6qeDw2v+Tr8IVyxel9tINR7XlxDXkYsa dQVCJXZK4Sly6X5N3pEZKv1ovLNhuETHX7sHjsGSHFBAi/g6svwtZkza+rDuQRp7IqyN NxDKr3MmXs6bvrCtLGgNteGY/vEM/QUa/EulU6yGMDQziN38ULsqtmOJkRQe0iZnWJ2s kP2NdtVkZfiBC9j4U1Xh23QIFeCD29k0FTeMKDqKeJ9G+MsVa1MQlBsq6E8/uyXTX4Ct qerw== X-Gm-Message-State: AOJu0YyiD2DlOP402FPjscIZc7mo78oFUDO5/NEbs0Y4lJpWBlh6pL4X beprM6jN/D4A8ZkhRab7fTYR+iEI5gHVVqR6KtdYCHGl2RYOOSXTZ7mjmg== X-Google-Smtp-Source: AGHT+IHkISPozLoZQDv6b/YFD2QL/S8z4UsnNEZsJE80v3eWrHJOmY2Wt1EzE3oU7O7jPsFnLdPMXB591UYX2+6tui4= X-Received: by 2002:a05:6808:210e:b0:3a8:c5d6:c582 with SMTP id r14-20020a056808210e00b003a8c5d6c582mr13954288oiw.40.1693295963484; Tue, 29 Aug 2023 00:59:23 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Tue, 29 Aug 2023 15:59:12 +0800 Message-ID: Subject: Re: [RISCV] [GNU AS] Possible `vmsge{u}.vx` instruction lowering bug? To: Jan Beulich Cc: im Kiva , binutils@sourceware.org Content-Type: multipart/alternative; boundary="000000000000674a9f06040b3020" X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000674a9f06040b3020 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Is the following expected? Seems "vd is any" also has the same issue. Nelson diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 959cbbc32a5..e49b34fd524 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1966,13 +1966,13 @@ vector_macro (struct riscv_cl_insn *ip) /* Masked. Have vtemp to avoid overlap constraints. */ if (vd =3D=3D vm) { - macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); } else { /* Preserve the value of vd if not updating by vm. */ - macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); @@ -2001,13 +2001,13 @@ vector_macro (struct riscv_cl_insn *ip) /* Masked. Have vtemp to avoid overlap constraints. */ if (vd =3D=3D vm) { - macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); } else { /* Preserve the value of vd if not updating by vm. */ - macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d index dcc951a3cbf..aa633e357c9 100644 --- a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d @@ -11,9 +11,9 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4 [ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 -[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6e85c657[ ]+vmslt.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 -[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6e85c657[ ]+vmslt.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 [ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 @@ -21,9 +21,9 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4 [ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 -[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6a85c657[ ]+vmsltu.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 -[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6a85c657[ ]+vmsltu.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 [ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 On Tue, Aug 29, 2023 at 3:43=E2=80=AFPM Jan Beulich wro= te: > On 29.08.2023 08:52, im Kiva via Binutils wrote: > > Hi maintainers, > > > > I discovered that GNU Assembler (as) lowers `vmsge.vx` and `vmsgeu.vx` > (pseudo > > instructions from RISC-V Vector Extension [1]) when the destination > > register is v0 as follows: > > > > vmsge{u}.vx v0, v4, a0, v0.t, v2 > > > > will be expanded to: > > > > vmslt{u}.vx v2, v4, a0, v0.t > > vmandn.mm v0, v0, v2 > > > > You can inspect the lowering result with Godbolt [2]. > > However, according to the Vector specification [1] page 52. The > "desugared" > > `vmslt{u}.vx` is not masked: > > > >> masked va >=3D x, vd =3D=3D v0 > >> pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt > >> expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt > > > > So the spec-expected result of the example above should be: > > vmslt{u}.vx v2, v4, a0 <-- no v0.t here > > vmandn.mm v0, v0, v2 > > > > I thus submitted a patch to the LLVM [3], and it was accepted recently. > > > > I am wondering if binutils considers it a bug, or if it is just > intentional > > because of some historical and compatibility reasons. > > I think this wants fixing alike in binutils: From looking at > vector_macro(), > it appears that emitting the masked form is merely an accident resulting > from the inverted encoding of "masking". In particular, if masking was > indeed meant, I expect code there would be > > if (vd =3D=3D vm) > { > macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vtemp, > vs2, vs1, vm); > macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, > vm, vtemp); > } > else > ... > > much like it is a few lines down from there. (Apparently the "else" path > omitted above is similarly affected.) > > Jan > --000000000000674a9f06040b3020--