From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x33.google.com (mail-oa1-x33.google.com [IPv6:2001:4860:4864:20::33]) by sourceware.org (Postfix) with ESMTPS id 0D3C3386103B for ; Mon, 19 Feb 2024 01:44:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D3C3386103B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0D3C3386103B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:4860:4864:20::33 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708307061; cv=none; b=dtlORwCcD9byreKF+Bpo9uD4IaPgQS5gbCVZ1ifmbH/kmkhGqI7BxvsmIuPE5i7r6DkorJDHmOQG5PvbCZj6C1wPdSg4WxKkbzMYYnsjAZboOIbVQhy1oFL4tS/D8cuPFnWGl903thjIvcvOazWsGJFX/VzfHFr7VdFaHUiq63g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708307061; c=relaxed/simple; bh=uSos6WjRwUTEygXHQaNuuWeaKSd3tNXDiCS2N62PjM0=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=eYpVUPs9vwORlYtAlqhpFPPYFTGuTxYeogeBWNGiJg8KWbgqMq7F9Kai7SR6GQjwzMzShwncCyyp8aU16m3dPXAlgr16PFtcOq7MArt2i42Ikl+SL4raxrfW3Jf5qSNvm9KwA+iSex0VwuUmfY8rnZTNz/85G2IMroBeiM71XdQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-21e45ece781so2271904fac.0 for ; Sun, 18 Feb 2024 17:44:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1708307057; x=1708911857; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=u1ROx4U2vM3uQpDnjCVwjO9WudBDCJGduNyIhEfW/4w=; b=RiIPxcsn4DHm2nRZ2QzAA/ZV2GSaYcH8HG3NG3qf3Vt9uhpBBmw2gn0U6b6CE6LBAd NUV0JtVYOKJv6FYN7zt9fhUPZuzp+U3xAbOZJSQl5zXNDadlWTNm8xFSw5mdNOqudk6N nHXA2znMNH78GcA/NW8En2xdDdzac6Z7qoI/CuBhoUL+tl08eex5rKdo4EGP8Q6YV2Aa sq06CFO2JiehbGUtBV/TTyIGZ5C6bcsvj6lOMwlDADEij9I740RbuJ2SA+CDzAOiEU7J fbvoDoj/psMBvtmwRMDpaYCX4L5Pv50xz7Bbkw9HW/tkWd1tw0Zi4KJpGzBzy6ueW5bn jjCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708307057; x=1708911857; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=u1ROx4U2vM3uQpDnjCVwjO9WudBDCJGduNyIhEfW/4w=; b=C3pBv/VKKg3HVr7emT9OYq2AIg1+HvPXG1idxIfrKB1w0HdH+JiGFfKiJq3VEtbZJw Vbl0A3FRfLC+M2ceYnuUZ/EsoUl+3LbTYH9UJpW8udc5C3hsBIY3wcMBbnn2QTDdQdGb wQ4cJbzxK2nlF8auTg8v1L9viiNRIAPSr82Q42ovJ7uaKHNKm6kgHo2l8ScWpnwbZK42 cB8MbnZuFpT9nUQPG4CuEb7dR+ye9eS2PEnIA0WLJrmRgco3AIqH2p3IUihljrda+BjN uRPJdXu543HJXKZXAhxsXWOW+UtGToEus6toGhMBbO/r0ued+g5f93ut7Ik7ibupXqze Iy7A== X-Gm-Message-State: AOJu0Yy2AX9AmbuLTX4J5ftRxxyqU9xuF1wISKd64y7I+0X58k3ON2BY 4zIUPf8yhg80mrUaTkOzxry9UHYUkWzAtSTdYNbXpNdC0RdJ/jQ1+/D33plnWxEKx/Bte/DO+AL uXPsFqHXIB8YDJH5T1x9wWG5B/pIo7jd2XXrlTw== X-Google-Smtp-Source: AGHT+IE+P1TOEMH5BYF1WS2+peq0zQz0AvdC0QevyNH2lJk0ZlbcLpHGrTw4R2Q+LM5t6HMQqXha0TwoBv/z5JxUUjw= X-Received: by 2002:a05:6870:1581:b0:21e:bb30:e2b7 with SMTP id j1-20020a056870158100b0021ebb30e2b7mr3511023oab.50.1708307057386; Sun, 18 Feb 2024 17:44:17 -0800 (PST) MIME-Version: 1.0 References: <20230817180852.121628-2-ishitatsuyuki@gmail.com> <20231128085109.28422-1-ishitatsuyuki@gmail.com> <20231128085109.28422-4-ishitatsuyuki@gmail.com> In-Reply-To: <20231128085109.28422-4-ishitatsuyuki@gmail.com> From: Nelson Chu Date: Mon, 19 Feb 2024 09:44:06 +0800 Message-ID: Subject: Re: [PATCH v3 3/9] RISC-V: Add assembly support for TLSDESC. To: Tatsuyuki Ishi Cc: binutils@sourceware.org, i@maskray.me, rui314@gmail.com, ruiu@bluewhale.systems Content-Type: multipart/alternative; boundary="00000000000052ba800611b23bd2" X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000052ba800611b23bd2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Nov 28, 2023 at 4:51=E2=80=AFPM Tatsuyuki Ishi wrote: > gas/ > * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi, > %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype > renamed to percent_op_relax_only as this matcher is extended to handle > jalr as well which is not R-type. > (riscv_ip): Apply the percent_op_relax_only rename and update comment. > (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to > TLS relocation check list. > * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation > generation. > opcodes/ > * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with > %tlsdesc_call annotations. > --- > gas/config/tc-riscv.c | 18 +++++++++++++----- > gas/testsuite/gas/riscv/tlsdesc.d | 22 ++++++++++++++++++++++ > gas/testsuite/gas/riscv/tlsdesc.s | 24 ++++++++++++++++++++++++ > opcodes/riscv-opc.c | 1 + > 4 files changed, 60 insertions(+), 5 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/tlsdesc.d > create mode 100644 gas/testsuite/gas/riscv/tlsdesc.s > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 04738d5e00c..376d2a34530 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -2113,6 +2113,7 @@ static const struct percent_op_match > percent_op_utype[] =3D > {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, > {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, > {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, > + {"tlsdesc_hi", BFD_RELOC_RISCV_TLSDESC_HI20}, > {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, > {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, > {"hi", BFD_RELOC_RISCV_HI20}, > @@ -2124,6 +2125,8 @@ static const struct percent_op_match > percent_op_itype[] =3D > {"lo", BFD_RELOC_RISCV_LO12_I}, > {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, > {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, > + {"tlsdesc_load_lo", BFD_RELOC_RISCV_TLSDESC_LOAD_LO12}, > + {"tlsdesc_add_lo", BFD_RELOC_RISCV_TLSDESC_ADD_LO12}, > {0, 0} > }; > > @@ -2135,8 +2138,9 @@ static const struct percent_op_match > percent_op_stype[] =3D > {0, 0} > }; > > -static const struct percent_op_match percent_op_rtype[] =3D > +static const struct percent_op_match percent_op_relax_only[] =3D > { > + {"tlsdesc_call", BFD_RELOC_RISCV_TLSDESC_CALL}, > {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, > {0, 0} > }; > @@ -3244,10 +3248,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, > expressionS *imm_expr, > *imm_reloc =3D BFD_RELOC_RISCV_LO12_I; > goto load_store; > case '1': > - /* This is used for TLS, where the fourth operand is > - %tprel_add, to get a relocation applied to an add > - instruction, for relaxation to use. */ > - p =3D percent_op_rtype; > + /* This is used for TLS relocations that acts as relaxation > + markers and do not change the instruction encoding, > + i.e. %tprel_add and %tlsdesc_call. */ > + p =3D percent_op_relax_only; > Okay, looks good. > goto alu_op; > case '0': /* AMO displacement, which must be zero. */ > load_store: > @@ -4036,6 +4040,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg > ATTRIBUTE_UNUSED) > case BFD_RELOC_RISCV_TPREL_LO12_I: > case BFD_RELOC_RISCV_TPREL_LO12_S: > case BFD_RELOC_RISCV_TPREL_ADD: > + case BFD_RELOC_RISCV_TLSDESC_HI20: > relaxable =3D true; > /* Fall through. */ > > @@ -4209,6 +4214,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg > ATTRIBUTE_UNUSED) > > case BFD_RELOC_RISCV_CALL: > case BFD_RELOC_RISCV_CALL_PLT: > + case BFD_RELOC_RISCV_TLSDESC_LOAD_LO12: > + case BFD_RELOC_RISCV_TLSDESC_ADD_LO12: > + case BFD_RELOC_RISCV_TLSDESC_CALL: > relaxable =3D true; > break; > > diff --git a/gas/testsuite/gas/riscv/tlsdesc.d > b/gas/testsuite/gas/riscv/tlsdesc.d > new file mode 100644 > index 00000000000..11872953d23 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/tlsdesc.d > @@ -0,0 +1,22 @@ > +#as: -march=3Drv32ia > Probably can remove the architecture setting, so that we can test more situations. > +#source: tlsdesc.s > +#readelf: -Wr > #objdump: -dr maye be better. > + > +Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 16 entrie= s: > + +Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend > +0+ +0+a3e +R_RISCV_TLSDESC_HI20 +0+ +sg1 \+ 0 > +0+ +0+33 +R_RISCV_RELAX + 0 > +0+4 +0+63f +R_RISCV_TLSDESC_LOAD_LO12 0+ +\.desc1 \+ 0 > +0+4 +0+33 +R_RISCV_RELAX + 0 > +0+8 +0+640 +R_RISCV_TLSDESC_ADD_LO12 0+ +\.desc1 \+ 0 > +0+8 +0+33 +R_RISCV_RELAX + 0 > +0+c +0+641 +R_RISCV_TLSDESC_CALL +0+ +\.desc1 \+ 0 > +0+c +0+33 +R_RISCV_RELAX + 0 > +0+10 +0+53e +R_RISCV_TLSDESC_HI20 +0+4 +sl1 \+ 0 > +0+10 +0+33 +R_RISCV_RELAX + 0 > +0+14 +0+83f +R_RISCV_TLSDESC_LOAD_LO12 0+10 +\.desc2 \+ 0 > +0+14 +0+33 +R_RISCV_RELAX + 0 > +0+18 +0+840 +R_RISCV_TLSDESC_ADD_LO12 0+10 +\.desc2 \+ 0 > +0+18 +0+33 +R_RISCV_RELAX +0 > +0+1c +0+841 +R_RISCV_TLSDESC_CALL +0+10 +\.desc2 \+ 0 > +0+1c +0+33 +R_RISCV_RELAX +0 [ ] means [space+tab] 0+000 <_start>: [ ]+0:[ ]+[0-9a-f]+[ ]+auipc[ ]+a0,0x0 [ ]+0:[ ]+R_RISCV_TLSDESC_HI20[ ]+sg1 [ ]+0:[ ]+R_RISCV_RELAX[ ]+0 ... > diff --git a/gas/testsuite/gas/riscv/tlsdesc.s > b/gas/testsuite/gas/riscv/tlsdesc.s > new file mode 100644 > index 00000000000..15468d5f947 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/tlsdesc.s > @@ -0,0 +1,24 @@ > + .section .tbss,"awT",@nobits > + .global sg1 > +sg1: > + .zero 4 > +sl1: > + .zero 4 > + > + .text > + .globl _start > + .type _start,@function > +_start: > +.desc1: > + auipc a0, %tlsdesc_hi(sg1) > + lw t0, %tlsdesc_load_lo(.desc1)(a0) > + addi a0, a0, %tlsdesc_add_lo(.desc1) > + jalr t0, t0, %tlsdesc_call(.desc1) > + > +.desc2: > + auipc a0, %tlsdesc_hi(sl1) > + lw t0, %tlsdesc_load_lo(.desc2)(a0) > + addi a0, a0, %tlsdesc_add_lo(.desc2) > + jalr t0, t0, %tlsdesc_call(.desc2) > + > + ret > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index bf19978e025..edaf4b0c8b5 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -372,6 +372,7 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA << > OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, > {"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR, > MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, > {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, > match_opcode, INSN_JSR }, > +{"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR, > MASK_JALR|MASK_IMM, match_opcode, INSN_JSR }, > {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, > match_opcode, INSN_JSR }, > {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, > match_opcode, INSN_ALIAS|INSN_BRANCH }, > {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, > MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, > -- > 2.43.0 > > --00000000000052ba800611b23bd2--