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ssWhH7/+a4+zBTar0uImwFBszzebHqCgtBEhrggE1SbqY652WZPk3agrrA== X-Google-Smtp-Source: AGHT+IG3zn5OHzU9+3t71izfXik0380EFT4DgnVDTHzfepDU07XKBtVEmyHNd2RX+Lv0boafCDpQbYD9BHZG9uS3/xE= X-Received: by 2002:a05:6870:330a:b0:1f5:cf59:1ed2 with SMTP id x10-20020a056870330a00b001f5cf591ed2mr9687542oae.13.1700540451794; Mon, 20 Nov 2023 20:20:51 -0800 (PST) MIME-Version: 1.0 References: <20231113121425.958923-1-mary.bennett@embecosm.com> <20231113121425.958923-2-mary.bennett@embecosm.com> In-Reply-To: <20231113121425.958923-2-mary.bennett@embecosm.com> From: Nelson Chu Date: Tue, 21 Nov 2023 12:20:40 +0800 Message-ID: Subject: Re: [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P To: Mary Bennett Cc: binutils@sourceware.org Content-Type: multipart/alternative; boundary="0000000000008e44a3060aa1edb0" X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000008e44a3060aa1edb0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Nov 13, 2023 at 8:15=E2=80=AFPM Mary Bennett wrote: > Spec: > https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/inst= ruction_set_extensions.html > > Contributors: > Mary Bennett > Nandni Jamnadas > Pietra Ferreira > Charlie Keaney > Jessica Mills > Craig Blackmore > Simon Cook > Jeremy Bennett > Helene Chelin > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` > instruction class. > (riscv_multi_subset_supports_ext): Likewise. > > gas/ChangeLog: > > * doc/c-riscv.texi: Note XCVelw as an additional ISA extension > for CORE-V. > * testsuite/gas/riscv/cv-elw-fail.d: New test. > * testsuite/gas/riscv/cv-elw-fail.l: New test. > * testsuite/gas/riscv/cv-elw-fail.s: New test. > * testsuite/gas/riscv/cv-elw-fail-march.d: New test. > * testsuite/gas/riscv/cv-elw-fail-march.l: New test. > * testsuite/gas/riscv/cv-elw-fail-march.s: New test. > * testsuite/gas/riscv/cv-elw-pass.d: New test. > * testsuite/gas/riscv/cv-elw-pass.s: New test. > > opcodes/ChangeLog: > > * riscv-opc.c: (riscv_opcode) Add event load instructions. > > include/ChangeLog: > > * opcode/riscv-opc.h: Add corresponding MATCH and MASK > instruction opcode macros. > * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW. > --- > bfd/elfxx-riscv.c | 5 +++ > gas/doc/c-riscv.texi | 5 +++ > gas/testsuite/gas/riscv/cv-elw-fail-march.d | 3 ++ > gas/testsuite/gas/riscv/cv-elw-fail-march.l | 38 +++++++++++++++++ > gas/testsuite/gas/riscv/cv-elw-fail-march.s | 42 +++++++++++++++++++ > gas/testsuite/gas/riscv/cv-elw-fail.d | 3 ++ > gas/testsuite/gas/riscv/cv-elw-fail.l | 5 +++ > gas/testsuite/gas/riscv/cv-elw-fail.s | 8 ++++ > gas/testsuite/gas/riscv/cv-elw-pass.d | 46 +++++++++++++++++++++ > gas/testsuite/gas/riscv/cv-elw-pass.s | 42 +++++++++++++++++++ > include/opcode/riscv-opc.h | 3 ++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 3 ++ > 13 files changed, 204 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.l > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s > create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d > create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index c9acf124626..545588b5afd 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1361,6 +1361,7 @@ static struct riscv_supported_ext > riscv_supported_vendor_x_ext[] =3D > { > {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -2556,6 +2557,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t > *rps, > return riscv_subset_supports (rps, "xcvmac"); > case INSN_CLASS_XCVALU: > return riscv_subset_supports (rps, "xcvalu"); > + case INSN_CLASS_XCVELW: > + return riscv_subset_supports (rps, "xcvelw"); > case INSN_CLASS_XTHEADBA: > return riscv_subset_supports (rps, "xtheadba"); > case INSN_CLASS_XTHEADBB: > @@ -2800,6 +2803,8 @@ riscv_multi_subset_supports_ext > (riscv_parse_subset_t *rps, > return "xcvmac"; > case INSN_CLASS_XCVALU: > return "xcvalu"; > + case INSN_CLASS_XCVELW: > + return "xcvelw"; > case INSN_CLASS_XTHEADBA: > return "xtheadba"; > case INSN_CLASS_XTHEADBB: > diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi > index b23504648bd..8d2b8b2d4bb 100644 > --- a/gas/doc/c-riscv.texi > +++ b/gas/doc/c-riscv.texi > @@ -754,6 +754,11 @@ The Xcvalu extension provides instructions for > general ALU operations. > > It is documented in @url{ > https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/inst= ruction_set_extensions.html > } > > +@item Xcvelw > +The Xcvelw extension provides instructions for event load word operation= s. > + > +It is documented in @url{ > https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/inst= ruction_set_extensions.html > } > + > @item XTheadBa > The XTheadBa extension provides instructions for address calculations. > > diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.d > b/gas/testsuite/gas/riscv/cv-elw-fail-march.d > new file mode 100644 > index 00000000000..5a3a6dba66b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i > +#source: cv-elw-fail-march.s > +#error_output: cv-elw-fail-march.l > diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.l > b/gas/testsuite/gas/riscv/cv-elw-fail-march.l > new file mode 100644 > index 00000000000..760a71b3827 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.l > @@ -0,0 +1,38 @@ > +.*: Assembler messages: > +.*: Error: unrecognized opcode `cv.elw x5,-2048\(x6\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x5,0\(x6\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x5,20\(x6\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x5,2047\(x6\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x31,2047\(x31\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x0,0\(x0\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x1,1024\(x1\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x2,1024\(x2\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x3,1024\(x3\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x4,1024\(x4\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x5,1024\(x5\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x6,1024\(x6\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x7,1024\(x7\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x8,1024\(x8\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x9,1024\(x9\)', extension `xcvelw' > required > +.*: Error: unrecognized opcode `cv.elw x10,1024\(x10\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x11,1024\(x11\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x12,1024\(x12\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x13,1024\(x13\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x14,1024\(x14\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x15,1024\(x15\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x16,1024\(x16\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x17,1024\(x17\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x18,1024\(x18\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x19,1024\(x19\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x20,1024\(x20\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x21,1024\(x21\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x22,1024\(x22\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x23,1024\(x23\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x24,1024\(x24\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x25,1024\(x25\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x26,1024\(x26\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x27,1024\(x27\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x28,1024\(x28\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x29,1024\(x29\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x30,1024\(x30\)', extension > `xcvelw' required > +.*: Error: unrecognized opcode `cv.elw x31,1024\(x31\)', extension > `xcvelw' required > diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.s > b/gas/testsuite/gas/riscv/cv-elw-fail-march.s > new file mode 100644 > index 00000000000..8728f1cbdee > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.s > @@ -0,0 +1,42 @@ > +target: > + # Immediate Boundary Tests > + cv.elw x5,-2048(x6) > + cv.elw x5,0(x6) > + cv.elw x5,20(x6) > + cv.elw x5,2047(x6) > + cv.elw x31,2047(x31) > + > + # Register Boundary Tests > + cv.elw x0,0(x0) > + cv.elw x1,1024(x1) > + cv.elw x2,1024(x2) > + cv.elw x3,1024(x3) > + cv.elw x4,1024(x4) > + cv.elw x5,1024(x5) > + cv.elw x6,1024(x6) > + cv.elw x7,1024(x7) > + cv.elw x8,1024(x8) > + cv.elw x9,1024(x9) > + cv.elw x10,1024(x10) > + cv.elw x11,1024(x11) > + cv.elw x12,1024(x12) > + cv.elw x13,1024(x13) > + cv.elw x14,1024(x14) > + cv.elw x15,1024(x15) > + cv.elw x16,1024(x16) > + cv.elw x17,1024(x17) > + cv.elw x18,1024(x18) > + cv.elw x19,1024(x19) > + cv.elw x20,1024(x20) > + cv.elw x21,1024(x21) > + cv.elw x22,1024(x22) > + cv.elw x23,1024(x23) > + cv.elw x24,1024(x24) > + cv.elw x25,1024(x25) > + cv.elw x26,1024(x26) > + cv.elw x27,1024(x27) > + cv.elw x28,1024(x28) > + cv.elw x29,1024(x29) > + cv.elw x30,1024(x30) > + cv.elw x31,1024(x31) > + > \ No newline at end of file > diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.d > b/gas/testsuite/gas/riscv/cv-elw-fail.d > new file mode 100644 > index 00000000000..d7fd1d1a6cb > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-fail.d > @@ -0,0 +1,3 @@ > +#as: -march=3Drv32i_xcvelw > +#source: cv-elw-fail.s > +#error_output: cv-elw-fail.l > diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.l > b/gas/testsuite/gas/riscv/cv-elw-fail.l > new file mode 100644 > index 00000000000..4d3f15ba138 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-fail.l > @@ -0,0 +1,5 @@ > +.*: Assembler messages: > +.*: Error: illegal operands `cv.elw x5,-2049\(x6\)' > +.*: Error: illegal operands `cv.elw x5,2048\(x6\)' > +.*: Error: illegal operands `cv.elw x-1,1024\(x-1\)' > +.*: Error: illegal operands `cv.elw x32,1024\(x32\)' > \ No newline at end of file > diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.s > b/gas/testsuite/gas/riscv/cv-elw-fail.s > new file mode 100644 > index 00000000000..4ce122297f4 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-fail.s > @@ -0,0 +1,8 @@ > +target: > + # Immediate Boundary Tests > + cv.elw x5,-2049(x6) > + cv.elw x5,2048(x6) > + > + # Register Boundary Tests > + cv.elw x-1,1024(x-1) > + cv.elw x32,1024(x32) > diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.d > b/gas/testsuite/gas/riscv/cv-elw-pass.d > new file mode 100644 > index 00000000000..fed2c870e7e > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-pass.d > @@ -0,0 +1,46 @@ > +#as: -march=3Drv32i_xcvelw > +#source: cv-elw-pass.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+0:[ ]+80036283[ ]+cv.elw[ ]+t0,-2048\(t1\) > +[ ]+4:[ ]+00036283[ ]+cv.elw[ ]+t0,0\(t1\) > +[ ]+8:[ ]+01436283[ ]+cv.elw[ ]+t0,20\(t1\) > +[ ]+c:[ ]+7ff36283[ ]+cv.elw[ ]+t0,2047\(t1\) > +[ ]+10:[ ]+7fffef83[ ]+cv.elw[ ]+t6,2047\(t6\) > +[ ]+14:[ ]+00006003[ ]+cv.elw[ ]+zero,0\(zero\) # 0 > > +[ ]+18:[ ]+4000e083[ ]+cv.elw[ ]+ra,1024\(ra\) > +[ ]+1c:[ ]+40016103[ ]+cv.elw[ ]+sp,1024\(sp\) > +[ ]+20:[ ]+4001e183[ ]+cv.elw[ ]+gp,1024\(gp\) > +[ ]+24:[ ]+40026203[ ]+cv.elw[ ]+tp,1024\(tp\) # 400 > > +[ ]+28:[ ]+4002e283[ ]+cv.elw[ ]+t0,1024\(t0\) > +[ ]+2c:[ ]+40036303[ ]+cv.elw[ ]+t1,1024\(t1\) > +[ ]+30:[ ]+4003e383[ ]+cv.elw[ ]+t2,1024\(t2\) > +[ ]+34:[ ]+40046403[ ]+cv.elw[ ]+s0,1024\(s0\) > +[ ]+38:[ ]+4004e483[ ]+cv.elw[ ]+s1,1024\(s1\) > +[ ]+3c:[ ]+40056503[ ]+cv.elw[ ]+a0,1024\(a0\) > +[ ]+40:[ ]+4005e583[ ]+cv.elw[ ]+a1,1024\(a1\) > +[ ]+44:[ ]+40066603[ ]+cv.elw[ ]+a2,1024\(a2\) > +[ ]+48:[ ]+4006e683[ ]+cv.elw[ ]+a3,1024\(a3\) > +[ ]+4c:[ ]+40076703[ ]+cv.elw[ ]+a4,1024\(a4\) > +[ ]+50:[ ]+4007e783[ ]+cv.elw[ ]+a5,1024\(a5\) > +[ ]+54:[ ]+40086803[ ]+cv.elw[ ]+a6,1024\(a6\) > +[ ]+58:[ ]+4008e883[ ]+cv.elw[ ]+a7,1024\(a7\) > +[ ]+5c:[ ]+40096903[ ]+cv.elw[ ]+s2,1024\(s2\) > +[ ]+60:[ ]+4009e983[ ]+cv.elw[ ]+s3,1024\(s3\) > +[ ]+64:[ ]+400a6a03[ ]+cv.elw[ ]+s4,1024\(s4\) > +[ ]+68:[ ]+400aea83[ ]+cv.elw[ ]+s5,1024\(s5\) > +[ ]+6c:[ ]+400b6b03[ ]+cv.elw[ ]+s6,1024\(s6\) > +[ ]+70:[ ]+400beb83[ ]+cv.elw[ ]+s7,1024\(s7\) > +[ ]+74:[ ]+400c6c03[ ]+cv.elw[ ]+s8,1024\(s8\) > +[ ]+78:[ ]+400cec83[ ]+cv.elw[ ]+s9,1024\(s9\) > +[ ]+7c:[ ]+400d6d03[ ]+cv.elw[ ]+s10,1024\(s10\) > +[ ]+80:[ ]+400ded83[ ]+cv.elw[ ]+s11,1024\(s11\) > +[ ]+84:[ ]+400e6e03[ ]+cv.elw[ ]+t3,1024\(t3\) > +[ ]+88:[ ]+400eee83[ ]+cv.elw[ ]+t4,1024\(t4\) > +[ ]+8c:[ ]+400f6f03[ ]+cv.elw[ ]+t5,1024\(t5\) > +[ ]+90:[ ]+400fef83[ ]+cv.elw[ ]+t6,1024\(t6\) > diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.s > b/gas/testsuite/gas/riscv/cv-elw-pass.s > new file mode 100644 > index 00000000000..ed6d1882f06 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/cv-elw-pass.s > @@ -0,0 +1,42 @@ > +target: > + # Immediate Boundary Tests > + cv.elw x5,-2048(x6) > + cv.elw x5,0(x6) > + cv.elw x5,20(x6) > + cv.elw x5,2047(x6) > + cv.elw x31,2047(x31) > + > + # Register Boundary Tests > + cv.elw x0,0(x0) > + cv.elw x1,1024(x1) > + cv.elw x2,1024(x2) > + cv.elw x3,1024(x3) > + cv.elw x4,1024(x4) > + cv.elw x5,1024(x5) > + cv.elw x6,1024(x6) > + cv.elw x7,1024(x7) > + cv.elw x8,1024(x8) > + cv.elw x9,1024(x9) > + cv.elw x10,1024(x10) > + cv.elw x11,1024(x11) > + cv.elw x12,1024(x12) > + cv.elw x13,1024(x13) > + cv.elw x14,1024(x14) > + cv.elw x15,1024(x15) > + cv.elw x16,1024(x16) > + cv.elw x17,1024(x17) > + cv.elw x18,1024(x18) > + cv.elw x19,1024(x19) > + cv.elw x20,1024(x20) > + cv.elw x21,1024(x21) > + cv.elw x22,1024(x22) > + cv.elw x23,1024(x23) > + cv.elw x24,1024(x24) > + cv.elw x25,1024(x25) > + cv.elw x26,1024(x26) > + cv.elw x27,1024(x27) > + cv.elw x28,1024(x28) > + cv.elw x29,1024(x29) > + cv.elw x30,1024(x30) > + cv.elw x31,1024(x31) > + > \ No newline at end of file > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index 24217062edc..3d521703b98 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2424,6 +2424,9 @@ > #define MASK_CV_SUBRN 0xc000707f > #define MATCH_CV_SUBURN 0xc000305b > #define MASK_CV_SUBURN 0xc000707f > +/* Vendor-specific (CORE-V) Xcvelw instructions. */ > +#define MATCH_CV_ELW 0x6003 > +#define MASK_CV_ELW 0x707f > Seems like this encoding is the same as standard 64-bit LWU. So, 1. Could we just use MATCH/MASK_LWU to replace MATCH/MASK_CV_ELW? 2. Does that mean even if Xcvelw is enabled, under rv64 the cv.elw will still be lwu? Thanks Nelson > /* Vendor-specific (T-Head) XTheadBa instructions. */ > #define MATCH_TH_ADDSL 0x0000100b > #define MASK_TH_ADDSL 0xf800707f > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index 710a9b73189..df131aa3680 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -455,6 +455,7 @@ enum riscv_insn_class > INSN_CLASS_H, > INSN_CLASS_XCVMAC, > INSN_CLASS_XCVALU, > + INSN_CLASS_XCVELW, > INSN_CLASS_XTHEADBA, > INSN_CLASS_XTHEADBB, > INSN_CLASS_XTHEADBS, > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 72d727cd77e..c3fb20ec345 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -2100,6 +2100,9 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, > MASK_CV_SUBRNR, match_opcode, 0}, > {"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, > MASK_CV_SUBURNR, match_opcode, 0}, > > +/* Vendor-specific (CORE-V) Xcvelw instructions. */ > +{"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)", MATCH_CV_ELW, MASK_CV_ELW, > match_opcode, 0}, > + > /* Vendor-specific (T-Head) XTheadBa instructions. */ > {"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", > MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0}, > > -- > 2.34.1 > > --0000000000008e44a3060aa1edb0--