From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id 921043858425 for ; Thu, 22 Dec 2022 01:51:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 921043858425 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-ed1-x52b.google.com with SMTP id e13so1012286edj.7 for ; Wed, 21 Dec 2022 17:51:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=bRrPVSyHXpcgGvjToyReGdb0r+CN+CF/XKylBDynLb8=; b=2svnS2we0sL6hu73lsQiuRli9IrnEm4H6Q13h1Q31hBYfXhmmcC+hkFvQVmYY/+xbk 188ckKQfgVKCOhf4zhiatjc0gbZVAysA2pqXrr0WN7FPG4FDymQGEKrRxG2zPJ2SgQv+ gl6NIS8jO2O3bMAqlrtq6CsRTe+BfRZUsyIXSKD/+rswHfH7nvJap+6VbUb+pvbC9YkE kP59oX89MMxKZf7j6vzEGh/ZqA7JXvzDg9Ax1gsoZ9g/t+Og+4NbdnNfehSae4RxzZMs Kje7UlfZxT2ylAGnsrqCSSr1kg3ykzwTLXW8oBkoKD04fD37UZjnxiWAPLfKsWRBn/5n 9PqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bRrPVSyHXpcgGvjToyReGdb0r+CN+CF/XKylBDynLb8=; b=fYhGyWG9Be5Fw1F3tq9sixaSY/V1d13gYbhkXborwojDYTmxftjmtbXrph+bWlqLcC SN/FY/LcHga0v6SO7LuiuOGAdyp0dMs8gbBcQqvryJsU6VmZ14iBSod1hZHGZXKz+wJy WpIil19urcoWOP2E47eDKMQw5EYNgC+RRC72bjYZcfvLhTeDPMgeJvTtZ+JNd68hi+On GHgocjVQginXcmcpDTy8cRLCHyN3GOxP8yU0VBfJ+Jp9RAibyii3avm8Snjkb2Y8THdk eUabVlLDJuPkotKqOXv7ZGKTY8gK616/QUyE93Fa6dazcahIN28QjkJbSaPPqmVhs6H7 Laag== X-Gm-Message-State: AFqh2kpvTkLxVjQE39cnMXmAMTddlVcd3Rjg0n1wjuBv+ZP10UQfN8Ee 5oO/MIvLaR0Un2qPWO4VoX68H00/JbZDDl+7DWvJxw== X-Google-Smtp-Source: AMrXdXv7ObD9EVrKjjBwj04zcuNWlq2aabRVnMCwoXQsKdNuFCz+DbnOoI5cx8LFLvXrcmBRDmGHNsEyr1eyNPahJgw= X-Received: by 2002:a50:ef0a:0:b0:46f:7453:c9b4 with SMTP id m10-20020a50ef0a000000b0046f7453c9b4mr284213eds.278.1671673870326; Wed, 21 Dec 2022 17:51:10 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Thu, 22 Dec 2022 09:50:59 +0800 Message-ID: Subject: [Offline] Re: [PATCH] RISC-V: Fix T-Head Fmv vendor extension encoding To: Palmer Dabbelt Cc: =?UTF-8?Q?Christoph_M=C3=BCllner?= , Binutils , Andrew Waterman , Philipp Tomsich , Lifang Xia Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Do we expect this in the 2.40 release? I haven't seen this in master for n= ow. Thanks Nelson On Sat, Dec 17, 2022 at 3:00 AM Palmer Dabbelt wrote: > > On Fri, 16 Dec 2022 10:59:53 PST (-0800), christoph.muellner@vrull.eu wro= te: > > On Fri, Dec 16, 2022 at 7:56 PM Palmer Dabbelt wro= te: > > > >> On Fri, 16 Dec 2022 10:51:33 PST (-0800), christoph.muellner@vrull.eu > >> wrote: > >> > From: Christoph M=C3=BCllner > >> > > >> > A recent change in the XTheadFmv spec fixed an encoding bug in the > >> > document. This patch changes the code to follow this bugfix. > >> > > >> > Spec patch can be found here: > >> > https://github.com/T-head-Semi/thead-extension-spec/pull/11 > >> > >> There's not much info in there. Was this just a bug in the ISA manual= ? > >> In other words, does the existing hardware (I know of at least C906s a= nd > >> C910s in the wild) behave the new way already? In that case > >> > > > > Yes, this was just a bug in the ISA manual, which slipped through the > > review. > > The manual now matches the implementation. > > OK, thanks! > > > > > > > > >> > >> Reviewed-by: Palmer Dabbelt > >> > >> but if the hardware has the old behavior then we'll need to do somethi= ng > >> more complicated to avoid breaking compatibility. > >> > >> > > >> > Signed-off-by: Christoph M=C3=BCllner > >> > --- > >> > gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++-- > >> > include/opcode/riscv-opc.h | 4 ++-- > >> > 2 files changed, 4 insertions(+), 4 deletions(-) > >> > > >> > diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d > >> b/gas/testsuite/gas/riscv/x-thead-fmv.d > >> > index f2bbe010beb..af8ce0c8ee0 100644 > >> > --- a/gas/testsuite/gas/riscv/x-thead-fmv.d > >> > +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d > >> > @@ -7,5 +7,5 @@ > >> > Disassembly of section .text: > >> > > >> > 0+000 : > >> > -[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 > >> > -[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 > >> > +[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 > >> > +[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 > >> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > >> > index 06e3df0f5a6..5420bfac91b 100644 > >> > --- a/include/opcode/riscv-opc.h > >> > +++ b/include/opcode/riscv-opc.h > >> > @@ -2209,9 +2209,9 @@ > >> > #define MATCH_TH_FSURW 0x5000700b > >> > #define MASK_TH_FSURW 0xf800707f > >> > /* Vendor-specific (T-Head) XTheadFmv instructions. */ > >> > -#define MATCH_TH_FMV_HW_X 0x6000100b > >> > +#define MATCH_TH_FMV_HW_X 0x5000100b > >> > #define MASK_TH_FMV_HW_X 0xfff0707f > >> > -#define MATCH_TH_FMV_X_HW 0x5000100b > >> > +#define MATCH_TH_FMV_X_HW 0x6000100b > >> > #define MASK_TH_FMV_X_HW 0xfff0707f > >> > /* Vendor-specific (T-Head) XTheadInt instructions. */ > >> > #define MATCH_TH_IPOP 0x0050000b > >>