From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by sourceware.org (Postfix) with ESMTPS id 43D3A3858D35 for ; Thu, 21 Sep 2023 00:19:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 43D3A3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-1d69c93954fso234228fac.0 for ; Wed, 20 Sep 2023 17:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1695255547; x=1695860347; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=u5Mf26K4BtBBZ4jo78xxYWax2SYUspbX16wYpWXG0PI=; b=ykLXZoQNH1C5R+S5ZyxmaSSloIflLQXUYqx2jmVRyu3A5Od/tzDnid5DwsrUeI7czA YHgP30BsOsZD0da+75hmpkrKxBf2XLZ/aHyC1IvNxDguTNwCih/NE/s2iBasFObxs3Dp znhTV0053kUkWlIA0cn2jcdhiKr4UG6Tgm0Pc0ZtK+5h6OL6yF3D1Wcl6MR34ylPPVM5 Ph17Jy4uI0KEFouvnd9yEh+PA16PPo8Av3KUYarz1CW2Xsq/vtYlAPqUvsFIsKFd/Msr IKq5cJXMRSOoFHu4xNEbRK6Yq2GDC73Rfdg0u8+1O9ABdo9uHNJwrjiYF50pll+bawjT KggA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695255547; x=1695860347; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=u5Mf26K4BtBBZ4jo78xxYWax2SYUspbX16wYpWXG0PI=; b=u30xR+WuZinkrTH5vbCkqFuTewqHFRTQeJy1xKK1oRdjbTRJGzlA477uAGv3IoXpW6 6FVaLDs+KVtT8EPJETaXzd8THjxGyxCTKKaFMz4uZa6RCBw8z2SomTvMR++Zoi32IeHY LA+oJMNsP/eVp+/O8I7qd0NyozsDu18AaVRxvmplsYpbckwbPH9TiVUs4TduNC8VgE+d n9+ojyzItnrbCgvmcy48d5yZrDkiFVG0XJIgh9qk/SVyGJDM5+s4FJiJXUnpsn0zKFll BLRn58vcpWEYVVyzIhziFWLRkjUC0lUwfQD+yATDtiNwoDv+CfJgZD7EYm5WnCu5Zik1 dzyw== X-Gm-Message-State: AOJu0YzgTcklH7yvd0svFOpegVuCKbpul8YOwBz0BUJFJYBBwWhfvjiL 5FYCZJ3xIUXxNSGx/D3xJw1X1JQ/bAuV3ijnHofzX5mI8/XHrs4nO9c= X-Google-Smtp-Source: AGHT+IEHJJS1XR8npLy1ZLfkbOm835CXFcJdz6aTTzG79QVahVWT12ApwJ+gPgGsGuSHD37iOKGOrbtpel5Y+qK7kgo= X-Received: by 2002:a05:6870:8a0d:b0:1d6:5c83:e6c5 with SMTP id p13-20020a0568708a0d00b001d65c83e6c5mr4363117oaq.44.1695255547365; Wed, 20 Sep 2023 17:19:07 -0700 (PDT) MIME-Version: 1.0 References: <20230920083124.2072273-1-ruiu@bluewhale.systems> In-Reply-To: <20230920083124.2072273-1-ruiu@bluewhale.systems> From: Nelson Chu Date: Thu, 21 Sep 2023 08:18:56 +0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: emit R_RISCV_RELAX for the la pseudo instruction To: Rui Ueyama Cc: binutils@sourceware.org, Rui Ueyama Content-Type: multipart/alternative; boundary="000000000000b45eec0605d3702b" X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000b45eec0605d3702b Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Looks good, thanks! Nelson On Wed, Sep 20, 2023 at 4:34=E2=80=AFPM Rui Ueyama wrote: > Now the macro identifier is stored to tc_fix_data if a relocation > is created as a result of assembler macro expansion. > > > --- > gas/config/tc-riscv.c | 15 +++++++++++++++ > gas/config/tc-riscv.h | 8 ++++++++ > gas/testsuite/gas/riscv/la-variants.d | 3 +++ > 3 files changed, 26 insertions(+) > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 3b520ad208b..c761b793afc 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -59,6 +59,9 @@ struct riscv_cl_insn > fixS *fixp; > }; > > +/* The identifier of the assembler macro we are expanding, if any. */ > +static int source_macro =3D -1; > + > /* All RISC-V CSR belong to one of these classes. */ > enum riscv_csr_class > { > @@ -1659,6 +1662,7 @@ append_insn (struct riscv_cl_insn *ip, expressionS > *address_expr, > address_expr, false, reloc_type); > > ip->fixp->fx_tcbit =3D riscv_opts.relax; > + ip->fixp->tc_fix_data.source_macro =3D source_macro; > } > } > > @@ -2020,6 +2024,8 @@ macro (struct riscv_cl_insn *ip, expressionS > *imm_expr, > int rs2 =3D (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; > int mask =3D ip->insn_mo->mask; > > + source_macro =3D mask; > + > switch (mask) > { > case M_LI: > @@ -2168,6 +2174,8 @@ macro (struct riscv_cl_insn *ip, expressionS > *imm_expr, > as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name= ); > break; > } > + > + source_macro =3D -1; > } > > static const struct percent_op_match percent_op_utype[] =3D > @@ -4049,6 +4057,13 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg > ATTRIBUTE_UNUSED) > break; > > case BFD_RELOC_RISCV_GOT_HI20: > + /* R_RISCV_GOT_HI20 and the following R_RISCV_LO12_I are relaxable > + only if it is created as a result of la or lga assembler macros. > */ > + if (fixP->tc_fix_data.source_macro =3D=3D M_LA || > + fixP->tc_fix_data.source_macro =3D=3D M_LGA) > + relaxable =3D true; > + break; > + > case BFD_RELOC_RISCV_ADD8: > case BFD_RELOC_RISCV_ADD16: > case BFD_RELOC_RISCV_ADD32: > diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h > index 0c70c7d4739..4fba3a07829 100644 > --- a/gas/config/tc-riscv.h > +++ b/gas/config/tc-riscv.h > @@ -101,6 +101,14 @@ extern void riscv_pre_output_hook (void); > #define TC_FORCE_RELOCATION_LOCAL(FIX) 1 > #define DIFF_EXPR_OK 1 > > +struct riscv_fix > +{ > + int source_macro; > +}; > + > +#define TC_FIX_TYPE struct riscv_fix > +#define TC_INIT_FIX_DATA(FIX) (FIX)->tc_fix_data.source_macro =3D -1 > + > extern void riscv_pop_insert (void); > #define md_pop_insert() riscv_pop_insert () > > diff --git a/gas/testsuite/gas/riscv/la-variants.d > b/gas/testsuite/gas/riscv/la-variants.d > index b1d316983b7..e8ac09c2af2 100644 > --- a/gas/testsuite/gas/riscv/la-variants.d > +++ b/gas/testsuite/gas/riscv/la-variants.d > @@ -21,11 +21,13 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+00000617[ ]+auipc[ ]+a2,0x0 > [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a > +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+(00062603|00063603)[ ]+(lw|ld)[ > ]+a2,0\(a2\).* > [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+00000697[ ]+auipc[ ]+a3,0x0 > [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a > +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+(0006a683|0006b683)[ ]+(lw|ld)[ > ]+a3,0\(a3\).* > [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > @@ -37,6 +39,7 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+00000797[ ]+auipc[ ]+a5,0x0 > [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a > +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > [ ]+[0-9a-f]+:[ ]+(0007a783|0007b783)[ ]+(lw|ld)[ > ]+a5,0\(a5\).* > [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ > [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* > -- > 2.34.1 > > --000000000000b45eec0605d3702b--