From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by sourceware.org (Postfix) with ESMTPS id 999B53865488 for ; Thu, 23 May 2024 06:43:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 999B53865488 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 999B53865488 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::531 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716446627; cv=none; b=KZwCAouT42yOko5rzl8LAb2PNs1HOa9+4RrAGuwzEiv+eYAI5czP7rTOGJMNaPhZgRVUmLzVwZf/OfV3R6maBcmK1i6UWUs+DXN288pQTCqWJj8YHCcHIi0iZRwWvGsI+T1Gi2QDlrnWLpyMRAOAyaxnqg4UMgk516F7cgUSgX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716446627; c=relaxed/simple; bh=aMYTwSjs2Y4XNCUqz9XclvNuDnkUM6ufVgKI6Vtwn4Q=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=xBuZxbO0tttQEZQMX3A3HcfeUpFjPMGXWEEd0UsehoRoXsu2HWSDtQ9mmdmfXBNuq1J2qrYNQWkaa2ewggdEygXpTmvQ+8plYIabJgHnekLoToWs9tLzrN8O58Xz3bkHtgFrviFouUQxroyUyikt/mkkMLBrOPDBYnlQQf990l0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-56e56ee8d5cso12535610a12.2 for ; Wed, 22 May 2024 23:43:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1716446622; x=1717051422; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=VrV4PEKbVHecfTxxbgubJClkkJ0VZmY74SS/4a8Zbew=; b=148rocRmp70mpoMhOHdCW5V6v4Jv4BK7aruPhTMah4K0aW7hk4XpChqI26zmeS0Le7 cZofLfPZ9u7amoUKIOhmSf4O9aK38WNnaHrPtZhYMAtAncZcuzKYwWWeusRTFx58qBys nFB/8L+769s0Od+XDGHsNXqdsKi5vG4/4yYS21VVbOjY/N25ULZKvcfmV2FNGADJ8iz2 uoMtCy+c3QEDzrI36/jx82ssuQFfSTgjC0CJJvapCRu3SiILDBTqA91flAxYeyUr0xKU 7QO8HikM6GDShhIQndOuKnYj2q2pF9/lE1ygfo7A8YTL7B7YhRA5V0pE9Mm8G84mh/8R AKWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716446622; x=1717051422; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VrV4PEKbVHecfTxxbgubJClkkJ0VZmY74SS/4a8Zbew=; b=m3EhPViPlCIfRWHF+42zfB1Tm3SHJrcQmMugJroTH1SHmLN4SY3g1yrZcGUOEZTlir u0ViJ7JBZsy9KYhqpa5aUs1fzFHgTlnkY0JHAFrriYArJ79S4wGRO0qkjX+3AfdD4ASS 9WvfTqBUkqGVugVBppXBks0u5SaePXNa3RtimlhvhKz+N14+RrkEIvkR6cQfy6RfVMS0 gETw7Z5QM9gGT4pAEmUYZb2YHEeiG+eoiBTCcOvAbKAYl6kvVS4oPbX6NK0NFr/6V+3t 6pYIhM+ygH2IfzNfF8bqXVHFtTyNkPiYpLeJ9rOivFrrd30a5xf0pHprV9Bnhnucg1XF rUjg== X-Gm-Message-State: AOJu0Yx+7n4hUgcxjwamFJRPa9Ev7PQFYPdDIcrDoEHNL92ZZkc9wN6r 3F/MT4+eLk+foTG3Z93CvyGoGb1Z+poKdpl1thKs4OhzNeMF6ko//DDxiHCyLljZflDnTJk0+Zv ljmgt+FOFw+Ald8mnbFmeKw9pXzH7Jk3XvD9Deg== X-Google-Smtp-Source: AGHT+IGvwhtkbbIHoLX/u0qbGVdvHl4Oo5vux2iRx6nUDbCsw69Zp+59ZkYkqhgaGJShh83G8X35q8AvJL2yuuQYbrU= X-Received: by 2002:a17:906:2c51:b0:a59:beb2:62d6 with SMTP id a640c23a62f3a-a622814ddd3mr268060266b.74.1716446622015; Wed, 22 May 2024 23:43:42 -0700 (PDT) MIME-Version: 1.0 References: <20240506044520.2780464-1-hau.hsu@sifive.com> <20240506044520.2780464-2-hau.hsu@sifive.com> <89C7C17E-5E9D-4E00-A3AE-FF1F014C0939@sifive.com> <6B8C7B37-CAB2-40E0-9C3F-CA8F8B37D367@sifive.com> <53B9A941-BE25-4DB5-8F65-607890181EDF@sifive.com> In-Reply-To: <53B9A941-BE25-4DB5-8F65-607890181EDF@sifive.com> From: Nelson Chu Date: Thu, 23 May 2024 14:43:30 +0800 Message-ID: Subject: Re: [PATCH 2/2] riscv: Fix R_RISCV_IRELATIVE overwrite and order issues To: Hau Hsu Cc: Binutils , Kito Cheng Content-Type: multipart/alternative; boundary="0000000000002e810d0619195f1c" X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000002e810d0619195f1c Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Your code will break what we discussed in the pr13302 - "riscv inserts the dynamic relocations in the order of plt and got entry offset" On Thu, May 23, 2024 at 11:54=E2=80=AFAM Hau Hsu wrote: > I used riscv-gnu-toolchain to run gcc test suite (linux) and got no > regressions: > > =3D=3D=3D=3D=3D=3D=3D=3D=3D Summary of gcc testsuite =3D= =3D=3D=3D=3D=3D=3D=3D=3D > | # of unexpected case / # of unique > unexpected case > | gcc | g++ | gfortran | > rv64imafdc/ lp64d/ medlow | 0 / 0 | 0 / 0 | 0 / 0 | > > > I think the quite easy solution is - don't use riscv_elf_append_rela to > emit dynamic IRELATIVE for R_RISCV_32/64 into iplt section. Seems like > commit 51a8a7c2e3cc only handles the finish_dynamic_symbol, but forgot to > apply a similar fix in the relocate_section. > > > It seems my change works. But I can try to modify code as suggested. > > > Hau Hsu > > > > > On May 17, 2024, at 10:32=E2=80=AFAM, Hau Hsu wrote: > > Let me run more toolchain integrated tests. > Thanks! > > Hau > > > > On May 16, 2024, at 4:28=E2=80=AFPM, Nelson Chu wro= te: > > I think the quite easy solution is - don't use riscv_elf_append_rela to > emit dynamic IRELATIVE for R_RISCV_32/64 into iplt section. Seems like > commit 51a8a7c2e3cc only handles the finish_dynamic_symbol, but forgot to > apply a similar fix in the relocate_section. > > https://github.com/bminor/binutils-gdb/blob/master/bfd/elfnn-riscv.c#L2408 > diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c > index 604f6de4511..dca446c0495 100644 > --- a/bfd/elfnn-riscv.c > +++ b/bfd/elfnn-riscv.c > @@ -2399,13 +2399,16 @@ riscv_elf_relocate_section (bfd *output_bfd, > 2. .rela.got section in dynamic executable. > 3. .rela.iplt section in static executable. */ > if (bfd_link_pic (info)) > - sreloc =3D htab->elf.irelifunc; > + riscv_elf_append_rela (output_bfd, > htab->elf.irelifunc, &outrel); > else if (htab->elf.splt !=3D NULL) > - sreloc =3D htab->elf.srelgot; > + riscv_elf_append_rela (output_bfd, > htab->elf.srelgot, &outrel); > else > - sreloc =3D htab->elf.irelplt; > - > - riscv_elf_append_rela (output_bfd, sreloc, &outrel); > + { > + const struct elf_backend_data *bed =3D > get_elf_backend_data (output_bfd); > + bfd_vma iplt_idx =3D htab->last_iplt_index--; > + bfd_byte *loc =3D htab->elf.irelplt->contents + > iplt_idx * sizeof (ElfNN_External_Rela); > + bed->s->swap_reloca_out (output_bfd, &outrel, loc= ); > + } > > /* If this reloc is against an external symbol, we > do not want to fiddle with the addend. Otherwise, > > The above changes seem to fix the testcase you provided, but without > testing fully riscv-gnu-toolchain regressions. > Or we should find a way to handle reloc_index for iplt, and all use > riscv_elf_append_rela to emit the dynamic relocation. > > Nelson > > On Thu, May 16, 2024 at 3:30=E2=80=AFPM Hau Hsu wrot= e: > >> >> On May 16, 2024, at 3:07=E2=80=AFPM, Nelson Chu wr= ote: >> >> On Thu, May 16, 2024 at 2:16=E2=80=AFPM Hau Hsu wro= te: >> >>> Hi Nelson, >>> >>> Sorry for the late reply. >>> >>> On May 8, 2024, at 9:00=E2=80=AFAM, Nelson Chu wr= ote: >>> >>> Can you provide the testcase to show the case which I mentioned in the >>> pr13302? Which is that an ifunc with a dynamic jump slot calls another >>> ifunc, and are not in the rel.dyn. >>> >>> I am not quite sure what's the issue you mentioned in PR13302. >>> You mean the order issue of cause by one ifunc (generates >>> JUMP_SLOT[32|64]) calls another JUMP_SLOT[32|64] ifunc? >>> >>> Since according to the testcase below, it seems no requirement to apply >>> this fix though. >>> >>> The new test case uses two methods to call ifuncs: >>> 1. Through a normal function call: PLT + GOT >>> 2. Through a global function pointer: GOT only >>> >>> Without the fix, the relocation of the first method overwrites the >>> second's. >>> The relocation section of my test case would be: >>> >>> Relocation section '.rela.plt' at offset 0x94 contains 2 entries: >>> Offset Info Type Sym. Value Symbol's Name + >>> Addend >>> 000110dc 0000003a R_RISCV_IRELATIVE 100c0 >>> 00000000 00000000 R_RISCV_NONE 0 >>> >>> >>> With the fix, it becomes >>> >>> Relocation section '.rela.plt' at offset 0x94 contains 2 entries: >>> Offset Info Type Sym. Value Symbol's Name + >>> Addend >>> 000110e0 0000003a R_RISCV_IRELATIVE 100c0 >>> 000110dc 0000003a R_RISCV_IRELATIVE 100c0 >>> >>> >> So it seems like the overwrite problem, not the order problem we were >> discussing in the pr13302... >> >> >> Yes. Sorry that I didn't explain the whole story well. >> >> This PR is originally to fix the overwrite problem, as my commit message >> says: >> > This commit resolved two issues: >> > 1. When an ifunc is referenced by a pointer, the relocation of >> > the pointer in .rela.plt would be overwritten by normal ifunc call. >> We found the issue when building glibc testbench statically. >> >> To fix this issue, I sent a PR ( >> https://sourceware.org/pipermail/binutils/2023-July/128485.html) about a >> year ago. >> The PR use the method smilier to your previous commit, i.e. >> >> https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dcommit;h=3D51a8a7c2= e3cc0730831963651a55d23d1fae624d >> Then you suggested to check whether the relocation order is correct. >> After that I checked the X86 implementation, I sent this PR. >> >> >> >>> --- /dev/null >>>> +++ b/ld/testsuite/ld-riscv-elf/ifunc-macro.s >>>> @@ -0,0 +1,19 @@ >>>> +/* Define macros to handle similar behaviors for rv32/rv64. >>>> + Assumes macro "__64_bit__" defined for rv64. >>>> + The macro is specifically defined for ifunc tests in >>>> ld-riscv-elf.exp. */ >>>> + >>>> +.macro PTR_DATA name >>>> +.ifdef __64_bit__ >>>> + .quad \name >>>> +.else >>>> + .long \name >>>> +.endif >>>> +.endm >>>> + >>>> +.macro LOAD rd, rs, offset >>>> +.ifdef __64_bit__ >>>> + ld \rd, \offset (\rs) >>>> +.else >>>> + lw \rd, \offset (\rs) >>>> +.endif >>>> +.endm >>> >>> >> Btw, can we not use these macroes? >> >> >> No problem. I just want to avoid similar codes in the ifunc tests. >> >> >> Nelson >> >> >> > > --0000000000002e810d0619195f1c--