From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x2a.google.com (mail-oa1-x2a.google.com [IPv6:2001:4860:4864:20::2a]) by sourceware.org (Postfix) with ESMTPS id 926CC3858C56 for ; Fri, 14 Oct 2022 01:37:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 926CC3858C56 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-136b5dd6655so4369885fac.3 for ; Thu, 13 Oct 2022 18:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=yjfhYwaqo3QR0Ct9acSIF2ZUTFdg/qRFThjPMp5vBBw=; b=trhhRZrzeFwjvhgBFSjR7g+c8yU1aeLEyOnU60idBNe9Ea7LaiQxznTHpVUDeg4l3U wqU256u+XBiYaE86l1+wz7Y3zkrY6M5RIiPDiWLGWEKvGajc6VM0OtLVCvzu5C48cf+9 8CYKPo0VRpcCZpbfnmsTSZe2UijL9XUOZ/puHcgOwGLyxBGwZCXJLehOF0jnhTU2sEAT dDGnz2qPIU6lgDoEvvgTZ0A7hFbQFjUFJxGvX4P0NTM5gpoctPrKuYaIF3ADmg2H/MTy y8HBvPf6aMQF89ZZqN1lh5KjnCUkcJUshbNhQ1dKYYAEyO/UthXP4vzySjt937u291j0 rcfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=yjfhYwaqo3QR0Ct9acSIF2ZUTFdg/qRFThjPMp5vBBw=; b=XAw7rK1DIUPqKY+zGxXig5VHE6kOfs/1rF4o1b9kePsvlcLX3xA9DwHSYEmHtrgRiD JUxwMTHLPNS33y/RxtJyHFtQdvOTi1oHOsTCDGKKIkXMKHt1gstq4VbJiPcTyvUxqkHh PuDiF1W4CzaVNncl3GxyY7AId2cuCk4dfigE0GPzYaSG1L9eo6Dhw347DxYe9eqQBU+3 cPe7ZgI2k0qkk7Hl0dD1YEaEennmMKSgqdpUs4zresTQtQ+OaOEHAhsz2YQMby6wKNe1 Whst2i6M9hX5G4b+ZuLroiTjrww98dXAPX1Kg3GuKlZI7cQHqFgtPwzMfEsUsZ/hEe4r UwHQ== X-Gm-Message-State: ACrzQf3L1PIsK6m3rP/Eqj2LPeqH8ZCGICKj2MwhAHIa5+D1lmlebWab D+aedpLJk2ZeuYY4/K1A2hNY1/vGRa5Ht1VRuc6P+I6kuduE8w== X-Google-Smtp-Source: AMsMyM6/uj9X39Qidr9Qj1itYpmwEV7Do2gqbW4CHvmjR/iWWpCqgrzDP4p8YhFp105rT3dRCySHrPxVdrHNdpnc9/g= X-Received: by 2002:a05:6870:507:b0:130:ae8d:db0e with SMTP id j7-20020a056870050700b00130ae8ddb0emr7237457oao.82.1665711459006; Thu, 13 Oct 2022 18:37:39 -0700 (PDT) MIME-Version: 1.0 References: <0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com> In-Reply-To: <0883001b3572e54d3fba264429c7ade2adb66610.1665203441.git.research_trasio@irq.a4lg.com> From: Nelson Chu Date: Fri, 14 Oct 2022 09:37:28 +0800 Message-ID: Subject: Re: [PATCH 1/1] RISC-V: Move standard hints before all instructions To: Tsukasa OI Cc: binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, Oct 8, 2022 at 12:32 PM Tsukasa OI via Binutils wrote: > > Because all standard hints must be placed before corresponding instruction > for the disassembler, they may taint basic RVI instruction section. > > This commit moves all standard hints before all basic RVI instructions > to improve maintainability. OK, improving maintainability makes sense and the reason is enough to me, please commit. Thanks Nelson > opcodes/ChangeLog: > > * riscv-opc.c (riscv_opcodes): Move all standard hints before all > standard instructions. > --- > opcodes/riscv-opc.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 11bb87d7eaa..4827aad9351 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -298,6 +298,14 @@ match_th_load_pair(const struct riscv_opcode *op, > const struct riscv_opcode riscv_opcodes[] = > { > /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ > + > +/* Standard hints. */ > +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > +{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, > + > +/* Basic RVI instructions and aliases. */ > {"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS }, > {"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW|(CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ > {"ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, > @@ -417,9 +425,6 @@ const struct riscv_opcode riscv_opcodes[] = > {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, > {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, > {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, > -{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > -{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > -{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > {"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, > {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, > {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, > @@ -446,7 +451,6 @@ const struct riscv_opcode riscv_opcodes[] = > {"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, > {"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, > {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, > -{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "",MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, > {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, > {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, > {"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 }, > -- > 2.34.1 >