From: Nelson Chu <nelson@rivosinc.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [PATCH v2 0/1] RISC-V psABI: Add testcase for DWARF register numbers (supplemental)
Date: Fri, 14 Oct 2022 09:33:02 +0800 [thread overview]
Message-ID: <CAPpQWtD_1fk+0eY+HjLnVx6y=g1j4dON2qQoTyRPO9u0enN3Vw@mail.gmail.com> (raw)
In-Reply-To: <cover.1665203374.git.research_trasio@irq.a4lg.com>
OK, please commit.
Thanks
Nelson
On Sat, Oct 8, 2022 at 12:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Hello,
>
> This is a supplement to my previous patchset and tests DWARF register number
> of "fp" (x8 or "s0").
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (1):
> RISC-V: Test DWARF register numbers for "fp"
>
> gas/testsuite/gas/riscv/dw-regnums.d | 1 +
> gas/testsuite/gas/riscv/dw-regnums.s | 3 +++
> 2 files changed, 4 insertions(+)
>
>
> base-commit: 4cbfd0daabd68516651ee37a19d0e24ca4789ea3
> --
> 2.34.1
>
prev parent reply other threads:[~2022-10-14 1:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 8:41 [PATCH 0/1] RISC-V psABI: Add testcase for DWARF register numbers Tsukasa OI
2022-09-23 8:41 ` [PATCH 1/1] RISC-V: " Tsukasa OI
2022-10-08 4:29 ` [PATCH v2 0/1] RISC-V psABI: Add testcase for DWARF register numbers (supplemental) Tsukasa OI
2022-10-08 4:29 ` [PATCH v2 1/1] RISC-V: Test DWARF register numbers for "fp" Tsukasa OI
2022-10-14 1:33 ` Nelson Chu [this message]
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