From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc35.google.com (mail-oo1-xc35.google.com [IPv6:2607:f8b0:4864:20::c35]) by sourceware.org (Postfix) with ESMTPS id CFAE63858D35 for ; Thu, 7 Sep 2023 04:49:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CFAE63858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oo1-xc35.google.com with SMTP id 006d021491bc7-5739965a482so280696eaf.0 for ; Wed, 06 Sep 2023 21:49:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694062180; x=1694666980; darn=sourceware.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=C/LAs6iefISWKeztDIHYP36rzVF9wHzl2bql5B+2tSM=; b=RqYGO2gXSfiVXbzpf3W7wPky1ZRDNpqymZdV6XdK3bD61ap6aydrZcQppwuLvRoJuA sFXbEjrbRIcE+eXNAB716SYSW+VtunS2ClvDEplIRthn/hewztVYzRXTI4md1dewCeQs vzKLGyoRyIyFIKI6HR27ZRxAXG4wzvNLyvsXz4ov/EjZPUOphcQ+FKkOsT0/sEBFm91/ I8VM8j2JQzvqrpdwZdooYKRpervcD7qWIGQNXWH2pPLZFdrWvAnu4JZ/ei7HkpB5sK/P jjwJi/nDxbEBOaIFPFJGWI6Sp9RJNAhkaQJ0PcCQ6bLGsTiv89lVYGurNJDlbChczPhq Fkjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694062180; x=1694666980; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=C/LAs6iefISWKeztDIHYP36rzVF9wHzl2bql5B+2tSM=; b=Fhs6faaal0XKPJPGKGST6L6qvXEZmRDXd53GAUbNmLH47fJ92CenaMrEKx7povkYZV 0I/nKnYOQsUtB0kfH4DxeAYjZ+uOnWYc7i/tvtO3++XCPgsa3AO/vWhFjBp7mZF5NASP Kc48H5tclEnhqKH85vT5iNmNaYPwV3Cv7psVdIw9do+bbI5JSOJcim/I3d8apfxKkOAa Er6tNXLhDwB203K2RJruJ6X6E/OqqKvcMV4k6sBaX3nO2O5bkykTqpDvQ0uGrX7kM5s2 eeEAqt0om58p75vXxaFvwMLkRs9uCgfftZaMYuYbXUch3YAXpSw507Rl57CXJI736qnP M4Iw== X-Gm-Message-State: AOJu0YxjxE4vrBdo2tQH234XGdnN1Hijd0BmVg658Ox9vDloI/SbH9K1 WvaRoup2glGh+wM97zaD8TVi3CnMVepQEwpYCFSOMQ== X-Google-Smtp-Source: AGHT+IFdtZXMnvr3mFSzwSfSpB4wyNMJx6se8gPfzu0Uf6oMo2R5rqS1Fs4rnE8/5LSVhBtizZyKCrVkZWwFaVjRO80= X-Received: by 2002:a4a:d004:0:b0:56c:a9fe:f701 with SMTP id h4-20020a4ad004000000b0056ca9fef701mr1201003oor.3.1694062180102; Wed, 06 Sep 2023 21:49:40 -0700 (PDT) MIME-Version: 1.0 References: <20230905145300.652455-1-mary.bennett@embecosm.com> In-Reply-To: <20230905145300.652455-1-mary.bennett@embecosm.com> From: Nelson Chu Date: Thu, 7 Sep 2023 12:49:29 +0800 Message-ID: Subject: Re: [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions To: Mary Bennett Cc: binutils@sourceware.org, Jim Wilson , Jeff Law , Kito Cheng , Palmer Dabbelt , Andrew Waterman Content-Type: multipart/alternative; boundary="0000000000007906f00604bd96ba" X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000007906f00604bd96ba Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Mary, Thanks for the contribution, the vendor core-v extensions in binutils look good to me :-) Hi Jeff, Kito, Palmer and Andrew, I am not sure if we are likely to accept the vendor core-v extension only in binutils first? Or if we prefer to accept it with the whole toolchain support, including gcc and qemu. Need your help, thanks! If I forgot to cc anyone who may be related, please feel free to add them in the discussion! Nelson On Tue, Sep 5, 2023 at 10:53=E2=80=AFPM Mary Bennett wrote: > This patch series presents the comprehensive implementation of the MAC and > ALU > extension for CORE-V. > > Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to > ensure its correctness and compatibility with the existing codebase. > However, your input, reviews, and suggestions are invaluable in making th= is > extension even more robust. > > The CORE-V instructions are described in the specification [1] and work > can be > found in the OpenHW group's Github repository [2]. > > [1] > docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_= set_extensions.html > > [2] github.com/openhwgroup/corev-binutils-gdb > > Contributors: > Mary Bennett > Nandni Jamnadas > Pietra Ferreira > Charlie Keaney > Jessica Mills > Craig Blackmore > Simon Cook > Jeremy Bennett > > RISC-V: Add support for XCValu extension in CV32E40P > RISC-V: Add support for XCVmac extension in CV32E40P > > bfd/elfxx-riscv.c | 11 ++ > gas/config/tc-riscv.c | 60 +++++++ > gas/doc/c-riscv.texi | 10 ++ > gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 + > gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++ > gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++ > gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 + > gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++ > gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++ > .../gas/riscv/cv-alu-fail-operand-01.d | 3 + > .../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++ > .../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++ > .../gas/riscv/cv-alu-fail-operand-02.d | 3 + > .../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++ > .../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++ > .../gas/riscv/cv-alu-fail-operand-03.d | 3 + > .../gas/riscv/cv-alu-fail-operand-03.l | 25 +++ > .../gas/riscv/cv-alu-fail-operand-03.s | 26 +++ > .../gas/riscv/cv-alu-fail-operand-04.d | 3 + > .../gas/riscv/cv-alu-fail-operand-04.l | 3 + > .../gas/riscv/cv-alu-fail-operand-04.s | 4 + > .../gas/riscv/cv-alu-fail-operand-05.d | 3 + > .../gas/riscv/cv-alu-fail-operand-05.l | 9 + > .../gas/riscv/cv-alu-fail-operand-05.s | 10 ++ > .../gas/riscv/cv-alu-fail-operand-06.d | 3 + > .../gas/riscv/cv-alu-fail-operand-06.l | 9 + > .../gas/riscv/cv-alu-fail-operand-06.s | 10 ++ > .../gas/riscv/cv-alu-fail-operand-07.d | 3 + > .../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++ > .../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++ > gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++ > gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++ > gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 + > gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++ > gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++ > gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 + > gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++ > gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++ > gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++ > gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++ > include/opcode/riscv-opc.h | 56 +++++++ > include/opcode/riscv.h | 12 ++ > opcodes/riscv-dis.c | 20 +++ > opcodes/riscv-opc.c | 61 +++++++ > 44 files changed, 1406 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l > create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s > create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d > create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l > create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s > create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d > create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s > > -- > 2.34.1 > > --0000000000007906f00604bd96ba--