From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) by sourceware.org (Postfix) with ESMTPS id 2372D3858C56 for ; Fri, 14 Oct 2022 03:10:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2372D3858C56 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oi1-x22c.google.com with SMTP id w196so3797701oiw.8 for ; Thu, 13 Oct 2022 20:10:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=JgSewjrMEm+c1daQRIkebU6UnDK90qZqmzjM3CsGeF4=; b=DsEPyRFLykRfT0yySwT72tLrwBxCKo3LkMsQelj/FFsZJxfSqrWRUSF8UWYLICQra7 M1Tq6OVBROAovz7XFsE+f+0PfCnTUZoZKuwPm9NFr9OSK06YS4zwpmUKaQMJQbX6oGgg uPhFU9M7HOo3wuTy0cemKyicpQqgyNlJaBQ9bbyuDh4Asn4h82zwYCTaEPvFQX4FVQoX 1yxv2vPQAxnxcmbImkgbJbrtLCWluqT9NllPYT2q8rNGJwKsJtKgDyz8kT7CNSnmNwST xYD7MsnJPyGVo/NTtNhHgh5nLX1duZg/L+dzG5jchfuqabmGXso7G+Is+YqXSCMrAi6X e+6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=JgSewjrMEm+c1daQRIkebU6UnDK90qZqmzjM3CsGeF4=; b=yr1nMawlFnBZOktZuQNjtxVourDyCjek4v5C02G3L0Pw/HtdBMuNDKovrWRHW/vFPg 5hTMimaISyFg5yiBYbeto5SIip3W7d+J4SAHmyWadFTkOXPbY84TvaNCDAQU3T0Ce2SC 6+OmNKAI8wjyW+iF+zqHUgWSe8yPWXSB34wB/kUVfC1BSXFcV5jnRAzw2dv+z5P9EAj8 S6i1/EeSEjkDTxGoT33K/ew4/wYaigMtrA88ySfeqAt+trxnVnp/ZflOtScJ9IJ4KqGw KlDMuX8Br9yKxrqUCJRY1Ghgjta2wQcH+Gw5nt7Y9D9wDkxsXhZKtINxhBWKVzIUni03 SV8Q== X-Gm-Message-State: ACrzQf2B/RD+rOacVosyuiVXFlhYntwe8RHbt+8Al3tWQESJVJwkrG2i Oz3BYlSV1O99cj8bJoN046Xw0e2aY1v/+zceAbk06A== X-Google-Smtp-Source: AMsMyM5qQCUT0nypLApmZofMxka1R/vWxoWEKXQXSlAEbdiasaVFRo9vATjiY7YUu+YV66OBM+tR2VFgK61reMO1z1A= X-Received: by 2002:a05:6808:bca:b0:350:b22b:1283 with SMTP id o10-20020a0568080bca00b00350b22b1283mr6351214oik.82.1665717007533; Thu, 13 Oct 2022 20:10:07 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Nelson Chu Date: Fri, 14 Oct 2022 11:09:56 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Move certain arrays to riscv-opc.c To: Tsukasa OI Cc: Kito Cheng , Palmer Dabbelt , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: OK, test cases passed, please commit. Thanks Nelson On Sun, Oct 9, 2022 at 1:09 PM Tsukasa OI wrote: > > This is a part of small tidying (declare tables in riscv-opc.c). > > include/ChangeLog: > > * opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to > opcodes/riscv-opc.c. New non-static definitions. > > opcodes/ChangeLog: > > * riscv-opc.c (riscv_rm, riscv_pred_succ): Move from > include/opcode/riscv.h. Add description. > --- > include/opcode/riscv.h | 13 ++----------- > opcodes/riscv-opc.c | 13 +++++++++++++ > 2 files changed, 15 insertions(+), 11 deletions(-) > > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index f173a2eca25..dddabfdd415 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -46,17 +46,6 @@ static inline unsigned int riscv_insn_length (insn_t insn) > return 2; > } > > -static const char * const riscv_rm[8] = > -{ > - "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" > -}; > - > -static const char * const riscv_pred_succ[16] = > -{ > - 0, "w", "r", "rw", "o", "ow", "or", "orw", > - "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" > -}; > - > #define RVC_JUMP_BITS 11 > #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) > > @@ -555,6 +544,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR]; > extern const char * const riscv_gpr_names_abi[NGPR]; > extern const char * const riscv_fpr_names_numeric[NFPR]; > extern const char * const riscv_fpr_names_abi[NFPR]; > +extern const char * const riscv_rm[8]; > +extern const char * const riscv_pred_succ[16]; > extern const char * const riscv_vecr_names_numeric[NVECR]; > extern const char * const riscv_vecm_names_numeric[NVECM]; > extern const char * const riscv_vsew[8]; > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 11bb87d7eaa..04acc8470be 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -58,6 +58,19 @@ const char * const riscv_fpr_names_abi[NFPR] = > "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" > }; > > +/* Rounding modes. */ > +const char * const riscv_rm[8] = > +{ > + "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" > +}; > + > +/* FENCE: predecessor/successor sets. */ > +const char * const riscv_pred_succ[16] = > +{ > + 0, "w", "r", "rw", "o", "ow", "or", "orw", > + "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" > +}; > + > /* RVV registers. */ > const char * const riscv_vecr_names_numeric[NVECR] = > { > > base-commit: c10a862f17847bc9c50d680c87b87dc51ae4b95e > -- > 2.34.1 >