From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id A6ED43858D29 for ; Tue, 11 Jun 2024 04:56:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A6ED43858D29 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A6ED43858D29 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::630 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718081803; cv=none; b=n2kmC97ZLOcWZfUVeFiT1SUoTvFd1+7P+Y/qg0AEbJQ2B1XTTMrA5hEXMgms+T5K3ixXoaewz5ZsMG9qQjE0Xd6e1VKNXFDs2hWD+h/nGeG7nk9uWwTwJKXR1wKld8Js6GW3jvGnzv/80B0KFr7xQ9ixiZMKYpE0fvP3ea5djWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718081803; c=relaxed/simple; bh=pMda3snQC+K4w5hhpwT+54yag9FBz+nC9IjNHiUD4bk=; h=DKIM-Signature:From:Message-Id:Mime-Version:Subject:Date:To; b=rne0wLZfYzAe3DEUITUCLuN5hIlNR/lz5aNcaBbthPWjLFoflkxHm5/akpG3OnAb0CeiIQhNQrhXYYhzsQk/Sd4YZwUtA+7E4EHopH7XoUIhLIYxGqbkUuAAQ9rLIpMU/57bmQv2B6tCGKpyZAWujlr+At5qfAtLfy+f7bKhQKI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1f70131063cso4990375ad.2 for ; Mon, 10 Jun 2024 21:56:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718081799; x=1718686599; darn=sourceware.org; h=references:to:cc:in-reply-to:date:subject:mime-version:message-id :from:from:to:cc:subject:date:message-id:reply-to; bh=akTco99FYxG86DHovJZk8SPhQLXWs8d/BBOYavCamcE=; b=OAbjLaIiNzdCkCYjmNxKHMtGTRoi54IrN2EKX6Pdor4IznuytQqnhCHRBvLYCxurML Z+aa3d/T0YA3uAW5cTMk4znCLjI45hIegGNOTi0/wnTIOf44JuzowG4f2y5iBF22889H 2qCo41om+3N9yAf9MLykP7YLMIwkPavEEjPe9T8kShpDGyPsgFTKYo2eSCSCnJZCbx93 13B8yJI+AwW7iBAGuIYeDHhydTAwoPR1rb7xNnA1hg6yBhXQghjBtywkuEdKx0biO3B4 evKHoOof/fBsVAAWSUPEULCXIpTIdtBOF9QifDUTuml3HAQ1sEmbJX4dT1EMRpBiKVJ0 cGJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718081799; x=1718686599; h=references:to:cc:in-reply-to:date:subject:mime-version:message-id :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=akTco99FYxG86DHovJZk8SPhQLXWs8d/BBOYavCamcE=; b=CKZ60s8bUEdZui+M4rvsNZhBFbbBaMO/Xa/jF9TEfIgXSEvAQKLDl0Nw69WwKH9Yma +R5byZ01y0xFKlMdrAFvWCrD0rmSoZe6WyNGTQJ68xL7AdX65L4LMtReM/qCr2UI3i7w DOZjJ8srgAT7+Fpp2o2R9SSrJKmb6XUOsi42no4XIMFCnbL46xs/nIv/44feea7sbN5v jOmtWDw0SAl4jg44JBbFQ2ilrqEEVaQCy4E0h9Vl58sf3jnBHeg0eWaCJMuriUX8Ub/w HOR5lOUYpi6ZOV3Gt9C7jgpukUHSLeZuPKJIh4MKGWDTdOoujU7Rnv6cSahpuBj5zKsz KFVQ== X-Gm-Message-State: AOJu0Yz+I0hwu1jwh8ps9KA/6fPYOzqE2zmNeTslX1fGZFT0ZDTsUGC3 t6XTWz1CzSOs3ADWzCg83npJC/HjsF+jYF4AMcPyDWXz0eQRH2Ai1dvn8Z8FcljPO0m+oTK7fPN wOMs= X-Google-Smtp-Source: AGHT+IFQb9ALwSS5JwgJYjN2mEYZjkcUfzBjBorb8/8hnN5Tabjpd5ZtWgfIN6sEaXRR19lRFQYsbg== X-Received: by 2002:a17:903:2448:b0:1f7:3170:5b7 with SMTP id d9443c01a7336-1f7317007fdmr6013265ad.51.1718081799385; Mon, 10 Jun 2024 21:56:39 -0700 (PDT) Received: from smtpclient.apple ([136.226.240.173]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f7346f0537sm2492175ad.305.2024.06.10.21.56.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Jun 2024 21:56:39 -0700 (PDT) From: Hau Hsu Message-Id: Content-Type: multipart/alternative; boundary="Apple-Mail=_542D0B57-54F4-4F92-A9BE-B4F37F8DC0A4" Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.400.31\)) Subject: Re: [PATCH] RISC-V: Add SiFive cease extension v1.0 Date: Tue, 11 Jun 2024 12:56:26 +0800 In-Reply-To: Cc: Binutils , kito.cheng@gmail.com To: Nelson Chu References: <20240521074146.3514252-1-hau.hsu@sifive.com> X-Mailer: Apple Mail (2.3774.400.31) X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --Apple-Mail=_542D0B57-54F4-4F92-A9BE-B4F37F8DC0A4 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 Hi Nelson, Thanks for reviewing. I have updated v2 that adds ChangeLogs and removed the accident change in gas/testsuite/gas/riscv/sifive-insns.d. Please review it again. Thanks! Best, Hau Hsu > On Jun 6, 2024, at 9:58=E2=80=AFAM, Nelson Chu wrot= e: >=20 >=20 >=20 > On Tue, May 21, 2024 at 3:46=E2=80=AFPM Hau Hsu > wrote: >> Add SiFive vender cease extension. >> This aligns LLVM: >> https://llvm.org/docs/RISCVUsage.html >=20 > It would be better if there are some ChangeLogs. >=20=20 >>=20 >> --- >> bfd/elfxx-riscv.c | 5 +++++ >> gas/testsuite/gas/riscv/march-help.l | 1 + >> gas/testsuite/gas/riscv/sifive-insns.d | 3 ++- >> gas/testsuite/gas/riscv/sifive-insns.s | 6 ++++++ >> include/opcode/riscv-opc.h | 3 +++ >> include/opcode/riscv.h | 1 + >> opcodes/riscv-opc.c | 3 +++ >> 7 files changed, 21 insertions(+), 1 deletion(-) >>=20 >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c >> index dfacb87eda0..c69a000a46e 100644 >> --- a/bfd/elfxx-riscv.c >> +++ b/bfd/elfxx-riscv.c >> @@ -1470,6 +1470,7 @@ static struct riscv_supported_ext riscv_supported_= vendor_x_ext[] =3D >> {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, >> + {"xsfcease", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {NULL, 0, 0, 0, 0} >> }; >>=20 >> @@ -2706,6 +2707,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t = *rps, >> return riscv_subset_supports (rps, "xventanacondops"); >> case INSN_CLASS_XSFVCP: >> return riscv_subset_supports (rps, "xsfvcp"); >> + case INSN_CLASS_XSFCEASE: >> + return riscv_subset_supports (rps, "xsfcease"); >> default: >> rps->error_handler >> (_("internal: unreachable INSN_CLASS_*")); >> @@ -2960,6 +2963,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subse= t_t *rps, >> return "xtheadvector"; >> case INSN_CLASS_XTHEADZVAMO: >> return "xtheadzvamo"; >> + case INSN_CLASS_XSFCEASE: >> + return _("xsfcease"); >> default: >> rps->error_handler >> (_("internal: unreachable INSN_CLASS_*")); >> diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/ri= scv/march-help.l >> index c5754837e05..b30790bb980 100644 >> --- a/gas/testsuite/gas/riscv/march-help.l >> +++ b/gas/testsuite/gas/riscv/march-help.l >> @@ -121,3 +121,4 @@ All available -march extensions for RISC-V: >> xtheadzvamo 1.0 >> xventanacondops 1.0 >> xsfvcp 1.0 >> + xsfcease 1.0 >> diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/= riscv/sifive-insns.d >> index f7d63d1bce0..ad811c328cd 100644 >> --- a/gas/testsuite/gas/riscv/sifive-insns.d >> +++ b/gas/testsuite/gas/riscv/sifive-insns.d >> @@ -33,5 +33,6 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+ac25d05b[ ]+sf.vc.v.fvv[ ]+0x1,v0,v2,fa1 >> [ ]+[0-9a-f]+:[ ]+fc20805b[ ]+sf.vc.v.vvw[ ]+0x3,v0,v2,v1 >> [ ]+[0-9a-f]+:[ ]+fc25c05b[ ]+sf.vc.v.xvw[ ]+0x3,v0,v2,a1 >> -[ ]+[0-9a-f]+:[ ]+fc27b05b[ ]+sf.vc.v.ivw[ ]+0x3,v0,v2,15 >> +[ ]+[0-9a-f]+:[ ]+fc27b05b[ ]+sf.vc.v.ivw[ ]+0x3,v0,v2,15 >=20 > What changed to it? The sf.vc.v.ivw seems to have the same encodings and= same operands. >=20=20 >> [ ]+[0-9a-f]+:[ ]+fc25d05b[ ]+sf.vc.v.fvw[ ]+0x1,v0,v2,fa1 >> +[ ]+[0-9a-f]+:[ ]+30500073[ ]+sf.cease >> diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/= riscv/sifive-insns.s >> index d593692c5c0..cdf90c1b3ba 100644 >> --- a/gas/testsuite/gas/riscv/sifive-insns.s >> +++ b/gas/testsuite/gas/riscv/sifive-insns.s >> @@ -31,3 +31,9 @@ >> sf.vc.v.ivw 0x3, v0, v2, 15 >> sf.vc.v.fvw 0x1, v0, v2, fa1 >> .option pop >> + >> + # xscease >> + .option push >> + .option arch, +xsfcease1p0 >> + sf.cease >> + .option pop >> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h >> index ae14e14d427..d2d08c6526d 100644 >> --- a/include/opcode/riscv-opc.h >> +++ b/include/opcode/riscv-opc.h >> @@ -3076,6 +3076,9 @@ >> #define MASK_SF_VC_FVW 0xfa00707f >> #define MATCH_SF_VC_V_FVW 0xf800505b >> #define MASK_SF_VC_V_FVW 0xfa00707f >> +/* Vendor-specific (SiFive) cease instruction. */ >> +#define MATCH_SF_CEASE 0x30500073 >> +#define MASK_SF_CEASE 0xffffffff >> /* Unprivileged Counter/Timers CSR addresses. */ >> #define CSR_CYCLE 0xc00 >> #define CSR_TIME 0xc01 >> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h >> index 5f516a1026e..d6081caa0dd 100644 >> --- a/include/opcode/riscv.h >> +++ b/include/opcode/riscv.h >> @@ -505,6 +505,7 @@ enum riscv_insn_class >> INSN_CLASS_XTHEADZVAMO, >> INSN_CLASS_XVENTANACONDOPS, >> INSN_CLASS_XSFVCP, >> + INSN_CLASS_XSFCEASE, >> }; >>=20 >> /* This structure holds information for a particular instruction. */ >> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c >> index 1ef4eaddf4d..01ced23d657 100644 >> --- a/opcodes/riscv-opc.c >> +++ b/opcodes/riscv-opc.c >> @@ -3041,6 +3041,9 @@ const struct riscv_opcode riscv_opcodes[] =3D >> {"sf.vc.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_FVW,= MASK_SF_VC_FVW, match_opcode, 0 }, >> {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FV= W, MASK_SF_VC_V_FVW, match_opcode, 0 }, >>=20 >> +/* Vendor-specific (SiFive) cease instruction. */ >> +{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE,= match_opcode, 0 }, >> + >> /* Terminate the list. */ >> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} >> }; >> --=20 >> 2.31.1 >>=20 --Apple-Mail=_542D0B57-54F4-4F92-A9BE-B4F37F8DC0A4--