* Re: Automatic opcode table generation and gas test cases for s/390.
@ 2001-09-17 5:33 Martin Schwidefsky
0 siblings, 0 replies; 14+ messages in thread
From: Martin Schwidefsky @ 2001-09-17 5:33 UTC (permalink / raw)
To: DJ Delorie; +Cc: binutils
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>It's up to you to regenerate them and check in those changes also.
>The Changelog entry usually just says "Regenerated." for those files.
>You should also check those diffs, to make sure you don't make
>unwanted changes while regenerating.
Ok, here is a patch with the changes to opcodes/{Makefile.in,configure}:
ChangeLog for opcodes:
2001-09-17 Martin Schwidefsky <schwidefsky@de.ibm.com>
* Makefile.in: Regenerate.
* configure: Regenerate.
(See attached file: binutils-optab390-auto.diff)
blue skies,
Martin
Linux/390 Design & Development, IBM Deutschland Entwicklung GmbH
Schönaicherstr. 220, D-71032 Böblingen, Telefon: 49 - (0)7031 - 16-2247
E-Mail: schwidefsky@de.ibm.com
[-- Attachment #2: binutils-optab390-auto.diff --]
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diff -urN src/opcodes/Makefile.in src-s390/opcodes/Makefile.in
--- src/opcodes/Makefile.in Thu Jul 26 21:09:11 2001
+++ src-s390/opcodes/Makefile.in Mon Sep 17 14:11:03 2001
@@ -220,6 +220,7 @@
pj-opc.c \
ppc-dis.c \
ppc-opc.c \
+ s390-mkopc.c \
s390-opc.c \
s390-dis.c \
sh-dis.c \
@@ -816,6 +817,12 @@
ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c
+s390-mkopc: s390-mkopc.c
+ $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c
+
+s390-opc.tab: s390-mkopc s390-opc.txt
+ ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab
+
# This dependency stuff is copied from BFD.
DEP: dep.sed $(CFILES) $(HFILES) config.h
@@ -1037,7 +1044,8 @@
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h
ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/ppc.h opintl.h
-s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h
+s390-opc.lo: s390-opc.c s390-opc.tab $(INCDIR)/ansidecl.h \
+ $(INCDIR)/opcode/s390.h
s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/s390.h
sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff -urN src/opcodes/configure src-s390/opcodes/configure
--- src/opcodes/configure Fri Sep 14 22:06:58 2001
+++ src-s390/opcodes/configure Mon Sep 17 14:18:33 2001
@@ -4307,6 +4307,44 @@
. ${srcdir}/../bfd/configure.host
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test -z "$CC_FOR_BUILD"; then
+ if test "x$cross_compiling" = "xno"; then
+ CC_FOR_BUILD='$(CC)'
+ else
+ CC_FOR_BUILD=gcc
+ fi
+fi
+
+# Also set EXEEXT_FOR_BUILD.
+if test "x$cross_compiling" = "xno"; then
+ EXEEXT_FOR_BUILD='$(EXEEXT)'
+else
+ echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6
+echo "configure:4325: checking for build system executable suffix" >&5
+if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ rm -f conftest*
+ echo 'int main () { return 0; }' > conftest.c
+ bfd_cv_build_exeext=
+ ${CC_FOR_BUILD} -o conftest conftest.c 1>&5 2>&5
+ for file in conftest.*; do
+ case $file in
+ *.c | *.o | *.obj | *.ilk | *.pdb) ;;
+ *) bfd_cv_build_exeext=`echo $file | sed -e s/conftest//` ;;
+ esac
+ done
+ rm -f conftest*
+ test x"${bfd_cv_build_exeext}" = x && bfd_cv_build_exeext=no
+fi
+
+echo "$ac_t""$bfd_cv_build_exeext" 1>&6
+ EXEEXT_FOR_BUILD=""
+ test x"${bfd_cv_build_exeext}" != xno && EXEEXT_FOR_BUILD=${bfd_cv_build_exeext}
+fi
+
+
# Find a good install program. We prefer a C program (faster),
# so one script is as good as another. But avoid the broken or
@@ -4320,7 +4358,7 @@
# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
# ./install, which can be erroneously created by make from ./install.sh.
echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:4324: checking for a BSD compatible install" >&5
+echo "configure:4362: checking for a BSD compatible install" >&5
if test -z "$INSTALL"; then
if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@@ -4377,17 +4415,17 @@
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:4381: checking for $ac_hdr" >&5
+echo "configure:4419: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 4386 "configure"
+#line 4424 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:4391: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4429: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@@ -4788,6 +4826,8 @@
s%@GT_YES@%$GT_YES%g
s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g
s%@l@%$l%g
+s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g
+s%@EXEEXT_FOR_BUILD@%$EXEEXT_FOR_BUILD%g
s%@HDEFINES@%$HDEFINES%g
s%@CGEN_MAINT_TRUE@%$CGEN_MAINT_TRUE%g
s%@CGEN_MAINT_FALSE@%$CGEN_MAINT_FALSE%g
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
2001-09-14 15:21 Martin Schwidefsky
2001-09-14 15:38 ` DJ Delorie
@ 2001-09-18 8:55 ` Nick Clifton
1 sibling, 0 replies; 14+ messages in thread
From: Nick Clifton @ 2001-09-18 8:55 UTC (permalink / raw)
To: Martin Schwidefsky; +Cc: DJ Delorie, binutils
Hi Martin,
> ChangeLog for gas:
>
> 2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
>
> * tc-s390.c (s390_insn): Add code to cope with 6 byte O_constants
> in 64 bit mode and make format "e" work.
>
> ChangeLog for opcodes:
>
> 2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
>
> * Makefile.am: Add rules and dependencies to create the s/390 opcode
> table out of s390-opc.txt automatically.
> * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used.
> * s390-mkopc.c (dumpTable): Change output to create a complete file.
> * s390-opc.c: New improved opcode format macros and remove the
> pregenerated opcode table.
> * s390-opc.txt: Adapt to new improved opcode format macros.
>
> ChangeLog for gas/testsuite:
>
> 2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
>
> * gas/s390/opcode.d: New file.
> * gas/s390/opcode.s: New file.
> * gas/s390/opcode64.d: New file.
> * gas/s390/opcode64.s: New file.
> * gas/s390/operands.d: New file.
> * gas/s390/operands.s: New file.
> * gas/s390/operands64.d: New file.
> * gas/s390/operands64.s: New file.
> * gas/s390/reloc.d: New file.
> * gas/s390/reloc.s: New file.
> * gas/s390/reloc64.d: New file.
> * gas/s390/reloc64.s: New file.
> * gas/s390/s390.exp: New file.
Approved and applied.
Cheers
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
2001-09-14 15:21 Martin Schwidefsky
@ 2001-09-14 15:38 ` DJ Delorie
2001-09-18 8:55 ` Nick Clifton
1 sibling, 0 replies; 14+ messages in thread
From: DJ Delorie @ 2001-09-14 15:38 UTC (permalink / raw)
To: schwidefsky; +Cc: binutils
> I haven't changed any files that are generated by autoconf or automake.=
>
> The optab patch won't work until these files are recreated.
It's up to you to regenerate them and check in those changes also.
The Changelog entry usually just says "Regenerated." for those files.
You should also check those diffs, to make sure you don't make
unwanted changes while regenerating.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
@ 2001-09-14 15:21 Martin Schwidefsky
2001-09-14 15:38 ` DJ Delorie
2001-09-18 8:55 ` Nick Clifton
0 siblings, 2 replies; 14+ messages in thread
From: Martin Schwidefsky @ 2001-09-14 15:21 UTC (permalink / raw)
To: DJ Delorie; +Cc: binutils
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
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>That looks OK to me. Don't forget the ChangeLog entry, and review the
>diffs for configure to make sure you aren't making spurious changes
>due to autoconf version drift, post the final patch with the other
>changes, and I'll re-review it. Whew.
Ok, here is the second try:
ChangeLog for gas:
2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
* tc-s390.c (s390_insn): Add code to cope with 6 byte O_constants
in 64 bit mode and make format "e" work.
ChangeLog for opcodes:
2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
* Makefile.am: Add rules and dependencies to create the s/390 opcode
table out of s390-opc.txt automatically.
* configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used.
* s390-mkopc.c (dumpTable): Change output to create a complete file.
* s390-opc.c: New improved opcode format macros and remove the
pregenerated opcode table.
* s390-opc.txt: Adapt to new improved opcode format macros.
(See attached file: binutils-optab390.diff)
ChangeLog for gas/testsuite:
2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
* gas/s390/opcode.d: New file.
* gas/s390/opcode.s: New file.
* gas/s390/opcode64.d: New file.
* gas/s390/opcode64.s: New file.
* gas/s390/operands.d: New file.
* gas/s390/operands.s: New file.
* gas/s390/operands64.d: New file.
* gas/s390/operands64.s: New file.
* gas/s390/reloc.d: New file.
* gas/s390/reloc.s: New file.
* gas/s390/reloc64.d: New file.
* gas/s390/reloc64.s: New file.
* gas/s390/s390.exp: New file.
(See attached file: binutils-test390.diff)
I haven't changed any files that are generated by autoconf or automake.
The optab patch won't work until these files are recreated.
I hope thats it. And thanks DJ for your help.
blue skies,
Martin
Linux/390 Design & Development, IBM Deutschland Entwicklung GmbH
Schönaicherstr. 220, D-71032 Böblingen, Telefon: 49 - (0)7031 - 16-2247
E-Mail: schwidefsky@de.ibm.com
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diff -urN src/gas/config/tc-s390.c src-s390/gas/config/tc-s390.c
--- src/gas/config/tc-s390.c Fri Sep 14 15:57:42 2001
+++ src-s390/gas/config/tc-s390.c Fri Sep 14 23:24:39 2001
@@ -1354,8 +1354,9 @@
expression (&exp);
if (exp.X_op == O_constant)
{
- if (opformat->oplen == 4 ||
- (opformat->oplen == 2 && exp.X_op < 0x10000))
+ if ((opformat->oplen == 6 && exp.X_op > 0 && exp.X_op < (1ULL << 48)) ||
+ (opformat->oplen == 4 && exp.X_op > 0 && exp.X_op < (1ULL << 32)) ||
+ (opformat->oplen == 2 && exp.X_op > 0 && exp.X_op < (1ULL << 16)))
md_number_to_chars (insn, exp.X_add_number, opformat->oplen);
else
as_bad (_("Invalid .insn format\n"));
@@ -1375,12 +1376,14 @@
}
else
as_bad (_("second operand of .insn not a constant\n"));
- if (*input_line_pointer++ != ',')
- as_bad (_("missing comma after insn constant\n"));
+ if (strcmp(opformat->name, "e") != 0 && *input_line_pointer++ != ',')
+ as_bad (_("missing comma after insn constant\n"));
+
if ((s = strchr (input_line_pointer, '\n')) != NULL)
*s = '\0';
- input_line_pointer = md_gather_operands (input_line_pointer, insn, opformat);
+ input_line_pointer = md_gather_operands (input_line_pointer, insn,
+ opformat);
if (s != NULL)
*s = '\n';
demand_empty_rest_of_line ();
diff -urN src/opcodes/Makefile.am src-s390/opcodes/Makefile.am
--- src/opcodes/Makefile.am Thu Jul 26 21:09:11 2001
+++ src-s390/opcodes/Makefile.am Fri Sep 14 23:25:46 2001
@@ -109,6 +109,7 @@
pj-opc.c \
ppc-dis.c \
ppc-opc.c \
+ s390-mkopc.c \
s390-opc.c \
s390-dis.c \
sh-dis.c \
@@ -305,6 +306,12 @@
ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c
+s390-mkopc: s390-mkopc.c
+ $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c
+
+s390-opc.tab: s390-mkopc s390-opc.txt
+ ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab
+
# This dependency stuff is copied from BFD.
DEP: dep.sed $(CFILES) $(HFILES) config.h
@@ -526,7 +533,8 @@
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h
ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/ppc.h opintl.h
-s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h
+s390-opc.lo: s390-opc.c s390-opc.tab $(INCDIR)/ansidecl.h \
+ $(INCDIR)/opcode/s390.h
s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/s390.h
sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff -urN src/opcodes/configure.in src-s390/opcodes/configure.in
--- src/opcodes/configure.in Fri Sep 14 22:26:35 2001
+++ src-s390/opcodes/configure.in Fri Sep 14 23:25:05 2001
@@ -82,6 +82,8 @@
. ${srcdir}/../bfd/configure.host
+BFD_CC_FOR_BUILD
+
AC_SUBST(HDEFINES)
AC_PROG_INSTALL
diff -urN src/opcodes/s390-mkopc.c src-s390/opcodes/s390-mkopc.c
--- src/opcodes/s390-mkopc.c Thu Mar 15 11:50:43 2001
+++ src-s390/opcodes/s390-mkopc.c Fri Sep 14 23:24:39 2001
@@ -99,6 +99,18 @@
no_ops++;
}
+static char file_header[] =
+ "/* The opcode table. This file was generated by s390-mkopc.\n\n"
+ " The format of the opcode table is:\n\n"
+ " NAME OPCODE MASK OPERANDS\n\n"
+ " Name is the name of the instruction.\n"
+ " OPCODE is the instruction opcode.\n"
+ " MASK is the opcode mask; this is used to tell the disassembler\n"
+ " which bits in the actual opcode must match OPCODE.\n"
+ " OPERANDS is the list of operands.\n\n"
+ " The disassembler reads the table in order and prints the first\n"
+ " instruction which matches. */\n\n"
+ "const struct s390_opcode s390_opcodes[] =\n {\n";
/*
* `dumpTable': write opcode table
@@ -110,7 +122,7 @@
int ix;
/* Write hash table entries (slots). */
- printf("const struct s390_opcode s390_opcodes[] = {\n");
+ printf(file_header);
for (ix = 0; ix < no_ops; ix++) {
printf(" { \"%s\", ", op_array[ix].mnemonic);
for (str = op_array[ix].opcode; *str != 0; str++)
diff -urN src/opcodes/s390-opc.c src-s390/opcodes/s390-opc.c
--- src/opcodes/s390-opc.c Fri Sep 14 16:00:09 2001
+++ src-s390/opcodes/s390-opc.c Fri Sep 14 23:24:39 2001
@@ -137,857 +137,182 @@
#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
(x >> 16) & 255, (x >> 8) & 255, x & 255}
-#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
-#define INSTR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
-#define INSTR_RR_M 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
-#define INSTR_RR_B 2, { R_12, 0,0,0,0,0 } /* e.g. br */
-#define INSTR_RR_I 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
-#define INSTR_RR_R 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
-#define INSTR_RR_E 2, { R_8,R_12,0,0,0,0 } /* e.g. aer */
-#define INSTR_RR_D 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
-#define INSTR_RR_X 2, { R_8,R_12,0,0,0,0 } /* e.g. mxr */
-#define INSTR_RR_ED 2, { F_8,F_12,0,0,0,0 } /* e.g. mer */
-#define INSTR_RR_DE 2, { F_8,F_12,0,0,0,0 } /* e.g. lrer */
-#define INSTR_RR_DX 2, { F_8,F_12,0,0,0,0 } /* e.g. mxdr */
-#define INSTR_RR_XD 2, { F_8,F_12,0,0,0,0 } /* e.g. lrdr */
-#define INSTR_RRE 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
-#define INSTR_RRE_A 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
-#define INSTR_RRE_F 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
-#define INSTR_RRE_O 4, { 0,0,0,0,0,0 } /* e.g. palb */
-#define INSTR_RRE_R 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
-#define INSTR_RRE_R2 4, { R_28,0,0,0,0,0 } /* e.g. tb */
-#define INSTR_RRE_E 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
-#define INSTR_RRE_D 4, { F_24,0,0,0,0,0 } /* e.g. sqdr */
-#define INSTR_RRE_X 4, { F_24,0,0,0,0,0 } /* e.g. dxr */
-#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
-#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
-#define INSTR_RRF_M 4, { R_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr*/
-#define INSTR_RRF_RM 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. didbr*/
-#define INSTR_RRF_R 4, { R_16,R_24,R_28,0,0,0 } /* e.g. madbr*/
-#define INSTR_RRF_F 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr*/
-#define INSTR_RS 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
-#define INSTR_RS_A 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
-#define INSTR_RS_C 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
-#define INSTR_RS_M 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
-#define INSTR_RS_S 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
-#define INSTR_RS_D 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sldl */
-#define INSTR_RX 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
-#define INSTR_RX_M 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
-#define INSTR_RX_B 4, { D_20,X_12,B_16,0,0,0 } /* e.g. b */
-#define INSTR_RX_E 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
-#define INSTR_RX_D 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ad */
-#define INSTR_RX_ED 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. me */
-#define INSTR_RX_DX 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */
-#define INSTR_RXE 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. agr */
-#define INSTR_RXE_F 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
-#define INSTR_RXF 6, { F_32,D_20,X_12,B_16,F_8,0 } /* e.g. madb */
-#define INSTR_S 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
-#define INSTR_S_O 4, { 0,0,0,0,0,0 } /* e.g. hsch */
-#define INSTR_SI 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
-#define INSTR_SS_RR 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
-#define INSTR_SS_LL 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
-#define INSTR_SS_LI 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
-#define INSTR_SS_L 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
-#define INSTR_SS_LMD 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
-#define INSTR_SS_PLO 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
-#define INSTR_SSE 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
-#define INSTR_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
-#define INSTR_RI_U 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
-#define INSTR_RI_A 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
-#define INSTR_RI_MA 4, { U4_8,J16_16,0,0,0 } /* e.g. brc */
-#define INSTR_RI_B 4, { J16_16,0,0,0,0 } /* e.g. j */
-#define INSTR_RSI_A 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
-#define INSTR_RSE 6, { R_8,D_20,B_16,R_12,0,0 } /* e.g. lmg */
-#define INSTR_RSE_M 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
-#define INSTR_RSE_R 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
-#define INSTR_RIE_A 6, { R_8,J16_16,R_12,0,0,0 } /* e.g. brxhg */
-#define INSTR_RIL_A 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
-#define INSTR_RIL_B 6, { J32_16,0,0,0,0,0 } /* e.g. jg */
-#define INSTR_RIL_MA 6, { R_8,J32_16,0,0,0,0 } /* e.g. brcl */
-
-#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_B { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_I { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_R { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_E { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_D { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_X { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_ED { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_DE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_DX { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_XD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_A { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_F { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_O { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
-#define MASK_RRE_R { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_R2 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_E { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_D { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_X { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRF_M { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRF_RM { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRF_R { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRF_F { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_A { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_C { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_S { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_D { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_B { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_E { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_D { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_ED { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_DX { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RXE { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXE_F { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_S { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_S_O { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
-#define MASK_SI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_LL { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_LI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_L { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_LMD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_PLO { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SSE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_U { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_A { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_MA { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_B { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RSI_A { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RSE { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RSE_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RSE_R { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RIE_A { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RIL_A { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RIL_B { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RIL_M { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RIL_MA { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+/* The new format of the INSTR_x_y and MASK_x_y defines is based
+ on the following rules:
+ 1) the middle part of the definition (x in INSTR_x_y) is the official
+ names of the instruction format that you can find in the principals
+ of operation.
+ 2) the last part of the definition (y in INSTR_x_y) gives you an idea
+ which operands the binary represenation of the instruction has.
+ The meanings of the letters in y are:
+ a - access register
+ c - control register
+ d - displacement, 12 bit
+ f - floating pointer register
+ i - signed integer, 4 or 8 bit
+ l - length, 4 or 8 bit
+ p - pc relative
+ r - general purpose register
+ u - unsigned integer, 4 or 8 bit
+ 0 - operand skipped.
+ The order of the letters reflects the layout of the format in
+ storage and not the order of the paramaters of the instructions.
+ The use of the letters is not a 100% match with the PoP but it is
+ quite close.
+
+ For example the instruction "mvo" is defined in the PoP as follows:
+
+ MVO D1(L1,B1),D2(L2,B2) [SS]
+
+ --------------------------------------
+ | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
+ --------------------------------------
+ 0 8 12 16 20 32 36
+
+ The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
+
+#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
+#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
+#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
+#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
+#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
+#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */
+#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
+#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
+#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
+#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
+#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
+#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
+#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
+#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
+#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
+#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
+#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
+#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
+#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
+#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
+#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
+#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
+#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
+#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */
+#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */
+#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */
+#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
+#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
+#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
+#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
+#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
+#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
+#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
+#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
+#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
+#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
+#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
+#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
+#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
+#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
+#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
+#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
+#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
+#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
+#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
+#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
+#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
+#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
+#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
+#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
+#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
+#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
+#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
+#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
+#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
+#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
+#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
+#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
+
+#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
+#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
+#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
+#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
+#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
+#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
const struct s390_opcode s390_opformats[] =
{
{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3 },
- { "ri", OP8(0x00LL), MASK_RI, INSTR_RI, 3 },
- { "ri_a", OP8(0x00LL), MASK_RI_A, INSTR_RI_A, 3 },
- { "ri_b", OP8(0x00LL), MASK_RI_B, INSTR_RI_B, 3 },
- { "ri_ma", OP8(0x00LL), MASK_RI_MA, INSTR_RI_MA, 3 },
- { "ri_u", OP8(0x00LL), MASK_RI_U, INSTR_RI_U, 3 },
- { "rie_a", OP8(0x00LL), MASK_RIE_A, INSTR_RIE_A, 3 },
- { "ril_a", OP8(0x00LL), MASK_RIL_A, INSTR_RIL_A, 3 },
- { "ril_b", OP8(0x00LL), MASK_RIL_B, INSTR_RIL_B, 3 },
- { "ril_ma", OP8(0x00LL), MASK_RIL_MA, INSTR_RIL_MA, 3 },
- { "rr", OP8(0x00LL), MASK_RR, INSTR_RR, 3 },
- { "rr_b", OP8(0x00LL), MASK_RR_B, INSTR_RR_B, 3 },
- { "rr_d", OP8(0x00LL), MASK_RR_D, INSTR_RR_D, 3 },
- { "rr_de", OP8(0x00LL), MASK_RR_DE, INSTR_RR_DE, 3 },
- { "rr_dx", OP8(0x00LL), MASK_RR_DX, INSTR_RR_DX, 3 },
- { "rr_e", OP8(0x00LL), MASK_RR_E, INSTR_RR_E, 3 },
- { "rr_ed", OP8(0x00LL), MASK_RR_ED, INSTR_RR_ED, 3 },
- { "rr_i", OP8(0x00LL), MASK_RR_I, INSTR_RR_I, 3 },
- { "rr_m", OP8(0x00LL), MASK_RR_M, INSTR_RR_M, 3 },
- { "rr_r", OP8(0x00LL), MASK_RR_R, INSTR_RR_R, 3 },
- { "rr_x", OP8(0x00LL), MASK_RR_X, INSTR_RR_X, 3 },
- { "rr_xd", OP8(0x00LL), MASK_RR_XD, INSTR_RR_XD, 3 },
- { "rre", OP8(0x00LL), MASK_RRE, INSTR_RRE, 3 },
- { "rre_a", OP8(0x00LL), MASK_RRE_A, INSTR_RRE_A, 3 },
- { "rre_ar", OP8(0x00LL), MASK_RRE_AR, INSTR_RRE_AR, 3 },
- { "rre_d", OP8(0x00LL), MASK_RRE_D, INSTR_RRE_D, 3 },
- { "rre_e", OP8(0x00LL), MASK_RRE_E, INSTR_RRE_E, 3 },
- { "rre_f", OP8(0x00LL), MASK_RRE_F, INSTR_RRE_F, 3 },
- { "rre_o", OP8(0x00LL), MASK_RRE_O, INSTR_RRE_O, 3 },
- { "rre_r", OP8(0x00LL), MASK_RRE_R, INSTR_RRE_R, 3 },
- { "rre_r2", OP8(0x00LL), MASK_RRE_R2, INSTR_RRE_R2, 3 },
- { "rre_ra", OP8(0x00LL), MASK_RRE_RA, INSTR_RRE_RA, 3 },
- { "rre_x", OP8(0x00LL), MASK_RRE_X, INSTR_RRE_X, 3 },
- { "rrf_f", OP8(0x00LL), MASK_RRF_F, INSTR_RRF_F, 3 },
- { "rrf_m", OP8(0x00LL), MASK_RRF_M, INSTR_RRF_M, 3 },
- { "rrf_r", OP8(0x00LL), MASK_RRF_R, INSTR_RRF_R, 3 },
- { "rrf_rm", OP8(0x00LL), MASK_RRF_RM, INSTR_RRF_RM, 3 },
- { "rs", OP8(0x00LL), MASK_RS, INSTR_RS, 3 },
- { "rs_a", OP8(0x00LL), MASK_RS_A, INSTR_RS_A, 3 },
- { "rs_c", OP8(0x00LL), MASK_RS_C, INSTR_RS_C, 3 },
- { "rs_d", OP8(0x00LL), MASK_RS_D, INSTR_RS_D, 3 },
- { "rs_m", OP8(0x00LL), MASK_RS_M, INSTR_RS_M, 3 },
- { "rs_s", OP8(0x00LL), MASK_RS_S, INSTR_RS_S, 3 },
- { "rse", OP8(0x00LL), MASK_RSE, INSTR_RSE, 3 },
- { "rse_m", OP8(0x00LL), MASK_RSE_M, INSTR_RSE_M, 3 },
- { "rse_r", OP8(0x00LL), MASK_RSE_R, INSTR_RSE_R, 3 },
- { "rsi_a", OP8(0x00LL), MASK_RSI_A, INSTR_RSI_A, 3 },
- { "rx", OP8(0x00LL), MASK_RX, INSTR_RX, 3 },
- { "rx_b", OP8(0x00LL), MASK_RX_B, INSTR_RX_B, 3 },
- { "rx_d", OP8(0x00LL), MASK_RX_D, INSTR_RX_D, 3 },
- { "rx_dx", OP8(0x00LL), MASK_RX_DX, INSTR_RX_DX, 3 },
- { "rx_e", OP8(0x00LL), MASK_RX_E, INSTR_RX_E, 3 },
- { "rx_ed", OP8(0x00LL), MASK_RX_ED, INSTR_RX_ED, 3 },
- { "rx_m", OP8(0x00LL), MASK_RX_M, INSTR_RX_M, 3 },
- { "rxe", OP8(0x00LL), MASK_RXE, INSTR_RXE, 3 },
- { "rxe_f", OP8(0x00LL), MASK_RXE_F, INSTR_RXE_F, 3 },
- { "rxf", OP8(0x00LL), MASK_RXF, INSTR_RXF, 3 },
- { "s", OP8(0x00LL), MASK_S, INSTR_S, 3 },
- { "si", OP8(0x00LL), MASK_SI, INSTR_SI, 3 },
- { "ss_l", OP8(0x00LL), MASK_SS_L, INSTR_SS_L, 3 },
- { "ss_li", OP8(0x00LL), MASK_SS_LI, INSTR_SS_LI, 3 },
- { "ss_ll", OP8(0x00LL), MASK_SS_LL, INSTR_SS_LL, 3 },
- { "ss_lmd", OP8(0x00LL), MASK_SS_LMD, INSTR_SS_LMD, 3 },
- { "ss_plo", OP8(0x00LL), MASK_SS_PLO, INSTR_SS_PLO, 3 },
- { "ss_rr", OP8(0x00LL), MASK_SS_RR, INSTR_SS_RR, 3 },
- { "sse", OP8(0x00LL), MASK_SSE, INSTR_SSE, 3 },
+ { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3 },
+ { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3 },
+ { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3 },
+ { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3 },
+ { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3 },
+ { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3 },
+ { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3 },
+ { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3 },
+ { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3 },
+ { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3 },
+ { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3 },
+ { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3 },
+ { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3 },
+ { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3 },
+ { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3 },
+ { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3 },
};
const int s390_num_opformats =
sizeof (s390_opformats) / sizeof (s390_opformats[0]);
-/* The opcode table.
-
- The format of the opcode table is:
-
- NAME OPCODE MASK OPERANDS
-
- NAME is the name of the instruction.
- OPCODE is the instruction opcode.
- MASK is the opcode mask; this is used to tell the disassembler
- which bits in the actual opcode must match OPCODE.
- OPERANDS is the list of operands.
-
- The disassembler reads the table in order and prints the first
- instruction which matches. */
-
-const struct s390_opcode s390_opcodes[] =
- {
- { "dp", OP8(0xfdLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "mp", OP8(0xfcLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "sp", OP8(0xfbLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "ap", OP8(0xfaLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "cp", OP8(0xf9LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "zap", OP8(0xf8LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "unpk", OP8(0xf3LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "pack", OP8(0xf2LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "mvo", OP8(0xf1LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "srp", OP8(0xf0LL), MASK_SS_LI, INSTR_SS_LI, 3},
- { "lmd", OP8(0xefLL), MASK_SS_LMD, INSTR_SS_LMD, 2},
- { "plo", OP8(0xeeLL), MASK_SS_PLO, INSTR_SS_PLO, 3},
- { "msdb", OP48(0xed000000001fLL), MASK_RXF, INSTR_RXF, 3},
- { "madb", OP48(0xed000000001eLL), MASK_RXF, INSTR_RXF, 3},
- { "ddb", OP48(0xed000000001dLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mdb", OP48(0xed000000001cLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "sdb", OP48(0xed000000001bLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "adb", OP48(0xed000000001aLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "cdb", OP48(0xed0000000019LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "kdb", OP48(0xed0000000018LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "meeb", OP48(0xed0000000017LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "sqdb", OP48(0xed0000000015LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "sqeb", OP48(0xed0000000014LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "tcxb", OP48(0xed0000000012LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "tcdb", OP48(0xed0000000011LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "tceb", OP48(0xed0000000010LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mseb", OP48(0xed000000000fLL), MASK_RXF, INSTR_RXF, 3},
- { "maeb", OP48(0xed000000000eLL), MASK_RXF, INSTR_RXF, 3},
- { "deb", OP48(0xed000000000dLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mdeb", OP48(0xed000000000cLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "seb", OP48(0xed000000000bLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "aeb", OP48(0xed000000000aLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "ceb", OP48(0xed0000000009LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "keb", OP48(0xed0000000008LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mxdb", OP48(0xed0000000007LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "lxeb", OP48(0xed0000000006LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "lxdb", OP48(0xed0000000005LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "ldeb", OP48(0xed0000000004LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "brxlg", OP48(0xec0000000045LL), MASK_RIE_A, INSTR_RIE_A, 2},
- { "brxhg", OP48(0xec0000000044LL), MASK_RIE_A, INSTR_RIE_A, 2},
- { "lmh", OP48(0xeb0000000096LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "icmh", OP48(0xeb0000000080LL), MASK_RSE_M, INSTR_RSE_M, 2},
- { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "csg", OP48(0xeb0000000030LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_M, INSTR_RSE_M, 2},
- { "stmh", OP48(0xeb0000000026LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "stctg", OP48(0xeb0000000025LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "stmg", OP48(0xeb0000000024LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "clmh", OP48(0xeb0000000020LL), MASK_RSE_M, INSTR_RSE_M, 2},
- { "rll", OP48(0xeb000000001dLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "rllg", OP48(0xeb000000001cLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "tracg", OP48(0xeb000000000fLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "sllg", OP48(0xeb000000000dLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "srlg", OP48(0xeb000000000cLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "slag", OP48(0xeb000000000bLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "srag", OP48(0xeb000000000aLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "lmg", OP48(0xeb0000000004LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "unpka", OP8(0xeaLL), MASK_SS_L, INSTR_SS_L, 2},
- { "pka", OP8(0xe9LL), MASK_SS_L, INSTR_SS_L, 2},
- { "mvcin", OP8(0xe8LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvcdk", OP16(0xe50fLL), MASK_SSE, INSTR_SSE, 3},
- { "mvcsk", OP16(0xe50eLL), MASK_SSE, INSTR_SSE, 3},
- { "tprot", OP16(0xe501LL), MASK_SSE, INSTR_SSE, 3},
- { "strag", OP48(0xe50000000002LL), MASK_SSE, INSTR_SSE, 2},
- { "lasp", OP16(0xe500LL), MASK_SSE, INSTR_SSE, 3},
- { "slb", OP48(0xe30000000099LL), MASK_RXE, INSTR_RXE, 2},
- { "alc", OP48(0xe30000000098LL), MASK_RXE, INSTR_RXE, 2},
- { "dl", OP48(0xe30000000097LL), MASK_RXE, INSTR_RXE, 2},
- { "ml", OP48(0xe30000000096LL), MASK_RXE, INSTR_RXE, 2},
- { "llgh", OP48(0xe30000000091LL), MASK_RXE, INSTR_RXE, 2},
- { "llgc", OP48(0xe30000000090LL), MASK_RXE, INSTR_RXE, 2},
- { "lpq", OP48(0xe3000000008fLL), MASK_RXE, INSTR_RXE, 2},
- { "stpq", OP48(0xe3000000008eLL), MASK_RXE, INSTR_RXE, 2},
- { "slbg", OP48(0xe30000000089LL), MASK_RXE, INSTR_RXE, 2},
- { "alcg", OP48(0xe30000000088LL), MASK_RXE, INSTR_RXE, 2},
- { "dlg", OP48(0xe30000000087LL), MASK_RXE, INSTR_RXE, 2},
- { "mlg", OP48(0xe30000000086LL), MASK_RXE, INSTR_RXE, 2},
- { "xg", OP48(0xe30000000082LL), MASK_RXE, INSTR_RXE, 2},
- { "og", OP48(0xe30000000081LL), MASK_RXE, INSTR_RXE, 2},
- { "ng", OP48(0xe30000000080LL), MASK_RXE, INSTR_RXE, 2},
- { "bctg", OP48(0xe30000000046LL), MASK_RXE, INSTR_RXE, 2},
- { "strvh", OP48(0xe3000000003fLL), MASK_RXE, INSTR_RXE, 2},
- { "strv", OP48(0xe3000000003eLL), MASK_RXE, INSTR_RXE, 2},
- { "clgf", OP48(0xe30000000031LL), MASK_RXE, INSTR_RXE, 2},
- { "cgf", OP48(0xe30000000030LL), MASK_RXE, INSTR_RXE, 2},
- { "strvg", OP48(0xe3000000002fLL), MASK_RXE, INSTR_RXE, 2},
- { "cvdg", OP48(0xe3000000002eLL), MASK_RXE, INSTR_RXE, 2},
- { "stg", OP48(0xe30000000024LL), MASK_RXE, INSTR_RXE, 2},
- { "clg", OP48(0xe30000000021LL), MASK_RXE, INSTR_RXE, 2},
- { "cg", OP48(0xe30000000020LL), MASK_RXE, INSTR_RXE, 2},
- { "lrvh", OP48(0xe3000000001fLL), MASK_RXE, INSTR_RXE, 2},
- { "lrv", OP48(0xe3000000001eLL), MASK_RXE, INSTR_RXE, 2},
- { "dsgf", OP48(0xe3000000001dLL), MASK_RXE, INSTR_RXE, 2},
- { "msgf", OP48(0xe3000000001cLL), MASK_RXE, INSTR_RXE, 2},
- { "slgf", OP48(0xe3000000001bLL), MASK_RXE, INSTR_RXE, 2},
- { "algf", OP48(0xe3000000001aLL), MASK_RXE, INSTR_RXE, 2},
- { "sgf", OP48(0xe30000000019LL), MASK_RXE, INSTR_RXE, 2},
- { "agf", OP48(0xe30000000018LL), MASK_RXE, INSTR_RXE, 2},
- { "llgt", OP48(0xe30000000017LL), MASK_RXE, INSTR_RXE, 2},
- { "llgf", OP48(0xe30000000016LL), MASK_RXE, INSTR_RXE, 2},
- { "lgh", OP48(0xe30000000015LL), MASK_RXE, INSTR_RXE, 2},
- { "lgf", OP48(0xe30000000014LL), MASK_RXE, INSTR_RXE, 2},
- { "lrvg", OP48(0xe3000000000fLL), MASK_RXE, INSTR_RXE, 2},
- { "cvbg", OP48(0xe3000000000eLL), MASK_RXE, INSTR_RXE, 2},
- { "dsg", OP48(0xe3000000000dLL), MASK_RXE, INSTR_RXE, 2},
- { "msg", OP48(0xe3000000000cLL), MASK_RXE, INSTR_RXE, 2},
- { "slg", OP48(0xe3000000000bLL), MASK_RXE, INSTR_RXE, 2},
- { "alg", OP48(0xe3000000000aLL), MASK_RXE, INSTR_RXE, 2},
- { "sg", OP48(0xe30000000009LL), MASK_RXE, INSTR_RXE, 2},
- { "ag", OP48(0xe30000000008LL), MASK_RXE, INSTR_RXE, 2},
- { "lg", OP48(0xe30000000004LL), MASK_RXE, INSTR_RXE, 2},
- { "lrag", OP48(0xe30000000003LL), MASK_RXE, INSTR_RXE, 2},
- { "unpku", OP8(0xe2LL), MASK_SS_L, INSTR_SS_L, 2},
- { "pku", OP8(0xe1LL), MASK_SS_L, INSTR_SS_L, 2},
- { "edmk", OP8(0xdfLL), MASK_SS_L, INSTR_SS_L, 3},
- { "ed", OP8(0xdeLL), MASK_SS_L, INSTR_SS_L, 3},
- { "trt", OP8(0xddLL), MASK_SS_L, INSTR_SS_L, 3},
- { "tr", OP8(0xdcLL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvcs", OP8(0xdbLL), MASK_SS_RR, INSTR_SS_RR, 3},
- { "mvcp", OP8(0xdaLL), MASK_SS_RR, INSTR_SS_RR, 3},
- { "mvck", OP8(0xd9LL), MASK_SS_RR, INSTR_SS_RR, 3},
- { "xc", OP8(0xd7LL), MASK_SS_L, INSTR_SS_L, 3},
- { "oc", OP8(0xd6LL), MASK_SS_L, INSTR_SS_L, 3},
- { "clc", OP8(0xd5LL), MASK_SS_L, INSTR_SS_L, 3},
- { "nc", OP8(0xd4LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvz", OP8(0xd3LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvc", OP8(0xd2LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvn", OP8(0xd1LL), MASK_SS_L, INSTR_SS_L, 3},
- { "jg", OP16(0xc0f4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgno", OP16(0xc0e4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnh", OP16(0xc0d4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnp", OP16(0xc0d4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgle", OP16(0xc0c4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnl", OP16(0xc0b4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnm", OP16(0xc0b4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jghe", OP16(0xc0a4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnlh", OP16(0xc094LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jge", OP16(0xc084LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgz", OP16(0xc084LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgne", OP16(0xc074LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnz", OP16(0xc074LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jglh", OP16(0xc064LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnhe", OP16(0xc054LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgl", OP16(0xc044LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgm", OP16(0xc044LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnle", OP16(0xc034LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgh", OP16(0xc024LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgp", OP16(0xc024LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgo", OP16(0xc014LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "brasl", OP16(0xc005LL), MASK_RIL_A, INSTR_RIL_A, 2},
- { "brcl", OP16(0xc004LL), MASK_RIL_MA, INSTR_RIL_MA, 2},
- { "larl", OP16(0xc000LL), MASK_RIL_A, INSTR_RIL_A, 2},
- { "icm", OP8(0xbfLL), MASK_RS_M, INSTR_RS_M, 3},
- { "stcm", OP8(0xbeLL), MASK_RS_M, INSTR_RS_M, 3},
- { "clm", OP8(0xbdLL), MASK_RS_M, INSTR_RS_M, 3},
- { "cds", OP8(0xbbLL), MASK_RS, INSTR_RS, 3},
- { "cs", OP8(0xbaLL), MASK_RS, INSTR_RS, 3},
- { "esea", OP16(0xb99dLL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "slbr", OP16(0xb999LL), MASK_RRE, INSTR_RRE, 2},
- { "alcr", OP16(0xb998LL), MASK_RRE, INSTR_RRE, 2},
- { "dlr", OP16(0xb997LL), MASK_RRE, INSTR_RRE, 2},
- { "mlr", OP16(0xb996LL), MASK_RRE, INSTR_RRE, 2},
- { "epsw", OP16(0xb98dLL), MASK_RRE, INSTR_RRE, 2},
- { "slbgr", OP16(0xb989LL), MASK_RRE, INSTR_RRE, 2},
- { "alcgr", OP16(0xb988LL), MASK_RRE, INSTR_RRE, 2},
- { "dlgr", OP16(0xb987LL), MASK_RRE, INSTR_RRE, 2},
- { "mlgr", OP16(0xb986LL), MASK_RRE, INSTR_RRE, 2},
- { "troo", OP16(0xb993LL), MASK_RRE, INSTR_RRE, 2},
- { "trot", OP16(0xb992LL), MASK_RRE, INSTR_RRE, 2},
- { "trto", OP16(0xb991LL), MASK_RRE, INSTR_RRE, 2},
- { "trtt", OP16(0xb990LL), MASK_RRE, INSTR_RRE, 2},
- { "xgr", OP16(0xb982LL), MASK_RRE, INSTR_RRE, 2},
- { "ogr", OP16(0xb981LL), MASK_RRE, INSTR_RRE, 2},
- { "ngr", OP16(0xb980LL), MASK_RRE, INSTR_RRE, 2},
- { "bctgr", OP16(0xb946LL), MASK_RRE, INSTR_RRE, 2},
- { "clgfr", OP16(0xb931LL), MASK_RRE, INSTR_RRE, 2},
- { "cgfr", OP16(0xb930LL), MASK_RRE, INSTR_RRE, 2},
- { "sturg", OP16(0xb925LL), MASK_RRE, INSTR_RRE, 2},
- { "clgr", OP16(0xb921LL), MASK_RRE, INSTR_RRE, 2},
- { "cgr", OP16(0xb920LL), MASK_RRE, INSTR_RRE, 2},
- { "lrvr", OP16(0xb91fLL), MASK_RRE, INSTR_RRE, 2},
- { "dsgfr", OP16(0xb91dLL), MASK_RRE, INSTR_RRE, 2},
- { "msgfr", OP16(0xb91cLL), MASK_RRE, INSTR_RRE, 2},
- { "slgfr", OP16(0xb91bLL), MASK_RRE, INSTR_RRE, 2},
- { "algfr", OP16(0xb91aLL), MASK_RRE, INSTR_RRE, 2},
- { "sgfr", OP16(0xb919LL), MASK_RRE, INSTR_RRE, 2},
- { "agfr", OP16(0xb918LL), MASK_RRE, INSTR_RRE, 2},
- { "llgtr", OP16(0xb917LL), MASK_RRE, INSTR_RRE, 2},
- { "llgfr", OP16(0xb916LL), MASK_RRE, INSTR_RRE, 2},
- { "lgfr", OP16(0xb914LL), MASK_RRE, INSTR_RRE, 2},
- { "lcgfr", OP16(0xb913LL), MASK_RRE, INSTR_RRE, 2},
- { "ltgfr", OP16(0xb912LL), MASK_RRE, INSTR_RRE, 2},
- { "lngfr", OP16(0xb911LL), MASK_RRE, INSTR_RRE, 2},
- { "lpgfr", OP16(0xb910LL), MASK_RRE, INSTR_RRE, 2},
- { "lrvgr", OP16(0xb90fLL), MASK_RRE, INSTR_RRE, 2},
- { "eregg", OP16(0xb90eLL), MASK_RRE, INSTR_RRE, 2},
- { "dsgr", OP16(0xb90dLL), MASK_RRE, INSTR_RRE, 2},
- { "msgr", OP16(0xb90cLL), MASK_RRE, INSTR_RRE, 2},
- { "slgr", OP16(0xb90bLL), MASK_RRE, INSTR_RRE, 2},
- { "algr", OP16(0xb90aLL), MASK_RRE, INSTR_RRE, 2},
- { "sgr", OP16(0xb909LL), MASK_RRE, INSTR_RRE, 2},
- { "agr", OP16(0xb908LL), MASK_RRE, INSTR_RRE, 2},
- { "lurag", OP16(0xb905LL), MASK_RRE, INSTR_RRE, 2},
- { "lgr", OP16(0xb904LL), MASK_RRE, INSTR_RRE, 2},
- { "lcgr", OP16(0xb903LL), MASK_RRE, INSTR_RRE, 2},
- { "ltgr", OP16(0xb902LL), MASK_RRE, INSTR_RRE, 2},
- { "lngr", OP16(0xb901LL), MASK_RRE, INSTR_RRE, 2},
- { "lpgr", OP16(0xb900LL), MASK_RRE, INSTR_RRE, 2},
- { "lctl", OP8(0xb7LL), MASK_RS_C, INSTR_RS_C, 3},
- { "stctl", OP8(0xb6LL), MASK_RS_C, INSTR_RS_C, 3},
- { "cgxr", OP16(0xb3caLL), MASK_RRF_F, INSTR_RRF_F, 2},
- { "cgdr", OP16(0xb3c9LL), MASK_RRF_F, INSTR_RRF_F, 2},
- { "cger", OP16(0xb3c8LL), MASK_RRF_F, INSTR_RRF_F, 2},
- { "cxgr", OP16(0xb3c6LL), MASK_RRE, INSTR_RRE, 2},
- { "cdgr", OP16(0xb3c5LL), MASK_RRE, INSTR_RRE, 2},
- { "cegr", OP16(0xb3c4LL), MASK_RRE, INSTR_RRE, 2},
- { "cgxbr", OP16(0xb3aaLL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "cgdbr", OP16(0xb3a9LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "cgebr", OP16(0xb3a8LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "cxgbr", OP16(0xb3a6LL), MASK_RRE, INSTR_RRE, 2},
- { "cdgbr", OP16(0xb3a5LL), MASK_RRE, INSTR_RRE, 2},
- { "cegbr", OP16(0xb3a4LL), MASK_RRE, INSTR_RRE, 2},
- { "cfxbr", OP16(0xb39aLL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "cfdbr", OP16(0xb399LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "cfebr", OP16(0xb398LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "cxfbr", OP16(0xb396LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cdfbr", OP16(0xb395LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cefbr", OP16(0xb394LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "efpc", OP16(0xb38cLL), MASK_RRE, INSTR_RRE, 3},
- { "sfpc", OP16(0xb384LL), MASK_RRE, INSTR_RRE, 3},
- { "lzxr", OP16(0xb376LL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "lzdr", OP16(0xb375LL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "lzer", OP16(0xb374LL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "fidbr", OP16(0xb35fLL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "didbr", OP16(0xb35bLL), MASK_RRF_RM, INSTR_RRF_RM, 3},
- { "thdr", OP16(0xb359LL), MASK_RRE, INSTR_RRE, 2},
- { "thder", OP16(0xb358LL), MASK_RRE, INSTR_RRE, 2},
- { "fiebr", OP16(0xb357LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "diebr", OP16(0xb353LL), MASK_RRF_RM, INSTR_RRF_RM, 3},
- { "tbdr", OP16(0xb351LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "tbedr", OP16(0xb350LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "dxbr", OP16(0xb34dLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mxbr", OP16(0xb34cLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sxbr", OP16(0xb34bLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "axbr", OP16(0xb34aLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cxbr", OP16(0xb349LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "kxbr", OP16(0xb348LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "fixbr", OP16(0xb347LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "lexbr", OP16(0xb346LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ldxbr", OP16(0xb345LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ledbr", OP16(0xb344LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lcxbr", OP16(0xb343LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ltxbr", OP16(0xb342LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lnxbr", OP16(0xb341LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lpxbr", OP16(0xb340LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "msdbr", OP16(0xb31fLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "madbr", OP16(0xb31eLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "ddbr", OP16(0xb31dLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mdbr", OP16(0xb31cLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sdbr", OP16(0xb31bLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "adbr", OP16(0xb31aLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cdbr", OP16(0xb319LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "kdbr", OP16(0xb318LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "meebr", OP16(0xb317LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sqxbr", OP16(0xb316LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sqdbr", OP16(0xb315LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sqebr", OP16(0xb314LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lcdbr", OP16(0xb313LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ltdbr", OP16(0xb312LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lndbr", OP16(0xb311LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lpdbr", OP16(0xb310LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "msebr", OP16(0xb30fLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "maebr", OP16(0xb30eLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "debr", OP16(0xb30dLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mdebr", OP16(0xb30cLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sebr", OP16(0xb30bLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "aebr", OP16(0xb30aLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cebr", OP16(0xb309LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "kebr", OP16(0xb308LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mxdbr", OP16(0xb307LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lxebr", OP16(0xb306LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lxdbr", OP16(0xb305LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ldebr", OP16(0xb304LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lcebr", OP16(0xb303LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ltebr", OP16(0xb302LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lnebr", OP16(0xb301LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lpebr", OP16(0xb300LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "trap4", OP16(0xb2ffLL), MASK_S, INSTR_S, 3},
- { "lpswe", OP16(0xb2b2LL), MASK_S, INSTR_S, 2},
- { "stfl", OP16(0xb2b1LL), MASK_S, INSTR_S, 2},
- { "cutfu", OP16(0xb2a7LL), MASK_RRE, INSTR_RRE, 3},
- { "cuutf", OP16(0xb2a6LL), MASK_RRE, INSTR_RRE, 3},
- { "tre", OP16(0xb2a5LL), MASK_RRE, INSTR_RRE, 2},
- { "lfpc", OP16(0xb29dLL), MASK_S, INSTR_S, 3},
- { "stfpc", OP16(0xb29cLL), MASK_S, INSTR_S, 3},
- { "srnm", OP16(0xb299LL), MASK_S, INSTR_S, 3},
- { "stsi", OP16(0xb27dLL), MASK_S, INSTR_S, 3},
- { "sacf", OP16(0xb279LL), MASK_S, INSTR_S, 3},
- { "stcke", OP16(0xb278LL), MASK_S, INSTR_S, 2},
- { "rp", OP16(0xb277LL), MASK_S, INSTR_S, 3},
- { "siga", OP16(0xb274LL), MASK_S, INSTR_S, 3},
- { "cmpsc", OP16(0xb263LL), MASK_RRE, INSTR_RRE, 3},
- { "srst", OP16(0xb25eLL), MASK_RRE, INSTR_RRE, 3},
- { "clst", OP16(0xb25dLL), MASK_RRE, INSTR_RRE, 3},
- { "bsa", OP16(0xb25aLL), MASK_RRE, INSTR_RRE, 3},
- { "bsg", OP16(0xb258LL), MASK_RRE, INSTR_RRE, 3},
- { "cuse", OP16(0xb257LL), MASK_RRE, INSTR_RRE, 3},
- { "mvst", OP16(0xb255LL), MASK_RRE, INSTR_RRE, 3},
- { "mvpg", OP16(0xb254LL), MASK_RRE, INSTR_RRE, 3},
- { "msr", OP16(0xb252LL), MASK_RRE, INSTR_RRE, 3},
- { "csp", OP16(0xb250LL), MASK_RRE, INSTR_RRE, 3},
- { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3},
- { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3},
- { "cpya", OP16(0xb24dLL), MASK_RRE_A, INSTR_RRE_A, 3},
- { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3},
- { "lura", OP16(0xb24bLL), MASK_RRE, INSTR_RRE, 3},
- { "esta", OP16(0xb24aLL), MASK_RRE, INSTR_RRE, 3},
- { "ereg", OP16(0xb249LL), MASK_RRE, INSTR_RRE, 3},
- { "palb", OP16(0xb248LL), MASK_RRE_O, INSTR_RRE_O, 3},
- { "msta", OP16(0xb247LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "stura", OP16(0xb246LL), MASK_RRE, INSTR_RRE, 3},
- { "sqer", OP16(0xb245LL), MASK_RRE_E, INSTR_RRE_E, 3},
- { "sqdr", OP16(0xb244LL), MASK_RRE_D, INSTR_RRE_D, 3},
- { "cksm", OP16(0xb241LL), MASK_RRE, INSTR_RRE, 3},
- { "bakr", OP16(0xb240LL), MASK_RRE, INSTR_RRE, 3},
- { "schm", OP16(0xb23cLL), MASK_S_O, INSTR_S_O, 3},
- { "rchp", OP16(0xb23bLL), MASK_S_O, INSTR_S_O, 3},
- { "stcps", OP16(0xb23aLL), MASK_S, INSTR_S, 3},
- { "stcrw", OP16(0xb239LL), MASK_S, INSTR_S, 3},
- { "rsch", OP16(0xb238LL), MASK_S_O, INSTR_S_O, 3},
- { "sal", OP16(0xb237LL), MASK_S_O, INSTR_S_O, 3},
- { "tpi", OP16(0xb236LL), MASK_S, INSTR_S, 3},
- { "tsch", OP16(0xb235LL), MASK_S, INSTR_S, 3},
- { "stsch", OP16(0xb234LL), MASK_S, INSTR_S, 3},
- { "ssch", OP16(0xb233LL), MASK_S, INSTR_S, 3},
- { "msch", OP16(0xb232LL), MASK_S, INSTR_S, 3},
- { "hsch", OP16(0xb231LL), MASK_S_O, INSTR_S_O, 3},
- { "csch", OP16(0xb230LL), MASK_S_O, INSTR_S_O, 3},
- { "dxr", OP16(0xb22dLL), MASK_RRE_X, INSTR_RRE_X, 3},
- { "tb", OP16(0xb22cLL), MASK_RRE_R2, INSTR_RRE_R2, 3},
- { "sske", OP16(0xb22bLL), MASK_RRE, INSTR_RRE, 3},
- { "rrbe", OP16(0xb22aLL), MASK_RRE, INSTR_RRE, 3},
- { "iske", OP16(0xb229LL), MASK_RRE, INSTR_RRE, 3},
- { "pt", OP16(0xb228LL), MASK_RRE, INSTR_RRE, 3},
- { "esar", OP16(0xb227LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "epar", OP16(0xb226LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "ssar", OP16(0xb225LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "iac", OP16(0xb224LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "ivsk", OP16(0xb223LL), MASK_RRE, INSTR_RRE, 3},
- { "ipm", OP16(0xb222LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "ipte", OP16(0xb221LL), MASK_RRE, INSTR_RRE, 3},
- { "cfc", OP16(0xb21aLL), MASK_S, INSTR_S, 3},
- { "sac", OP16(0xb219LL), MASK_S, INSTR_S, 3},
- { "pc", OP16(0xb218LL), MASK_S, INSTR_S, 3},
- { "sie", OP16(0xb214LL), MASK_S, INSTR_S, 3},
- { "stap", OP16(0xb212LL), MASK_S, INSTR_S, 3},
- { "stpx", OP16(0xb211LL), MASK_S, INSTR_S, 3},
- { "spx", OP16(0xb210LL), MASK_S, INSTR_S, 3},
- { "ptlb", OP16(0xb20dLL), MASK_S_O, INSTR_S_O, 3},
- { "ipk", OP16(0xb20bLL), MASK_S_O, INSTR_S_O, 3},
- { "spka", OP16(0xb20aLL), MASK_S, INSTR_S, 3},
- { "stpt", OP16(0xb209LL), MASK_S, INSTR_S, 3},
- { "spt", OP16(0xb208LL), MASK_S, INSTR_S, 3},
- { "stckc", OP16(0xb207LL), MASK_S, INSTR_S, 3},
- { "sckc", OP16(0xb206LL), MASK_S, INSTR_S, 3},
- { "stck", OP16(0xb205LL), MASK_S, INSTR_S, 3},
- { "sck", OP16(0xb204LL), MASK_S, INSTR_S, 3},
- { "stidp", OP16(0xb202LL), MASK_S, INSTR_S, 3},
- { "lra", OP8(0xb1LL), MASK_RX, INSTR_RX, 3},
- { "mc", OP8(0xafLL), MASK_SI, INSTR_SI, 3},
- { "sigp", OP8(0xaeLL), MASK_RS, INSTR_RS, 3},
- { "stosm", OP8(0xadLL), MASK_SI, INSTR_SI, 3},
- { "stnsm", OP8(0xacLL), MASK_SI, INSTR_SI, 3},
- { "clcle", OP8(0xa9LL), MASK_RS, INSTR_RS, 3},
- { "mvcle", OP8(0xa8LL), MASK_RS, INSTR_RS, 3},
- { "j", OP16(0xa7f4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jno", OP16(0xa7e4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnh", OP16(0xa7d4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnp", OP16(0xa7d4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jle", OP16(0xa7c4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnl", OP16(0xa7b4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnm", OP16(0xa7b4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jhe", OP16(0xa7a4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnlh", OP16(0xa794LL), MASK_RI_B, INSTR_RI_B, 3},
- { "je", OP16(0xa784LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jz", OP16(0xa784LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jne", OP16(0xa774LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnz", OP16(0xa774LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jlh", OP16(0xa764LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnhe", OP16(0xa754LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jl", OP16(0xa744LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jm", OP16(0xa744LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnle", OP16(0xa734LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jh", OP16(0xa724LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jp", OP16(0xa724LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jo", OP16(0xa714LL), MASK_RI_B, INSTR_RI_B, 3},
- { "cghi", OP16(0xa70fLL), MASK_RI, INSTR_RI, 2},
- { "chi", OP16(0xa70eLL), MASK_RI, INSTR_RI, 3},
- { "mghi", OP16(0xa70dLL), MASK_RI, INSTR_RI, 2},
- { "mhi", OP16(0xa70cLL), MASK_RI, INSTR_RI, 3},
- { "aghi", OP16(0xa70bLL), MASK_RI, INSTR_RI, 2},
- { "ahi", OP16(0xa70aLL), MASK_RI, INSTR_RI, 3},
- { "lghi", OP16(0xa709LL), MASK_RI, INSTR_RI, 2},
- { "lhi", OP16(0xa708LL), MASK_RI, INSTR_RI, 3},
- { "brctg", OP16(0xa707LL), MASK_RI_A, INSTR_RI_A, 2},
- { "brct", OP16(0xa706LL), MASK_RI_A, INSTR_RI_A, 3},
- { "bras", OP16(0xa705LL), MASK_RI_A, INSTR_RI_A, 3},
- { "brc", OP16(0xa704LL), MASK_RI_MA, INSTR_RI_MA, 3},
- { "tmhl", OP16(0xa703LL), MASK_RI_U, INSTR_RI_U, 2},
- { "tmhh", OP16(0xa702LL), MASK_RI_U, INSTR_RI_U, 2},
- { "tml", OP16(0xa701LL), MASK_RI_U, INSTR_RI_U, 3},
- { "tmll", OP16(0xa701LL), MASK_RI_U, INSTR_RI_U, 2},
- { "tmh", OP16(0xa700LL), MASK_RI_U, INSTR_RI_U, 3},
- { "tmlh", OP16(0xa700LL), MASK_RI_U, INSTR_RI_U, 2},
- { "llill", OP16(0xa50fLL), MASK_RI_U, INSTR_RI_U, 2},
- { "llilh", OP16(0xa50eLL), MASK_RI_U, INSTR_RI_U, 2},
- { "llihl", OP16(0xa50dLL), MASK_RI_U, INSTR_RI_U, 2},
- { "llihh", OP16(0xa50cLL), MASK_RI_U, INSTR_RI_U, 2},
- { "oill", OP16(0xa50bLL), MASK_RI_U, INSTR_RI_U, 2},
- { "oilh", OP16(0xa50aLL), MASK_RI_U, INSTR_RI_U, 2},
- { "oihl", OP16(0xa509LL), MASK_RI_U, INSTR_RI_U, 2},
- { "oihh", OP16(0xa508LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nill", OP16(0xa507LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nilh", OP16(0xa506LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nihl", OP16(0xa505LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nihh", OP16(0xa504LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iill", OP16(0xa503LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iilh", OP16(0xa502LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iihl", OP16(0xa501LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iihh", OP16(0xa500LL), MASK_RI_U, INSTR_RI_U, 2},
- { "stam", OP8(0x9bLL), MASK_RS_A, INSTR_RS_A, 3},
- { "lam", OP8(0x9aLL), MASK_RS_A, INSTR_RS_A, 3},
- { "trace", OP8(0x99LL), MASK_RS, INSTR_RS, 3},
- { "lm", OP8(0x98LL), MASK_RS, INSTR_RS, 3},
- { "xi", OP8(0x97LL), MASK_SI, INSTR_SI, 3},
- { "oi", OP8(0x96LL), MASK_SI, INSTR_SI, 3},
- { "cli", OP8(0x95LL), MASK_SI, INSTR_SI, 3},
- { "ni", OP8(0x94LL), MASK_SI, INSTR_SI, 3},
- { "ts", OP8(0x93LL), MASK_S, INSTR_S, 3},
- { "mvi", OP8(0x92LL), MASK_SI, INSTR_SI, 3},
- { "tm", OP8(0x91LL), MASK_SI, INSTR_SI, 3},
- { "stm", OP8(0x90LL), MASK_RS, INSTR_RS, 3},
- { "slda", OP8(0x8fLL), MASK_RS_D, INSTR_RS_D, 3},
- { "srda", OP8(0x8eLL), MASK_RS_D, INSTR_RS_D, 3},
- { "sldl", OP8(0x8dLL), MASK_RS_D, INSTR_RS_D, 3},
- { "srdl", OP8(0x8cLL), MASK_RS_D, INSTR_RS_D, 3},
- { "sla", OP8(0x8bLL), MASK_RS_S, INSTR_RS_S, 3},
- { "sra", OP8(0x8aLL), MASK_RS_S, INSTR_RS_S, 3},
- { "sll", OP8(0x89LL), MASK_RS_S, INSTR_RS_S, 3},
- { "srl", OP8(0x88LL), MASK_RS_S, INSTR_RS_S, 3},
- { "bxle", OP8(0x87LL), MASK_RS, INSTR_RS, 3},
- { "bxh", OP8(0x86LL), MASK_RS, INSTR_RS, 3},
- { "brxle", OP8(0x85LL), MASK_RSI_A, INSTR_RSI_A, 3},
- { "brxh", OP8(0x84LL), MASK_RSI_A, INSTR_RSI_A, 3},
- { "diag", OP8(0x83LL), MASK_RS, INSTR_RS, 3},
- { "lpsw", OP8(0x82LL), MASK_S, INSTR_S, 3},
- { "ssm", OP8(0x80LL), MASK_S, INSTR_S, 3},
- { "su", OP8(0x7fLL), MASK_RX_E, INSTR_RX_E, 3},
- { "au", OP8(0x7eLL), MASK_RX_E, INSTR_RX_E, 3},
- { "de", OP8(0x7dLL), MASK_RX_E, INSTR_RX_E, 3},
- { "me", OP8(0x7cLL), MASK_RX_ED, INSTR_RX_ED, 3},
- { "se", OP8(0x7bLL), MASK_RX_E, INSTR_RX_E, 3},
- { "ae", OP8(0x7aLL), MASK_RX_E, INSTR_RX_E, 3},
- { "ce", OP8(0x79LL), MASK_RX_E, INSTR_RX_E, 3},
- { "le", OP8(0x78LL), MASK_RX_E, INSTR_RX_E, 3},
- { "ms", OP8(0x71LL), MASK_RX, INSTR_RX, 3},
- { "ste", OP8(0x70LL), MASK_RX_E, INSTR_RX_E, 3},
- { "sw", OP8(0x6fLL), MASK_RX_D, INSTR_RX_D, 3},
- { "aw", OP8(0x6eLL), MASK_RX_D, INSTR_RX_D, 3},
- { "dd", OP8(0x6dLL), MASK_RX_D, INSTR_RX_D, 3},
- { "md", OP8(0x6cLL), MASK_RX_D, INSTR_RX_D, 3},
- { "sd", OP8(0x6bLL), MASK_RX_D, INSTR_RX_D, 3},
- { "ad", OP8(0x6aLL), MASK_RX_D, INSTR_RX_D, 3},
- { "cd", OP8(0x69LL), MASK_RX_D, INSTR_RX_D, 3},
- { "ld", OP8(0x68LL), MASK_RX_D, INSTR_RX_D, 3},
- { "mxd", OP8(0x67LL), MASK_RX_DX, INSTR_RX_DX, 3},
- { "std", OP8(0x60LL), MASK_RX_D, INSTR_RX_D, 3},
- { "sl", OP8(0x5fLL), MASK_RX, INSTR_RX, 3},
- { "al", OP8(0x5eLL), MASK_RX, INSTR_RX, 3},
- { "d", OP8(0x5dLL), MASK_RX, INSTR_RX, 3},
- { "m", OP8(0x5cLL), MASK_RX, INSTR_RX, 3},
- { "s", OP8(0x5bLL), MASK_RX, INSTR_RX, 3},
- { "a", OP8(0x5aLL), MASK_RX, INSTR_RX, 3},
- { "c", OP8(0x59LL), MASK_RX, INSTR_RX, 3},
- { "l", OP8(0x58LL), MASK_RX, INSTR_RX, 3},
- { "x", OP8(0x57LL), MASK_RX, INSTR_RX, 3},
- { "o", OP8(0x56LL), MASK_RX, INSTR_RX, 3},
- { "cl", OP8(0x55LL), MASK_RX, INSTR_RX, 3},
- { "n", OP8(0x54LL), MASK_RX, INSTR_RX, 3},
- { "lae", OP8(0x51LL), MASK_RX, INSTR_RX, 3},
- { "st", OP8(0x50LL), MASK_RX, INSTR_RX, 3},
- { "cvb", OP8(0x4fLL), MASK_RX, INSTR_RX, 3},
- { "cvd", OP8(0x4eLL), MASK_RX, INSTR_RX, 3},
- { "bas", OP8(0x4dLL), MASK_RX, INSTR_RX, 3},
- { "mh", OP8(0x4cLL), MASK_RX, INSTR_RX, 3},
- { "sh", OP8(0x4bLL), MASK_RX, INSTR_RX, 3},
- { "ah", OP8(0x4aLL), MASK_RX, INSTR_RX, 3},
- { "ch", OP8(0x49LL), MASK_RX, INSTR_RX, 3},
- { "lh", OP8(0x48LL), MASK_RX, INSTR_RX, 3},
- { "b", OP16(0x47f0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bno", OP16(0x47e0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnh", OP16(0x47d0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnp", OP16(0x47d0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "ble", OP16(0x47c0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnl", OP16(0x47b0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnm", OP16(0x47b0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bhe", OP16(0x47a0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnlh", OP16(0x4790LL), MASK_RX_B, INSTR_RX_B, 3},
- { "be", OP16(0x4780LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bz", OP16(0x4780LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bne", OP16(0x4770LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnz", OP16(0x4770LL), MASK_RX_B, INSTR_RX_B, 3},
- { "blh", OP16(0x4760LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnhe", OP16(0x4750LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bl", OP16(0x4740LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bm", OP16(0x4740LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnle", OP16(0x4730LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bh", OP16(0x4720LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bp", OP16(0x4720LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bo", OP16(0x4710LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bc", OP8(0x47LL), MASK_RX_M, INSTR_RX_M, 3},
- { "nop", OP16(0x4700LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bct", OP8(0x46LL), MASK_RX, INSTR_RX, 3},
- { "bal", OP8(0x45LL), MASK_RX, INSTR_RX, 3},
- { "ex", OP8(0x44LL), MASK_RX, INSTR_RX, 3},
- { "ic", OP8(0x43LL), MASK_RX, INSTR_RX, 3},
- { "stc", OP8(0x42LL), MASK_RX, INSTR_RX, 3},
- { "la", OP8(0x41LL), MASK_RX, INSTR_RX, 3},
- { "sth", OP8(0x40LL), MASK_RX, INSTR_RX, 3},
- { "sur", OP8(0x3fLL), MASK_RR_E, INSTR_RR_E, 3},
- { "aur", OP8(0x3eLL), MASK_RR_E, INSTR_RR_E, 3},
- { "der", OP8(0x3dLL), MASK_RR_E, INSTR_RR_E, 3},
- { "mer", OP8(0x3cLL), MASK_RR_ED, INSTR_RR_ED, 3},
- { "ser", OP8(0x3bLL), MASK_RR_E, INSTR_RR_E, 3},
- { "aer", OP8(0x3aLL), MASK_RR_E, INSTR_RR_E, 3},
- { "cer", OP8(0x39LL), MASK_RR_E, INSTR_RR_E, 3},
- { "ler", OP8(0x38LL), MASK_RR_E, INSTR_RR_E, 3},
- { "sxr", OP8(0x37LL), MASK_RR_X, INSTR_RR_X, 3},
- { "axr", OP8(0x36LL), MASK_RR, INSTR_RR, 3},
- { "lrer", OP8(0x35LL), MASK_RR_DE, INSTR_RR_DE, 3},
- { "her", OP8(0x34LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lcer", OP8(0x33LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lter", OP8(0x32LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lner", OP8(0x31LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lper", OP8(0x30LL), MASK_RR_E, INSTR_RR_E, 3},
- { "swr", OP8(0x2fLL), MASK_RR_D, INSTR_RR_D, 3},
- { "awr", OP8(0x2eLL), MASK_RR_D, INSTR_RR_D, 3},
- { "ddr", OP8(0x2dLL), MASK_RR_D, INSTR_RR_D, 3},
- { "mdr", OP8(0x2cLL), MASK_RR_D, INSTR_RR_D, 3},
- { "sdr", OP8(0x2bLL), MASK_RR_D, INSTR_RR_D, 3},
- { "adr", OP8(0x2aLL), MASK_RR_D, INSTR_RR_D, 3},
- { "cdr", OP8(0x29LL), MASK_RR_D, INSTR_RR_D, 3},
- { "ldr", OP8(0x28LL), MASK_RR_D, INSTR_RR_D, 3},
- { "mxdr", OP8(0x27LL), MASK_RR_DX, INSTR_RR_DX, 3},
- { "mxr", OP8(0x26LL), MASK_RR_X, INSTR_RR_X, 3},
- { "lrdr", OP8(0x25LL), MASK_RR_XD, INSTR_RR_XD, 3},
- { "hdr", OP8(0x24LL), MASK_RR_D, INSTR_RR_D, 3},
- { "lcdr", OP8(0x23LL), MASK_RR_D, INSTR_RR_D, 3},
- { "ltdr", OP8(0x22LL), MASK_RR_D, INSTR_RR_D, 3},
- { "lndr", OP8(0x21LL), MASK_RR_D, INSTR_RR_D, 3},
- { "lpdr", OP8(0x20LL), MASK_RR_D, INSTR_RR_D, 3},
- { "slr", OP8(0x1fLL), MASK_RR, INSTR_RR, 3},
- { "alr", OP8(0x1eLL), MASK_RR, INSTR_RR, 3},
- { "dr", OP8(0x1dLL), MASK_RR, INSTR_RR, 3},
- { "mr", OP8(0x1cLL), MASK_RR, INSTR_RR, 3},
- { "sr", OP8(0x1bLL), MASK_RR, INSTR_RR, 3},
- { "ar", OP8(0x1aLL), MASK_RR, INSTR_RR, 3},
- { "cr", OP8(0x19LL), MASK_RR, INSTR_RR, 3},
- { "lr", OP8(0x18LL), MASK_RR, INSTR_RR, 3},
- { "xr", OP8(0x17LL), MASK_RR, INSTR_RR, 3},
- { "or", OP8(0x16LL), MASK_RR, INSTR_RR, 3},
- { "clr", OP8(0x15LL), MASK_RR, INSTR_RR, 3},
- { "nr", OP8(0x14LL), MASK_RR, INSTR_RR, 3},
- { "lcr", OP8(0x13LL), MASK_RR, INSTR_RR, 3},
- { "ltr", OP8(0x12LL), MASK_RR, INSTR_RR, 3},
- { "lnr", OP8(0x11LL), MASK_RR, INSTR_RR, 3},
- { "lpr", OP8(0x10LL), MASK_RR, INSTR_RR, 3},
- { "clcl", OP8(0x0fLL), MASK_RR, INSTR_RR, 3},
- { "mvcl", OP8(0x0eLL), MASK_RR, INSTR_RR, 3},
- { "basr", OP8(0x0dLL), MASK_RR, INSTR_RR, 3},
- { "bassm", OP8(0x0cLL), MASK_RR, INSTR_RR, 3},
- { "bsm", OP8(0x0bLL), MASK_RR, INSTR_RR, 3},
- { "svc", OP8(0x0aLL), MASK_RR_I, INSTR_RR_I, 3},
- { "br", OP16(0x07f0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnor", OP16(0x07e0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnhr", OP16(0x07d0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnpr", OP16(0x07d0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bler", OP16(0x07c0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnlr", OP16(0x07b0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnmr", OP16(0x07b0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bher", OP16(0x07a0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnlhr", OP16(0x0790LL), MASK_RR_B, INSTR_RR_B, 3},
- { "ber", OP16(0x0780LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bzr", OP16(0x0780LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bner", OP16(0x0770LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnzr", OP16(0x0770LL), MASK_RR_B, INSTR_RR_B, 3},
- { "blhr", OP16(0x0760LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnher", OP16(0x0750LL), MASK_RR_B, INSTR_RR_B, 3},
- { "blr", OP16(0x0740LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bmr", OP16(0x0740LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnler", OP16(0x0730LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bhr", OP16(0x0720LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bpr", OP16(0x0720LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bor", OP16(0x0710LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bcr", OP8(0x07LL), MASK_RR_M, INSTR_RR_M, 3},
- { "nopr", OP16(0x0700LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bctr", OP8(0x06LL), MASK_RR, INSTR_RR, 3},
- { "balr", OP8(0x05LL), MASK_RR, INSTR_RR, 3},
- { "spm", OP8(0x04LL), MASK_RR_R, INSTR_RR_R, 3},
- { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3},
- { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2},
- { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 2},
- { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 2},
- { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 2},
- { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3},
- { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3},
- { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3}
-};
-
-const int s390_num_opcodes =
- sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);
+#include "s390-opc.tab"
diff -urN src/opcodes/s390-opc.txt src-s390/opcodes/s390-opc.txt
--- src/opcodes/s390-opc.txt Fri Sep 14 16:00:09 2001
+++ src-s390/opcodes/s390-opc.txt Fri Sep 14 23:24:39 2001
@@ -1,626 +1,626 @@
# S/390 opcodes list. Use s390-mkopc to convert it into the opcode table.
# Copyright 2000, 2001 Free Software Foundation, Inc.
# Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
-5a a RX "add" esa
-6a ad RX_D "add normalized (long)" esa
-2a adr RR_D "add normalized (long)" esa
-7a ae RX_E "add normalized (short)" esa
-3a aer RR_E "add normalized (short)" esa
-4a ah RX "add halfword" esa
-5e al RX "add logical" esa
-1e alr RR "add logical" esa
-fa ap SS_LL "add decimal" esa
-1a ar RR "add" esa
-7e au RX_E "add unnormalized (short)" esa
-3e aur RR_E "add unnormalized (short)" esa
-6e aw RX_D "add unnormalized (long)" esa
-2e awr RR_D "add unnormalized (long)" esa
-36 axr RR "add normalized" esa
-b240 bakr RRE "branch and stack" esa
-45 bal RX "branch and link" esa
-05 balr RR "branch and link" esa
-4d bas RX "branch and save" esa
-0d basr RR "branch and save" esa
-0c bassm RR "branch and save and set mode" esa
-47 bc RX_M "branch on condition" esa
-07 bcr RR_M "branch on condition" esa
-46 bct RX "branch on count" esa
-06 bctr RR "branch on count" esa
-b258 bsg RRE "branch in subspace group" esa
-0b bsm RR "branch and set mode" esa
-86 bxh RS "branch on index high" esa
-87 bxle RS "branch on index low or equal" esa
-59 c RX "compare" esa
-69 cd RX_D "compare (long)" esa
-29 cdr RR_D "compare (long)" esa
-bb cds RS "compare double and swap" esa
-79 ce RX_E "compare (short)" esa
-39 cer RR_E "compare (short)" esa
-b21a cfc S "compare and form codeword" esa
-49 ch RX "compare halfword" esa
-55 cl RX "compare logical" esa
-d5 clc SS_L "compare logical" esa
-0f clcl RR "compare logical long" esa
-95 cli SI "compare logical" esa
-bd clm RS_M "compare logical characters under mask" esa
-15 clr RR "compare logical" esa
-b25d clst RRE "compare logical string" esa
-b263 cmpsc RRE "compression call" esa
-f9 cp SS_LL "compare decimal" esa
-b24d cpya RRE_A "copy access" esa
-19 cr RR "compare" esa
-ba cs RS "compare and swap" esa
-b230 csch S_O "clear subchannel" esa
-b257 cuse RRE "compare until substring equal" esa
-b250 csp RRE "compare and swap and purge" esa
-4f cvb RX "convert to binary" esa
-4e cvd RX "convert to decimal" esa
-5d d RX "divide" esa
-6d dd RX_D "divide (long)" esa
-2d ddr RR_D "divide (long)" esa
-7d de RX_E "divide (short)" esa
-3d der RR_E "divide (short)" esa
-83 diag RS "diagnose" esa
-fd dp SS_LL "divide decimal" esa
-1d dr RR "divide" esa
-b22d dxr RRE_X "divide (ext.)" esa
+5a a RX_RRRD "add" esa
+6a ad RX_FRRD "add normalized (long)" esa
+2a adr RR_FF "add normalized (long)" esa
+7a ae RX_FRRD "add normalized (short)" esa
+3a aer RR_FF "add normalized (short)" esa
+4a ah RX_RRRD "add halfword" esa
+5e al RX_RRRD "add logical" esa
+1e alr RR_RR "add logical" esa
+fa ap SS_LLRDRD "add decimal" esa
+1a ar RR_RR "add" esa
+7e au RX_FRRD "add unnormalized (short)" esa
+3e aur RR_FF "add unnormalized (short)" esa
+6e aw RX_FRRD "add unnormalized (long)" esa
+2e awr RR_FF "add unnormalized (long)" esa
+36 axr RR_FF "add normalized" esa
+b240 bakr RRE_RR "branch and stack" esa
+45 bal RX_RRRD "branch and link" esa
+05 balr RR_RR "branch and link" esa
+4d bas RX_RRRD "branch and save" esa
+0d basr RR_RR "branch and save" esa
+0c bassm RR_RR "branch and save and set mode" esa
+47 bc RX_URRD "branch on condition" esa
+07 bcr RR_UR "branch on condition" esa
+46 bct RX_RRRD "branch on count" esa
+06 bctr RR_RR "branch on count" esa
+b258 bsg RRE_RR "branch in subspace group" esa
+0b bsm RR_RR "branch and set mode" esa
+86 bxh RS_RRRD "branch on index high" esa
+87 bxle RS_RRRD "branch on index low or equal" esa
+59 c RX_RRRD "compare" esa
+69 cd RX_FRRD "compare (long)" esa
+29 cdr RR_FF "compare (long)" esa
+bb cds RS_RRRD "compare double and swap" esa
+79 ce RX_FRRD "compare (short)" esa
+39 cer RR_FF "compare (short)" esa
+b21a cfc S_RD "compare and form codeword" esa
+49 ch RX_RRRD "compare halfword" esa
+55 cl RX_RRRD "compare logical" esa
+d5 clc SS_L0RDRD "compare logical" esa
+0f clcl RR_RR "compare logical long" esa
+95 cli SI_URD "compare logical" esa
+bd clm RS_RURD "compare logical characters under mask" esa
+15 clr RR_RR "compare logical" esa
+b25d clst RRE_RR "compare logical string" esa
+b263 cmpsc RRE_RR "compression call" esa
+f9 cp SS_LLRDRD "compare decimal" esa
+b24d cpya RRE_AA "copy access" esa
+19 cr RR_RR "compare" esa
+ba cs RS_RRRD "compare and swap" esa
+b230 csch S_00 "clear subchannel" esa
+b257 cuse RRE_RR "compare until substring equal" esa
+b250 csp RRE_RR "compare and swap and purge" esa
+4f cvb RX_RRRD "convert to binary" esa
+4e cvd RX_RRRD "convert to decimal" esa
+5d d RX_RRRD "divide" esa
+6d dd RX_FRRD "divide (long)" esa
+2d ddr RR_FF "divide (long)" esa
+7d de RX_FRRD "divide (short)" esa
+3d der RR_FF "divide (short)" esa
+83 diag RS_RRRD "diagnose" esa
+fd dp SS_LLRDRD "divide decimal" esa
+1d dr RR_RR "divide" esa
+b22d dxr RRE_F0 "divide (ext.)" esa
b24f ear RRE_RA "extract access" esa
-de ed SS_L "edit" esa
-df edmk SS_L "edit and mark" esa
-b226 epar RRE_R "extract primary ASN" esa
-b249 ereg RRE "extract stacked registers" esa
-b227 esar RRE_R "extract secondary ASN" esa
-b24a esta RRE "extract stacked state" esa
-44 ex RX "execute" esa
-24 hdr RR_D "halve (long)" esa
-34 her RR_E "halve (short)" esa
-b231 hsch S_O "halt subchannel" esa
-b224 iac RRE_R "insert address space control" esa
-43 ic RX "insert character" esa
-bf icm RS_M "insert characters under mask" esa
-b20b ipk S_O "insert PSW key" esa
-b222 ipm RRE_R "insert program mask" esa
-b221 ipte RRE "invalidate page table entry" esa
-b229 iske RRE "insert storage key extended" esa
-b223 ivsk RRE "insert virtual storage key" esa
-58 l RX "load" esa
-41 la RX "load address" esa
-51 lae RX "load address extended" esa
-9a lam RS_A "load access multiple" esa
-e500 lasp SSE "load address space parameters" esa
-23 lcdr RR_D "load complement (long)" esa
-33 lcer RR_E "load complement (short)" esa
-13 lcr RR "load complement" esa
-b7 lctl RS_C "load control" esa
-68 ld RX_D "load (long)" esa
-28 ldr RR_D "load (long)" esa
-78 le RX_E "load (short)" esa
-38 ler RR_E "load (short)" esa
-48 lh RX "load halfword" esa
-98 lm RS "load multiple" esa
-21 lndr RR_D "load negative (long)" esa
-31 lner RR_E "load negative (short)" esa
-11 lnr RR "load negative" esa
-20 lpdr RR_D "load positive (long)" esa
-30 lper RR_E "load positive (short)" esa
-10 lpr RR "load positive" esa
-82 lpsw S "load PSW" esa
-18 lr RR "load" esa
-b1 lra RX "load real address" esa
-25 lrdr RR_XD "load rounded (ext. to long)" esa
-35 lrer RR_DE "load rounded (long to short)" esa
-22 ltdr RR_D "load and test (long)" esa
-32 lter RR_E "load and test (short)" esa
-12 ltr RR "load and test" esa
-b24b lura RRE "load using real address" esa
-5c m RX "multiply" esa
-af mc SI "monitor call" esa
-6c md RX_D "multiply (long)" esa
-2c mdr RR_D "multiply (long)" esa
-7c me RX_ED "multiply (short to long)" esa
-3c mer RR_ED "multiply (short to long)" esa
-4c mh RX "multiply halfword" esa
-fc mp SS_LL "multiply decimal" esa
-1c mr RR "multiply" esa
-b232 msch S "modify subchannel" esa
-b247 msta RRE_R "modify stacked state" esa
-d2 mvc SS_L "move" esa
-e50f mvcdk SSE "move with destination key" esa
-e8 mvcin SS_L "move inverse" esa
-d9 mvck SS_RR "move with key" esa
-0e mvcl RR "move long" esa
-da mvcp SS_RR "move to primary" esa
-db mvcs SS_RR "move to secondary" esa
-e50e mvcsk SSE "move with source key" esa
-92 mvi SI "move" esa
-d1 mvn SS_L "move numerics" esa
-f1 mvo SS_LL "move with offset" esa
-b254 mvpg RRE "move page" esa
-b255 mvst RRE "move string" esa
-d3 mvz SS_L "move zones" esa
-67 mxd RX_DX "multiply (long to ext.)" esa
-27 mxdr RR_DX "multiply (long to ext.)" esa
-26 mxr RR_X "multiply (ext.)" esa
-54 n RX "AND" esa
-d4 nc SS_L "AND" esa
-94 ni SI "AND" esa
-14 nr RR "AND" esa
-56 o RX "OR" esa
-d6 oc SS_L "OR" esa
-96 oi SI "OR" esa
-16 or RR "OR" esa
-f2 pack SS_LL "pack" esa
-b248 palb RRE_O "purge ALB" esa
-b218 pc S "program call" esa
+de ed SS_L0RDRD "edit" esa
+df edmk SS_L0RDRD "edit and mark" esa
+b226 epar RRE_R0 "extract primary ASN" esa
+b249 ereg RRE_RR "extract stacked registers" esa
+b227 esar RRE_R0 "extract secondary ASN" esa
+b24a esta RRE_RR "extract stacked state" esa
+44 ex RX_RRRD "execute" esa
+24 hdr RR_FF "halve (long)" esa
+34 her RR_FF "halve (short)" esa
+b231 hsch S_00 "halt subchannel" esa
+b224 iac RRE_R0 "insert address space control" esa
+43 ic RX_RRRD "insert character" esa
+bf icm RS_RURD "insert characters under mask" esa
+b20b ipk S_00 "insert PSW key" esa
+b222 ipm RRE_R0 "insert program mask" esa
+b221 ipte RRE_RR "invalidate page table entry" esa
+b229 iske RRE_RR "insert storage key extended" esa
+b223 ivsk RRE_RR "insert virtual storage key" esa
+58 l RX_RRRD "load" esa
+41 la RX_RRRD "load address" esa
+51 lae RX_RRRD "load address extended" esa
+9a lam RS_AARD "load access multiple" esa
+e500 lasp SSE_RDRD "load address space parameters" esa
+23 lcdr RR_FF "load complement (long)" esa
+33 lcer RR_FF "load complement (short)" esa
+13 lcr RR_RR "load complement" esa
+b7 lctl RS_CCRD "load control" esa
+68 ld RX_FRRD "load (long)" esa
+28 ldr RR_FF "load (long)" esa
+78 le RX_FRRD "load (short)" esa
+38 ler RR_FF "load (short)" esa
+48 lh RX_RRRD "load halfword" esa
+98 lm RS_RRRD "load multiple" esa
+21 lndr RR_FF "load negative (long)" esa
+31 lner RR_FF "load negative (short)" esa
+11 lnr RR_RR "load negative" esa
+20 lpdr RR_FF "load positive (long)" esa
+30 lper RR_FF "load positive (short)" esa
+10 lpr RR_RR "load positive" esa
+82 lpsw S_RD "load PSW" esa
+18 lr RR_RR "load" esa
+b1 lra RX_RRRD "load real address" esa
+25 lrdr RR_FF "load rounded (ext. to long)" esa
+35 lrer RR_FF "load rounded (long to short)" esa
+22 ltdr RR_FF "load and test (long)" esa
+32 lter RR_FF "load and test (short)" esa
+12 ltr RR_RR "load and test" esa
+b24b lura RRE_RR "load using real address" esa
+5c m RX_RRRD "multiply" esa
+af mc SI_URD "monitor call" esa
+6c md RX_FRRD "multiply (long)" esa
+2c mdr RR_FF "multiply (long)" esa
+7c me RX_FRRD "multiply (short to long)" esa
+3c mer RR_FF "multiply (short to long)" esa
+4c mh RX_RRRD "multiply halfword" esa
+fc mp SS_LLRDRD "multiply decimal" esa
+1c mr RR_RR "multiply" esa
+b232 msch S_RD "modify subchannel" esa
+b247 msta RRE_R0 "modify stacked state" esa
+d2 mvc SS_L0RDRD "move" esa
+e50f mvcdk SSE_RDRD "move with destination key" esa
+e8 mvcin SS_L0RDRD "move inverse" esa
+d9 mvck SS_RRRDRD "move with key" esa
+0e mvcl RR_RR "move long" esa
+da mvcp SS_RRRDRD "move to primary" esa
+db mvcs SS_RRRDRD "move to secondary" esa
+e50e mvcsk SSE_RDRD "move with source key" esa
+92 mvi SI_URD "move" esa
+d1 mvn SS_L0RDRD "move numerics" esa
+f1 mvo SS_LLRDRD "move with offset" esa
+b254 mvpg RRE_RR "move page" esa
+b255 mvst RRE_RR "move string" esa
+d3 mvz SS_L0RDRD "move zones" esa
+67 mxd RX_FRRD "multiply (long to ext.)" esa
+27 mxdr RR_FF "multiply (long to ext.)" esa
+26 mxr RR_FF "multiply (ext.)" esa
+54 n RX_RRRD "AND" esa
+d4 nc SS_L0RDRD "AND" esa
+94 ni SI_URD "AND" esa
+14 nr RR_RR "AND" esa
+56 o RX_RRRD "OR" esa
+d6 oc SS_L0RDRD "OR" esa
+96 oi SI_URD "OR" esa
+16 or RR_RR "OR" esa
+f2 pack SS_LLRDRD "pack" esa
+b248 palb RRE_00 "purge ALB" esa
+b218 pc S_RD "program call" esa
0101 pr E "program return" esa
-b228 pt RRE "program transfer" esa
-b20d ptlb S_O "purge TLB" esa
-b23b rchp S_O "reset channel path" esa
-b22a rrbe RRE "reset reference bit extended" esa
-b238 rsch S_O "resume subchannel" esa
-5b s RX "subtract" esa
-b219 sac S "set address space control" esa
-b279 sacf S "set address space control fast" esa
-b237 sal S_O "set address limit" esa
+b228 pt RRE_RR "program transfer" esa
+b20d ptlb S_00 "purge TLB" esa
+b23b rchp S_00 "reset channel path" esa
+b22a rrbe RRE_RR "reset reference bit extended" esa
+b238 rsch S_00 "resume subchannel" esa
+5b s RX_RRRD "subtract" esa
+b219 sac S_RD "set address space control" esa
+b279 sacf S_RD "set address space control fast" esa
+b237 sal S_00 "set address limit" esa
b24e sar RRE_AR "set access" esa
-b23c schm S_O "set channel monitor" esa
-b204 sck S "set clock" esa
-b206 sckc S "set clock comparator" esa
-6b sd RX_D "subtract normalized (long)" esa
-2b sdr RR_D "subtract normalized (long)" esa
-7b se RX_E "subtract normalized (short)" esa
-3b ser RR_E "subtract normalized (short)" esa
-4b sh RX "subtract halfword" esa
-b214 sie S "start interpretive execution" esa
-ae sigp RS "signal processor" esa
-5f sl RX "subtract logical" esa
-8b sla RS_S "shift left single" esa
-8f slda RS_D "shift left double (long)" esa
-8d sldl RS_D "shift left double logical (long)" esa
-89 sll RS_S "shift left single logical" esa
-1f slr RR "subtract logical" esa
-fb sp SS_LL "subtract decimal" esa
-b20a spka S "set PSW key from address" esa
-04 spm RR_R "set program mask" esa
-b208 spt S "set CPU timer" esa
-b210 spx S "set prefix" esa
-b244 sqdr RRE_D "square root (long)" esa
-b245 sqer RRE_E "square root (short)" esa
-1b sr RR "subtract" esa
-8a sra RS_S "shift right single" esa
-8e srda RS_D "shift right double (long)" esa
-8c srdl RS_D "shift right double logical (long)" esa
-88 srl RS_S "shift right single logical" esa
-f0 srp SS_LI "shift and round decimal" esa
-b25e srst RRE "search string" esa
-b225 ssar RRE_R "set secondary ASN" esa
-b233 ssch S "start subchannel" esa
-b22b sske RRE "set storage key extended" esa
-80 ssm S "set system mask" esa
-50 st RX "store" esa
-9b stam RS_A "store access multiple" esa
-b212 stap S "store CPU address" esa
-42 stc RX "store character" esa
-b205 stck S "store clock" esa
-b207 stckc S "store clock comparator" esa
-be stcm RS_M "store characters under mask" esa
-b23a stcps S "store channel path status" esa
-b239 stcrw S "store channel report word" esa
-b6 stctl RS_C "store control" esa
-60 std RX_D "store (long)" esa
-70 ste RX_E "store (short)" esa
-40 sth RX "store halfword" esa
-b202 stidp S "store CPU id" esa
-90 stm RS "store multiple" esa
-ac stnsm SI "store then AND system mask" esa
-ad stosm SI "store then OR system mask" esa
-b209 stpt S "store CPU timer" esa
-b211 stpx S "store prefix" esa
-b234 stsch S "store subchannel" esa
-b246 stura RRE "store using real address" esa
-7f su RX_E "subtract unnormalized (short)" esa
-3f sur RR_E "subtract unnormalized (short)" esa
-0a svc RR_I "supervisor call" esa
-6f sw RX_D "subtract unnormalized (long)" esa
-2f swr RR_D "subtract unnormalized (long)" esa
-37 sxr RR_X "subtract normalized (ext.)" esa
+b23c schm S_00 "set channel monitor" esa
+b204 sck S_RD "set clock" esa
+b206 sckc S_RD "set clock comparator" esa
+6b sd RX_FRRD "subtract normalized (long)" esa
+2b sdr RR_FF "subtract normalized (long)" esa
+7b se RX_FRRD "subtract normalized (short)" esa
+3b ser RR_FF "subtract normalized (short)" esa
+4b sh RX_RRRD "subtract halfword" esa
+b214 sie S_RD "start interpretive execution" esa
+ae sigp RS_RRRD "signal processor" esa
+5f sl RX_RRRD "subtract logical" esa
+8b sla RS_R0RD "shift left single" esa
+8f slda RS_R0RD "shift left double (long)" esa
+8d sldl RS_R0RD "shift left double logical (long)" esa
+89 sll RS_R0RD "shift left single logical" esa
+1f slr RR_RR "subtract logical" esa
+fb sp SS_LLRDRD "subtract decimal" esa
+b20a spka S_RD "set PSW key from address" esa
+04 spm RR_R0 "set program mask" esa
+b208 spt S_RD "set CPU timer" esa
+b210 spx S_RD "set prefix" esa
+b244 sqdr RRE_F0 "square root (long)" esa
+b245 sqer RRE_F0 "square root (short)" esa
+1b sr RR_RR "subtract" esa
+8a sra RS_R0RD "shift right single" esa
+8e srda RS_R0RD "shift right double (long)" esa
+8c srdl RS_R0RD "shift right double logical (long)" esa
+88 srl RS_R0RD "shift right single logical" esa
+f0 srp SS_LIRDRD "shift and round decimal" esa
+b25e srst RRE_RR "search string" esa
+b225 ssar RRE_R0 "set secondary ASN" esa
+b233 ssch S_RD "start subchannel" esa
+b22b sske RRE_RR "set storage key extended" esa
+80 ssm S_RD "set system mask" esa
+50 st RX_RRRD "store" esa
+9b stam RS_AARD "store access multiple" esa
+b212 stap S_RD "store CPU address" esa
+42 stc RX_RRRD "store character" esa
+b205 stck S_RD "store clock" esa
+b207 stckc S_RD "store clock comparator" esa
+be stcm RS_RURD "store characters under mask" esa
+b23a stcps S_RD "store channel path status" esa
+b239 stcrw S_RD "store channel report word" esa
+b6 stctl RS_CCRD "store control" esa
+60 std RX_FRRD "store (long)" esa
+70 ste RX_FRRD "store (short)" esa
+40 sth RX_RRRD "store halfword" esa
+b202 stidp S_RD "store CPU id" esa
+90 stm RS_RRRD "store multiple" esa
+ac stnsm SI_URD "store then AND system mask" esa
+ad stosm SI_URD "store then OR system mask" esa
+b209 stpt S_RD "store CPU timer" esa
+b211 stpx S_RD "store prefix" esa
+b234 stsch S_RD "store subchannel" esa
+b246 stura RRE_RR "store using real address" esa
+7f su RX_FRRD "subtract unnormalized (short)" esa
+3f sur RR_FF "subtract unnormalized (short)" esa
+0a svc RR_U0 "supervisor call" esa
+6f sw RX_FRRD "subtract unnormalized (long)" esa
+2f swr RR_FF "subtract unnormalized (long)" esa
+37 sxr RR_FF "subtract normalized (ext.)" esa
b24c tar RRE_AR "test access" esa
-b22c tb RRE_R2 "test block" esa
-91 tm SI "test under mask" esa
-b236 tpi S "test pending interruption" esa
-e501 tprot SSE "test protection" esa
-dc tr SS_L "translate" esa
-99 trace RS "trace" esa
-dd trt SS_L "translate and test" esa
-93 ts S "test and set" esa
-b235 tsch S "test subchannel" esa
-f3 unpk SS_LL "unpack" esa
+b22c tb RRE_0R "test block" esa
+91 tm SI_URD "test under mask" esa
+b236 tpi S_RD "test pending interruption" esa
+e501 tprot SSE_RDRD "test protection" esa
+dc tr SS_L0RDRD "translate" esa
+99 trace RS_RRRD "trace" esa
+dd trt SS_L0RDRD "translate and test" esa
+93 ts S_RD "test and set" esa
+b235 tsch S_RD "test subchannel" esa
+f3 unpk SS_LLRDRD "unpack" esa
0102 upt E "update tree" esa
-57 x RX "exclusive OR" esa
-d7 xc SS_L "exclusive OR" esa
-97 xi SI "exclusive OR" esa
-17 xr RR "exclusive OR" esa
-f8 zap SS_LL "zero and add" esa
-a70a ahi RI "add halfword immediate" esa
-84 brxh RSI_A "branch relative on index high" esa
-85 brxle RSI_A "branch relative on index low or equal" esa
-a705 bras RI_A "branch relative and save" esa
-a704 brc RI_MA "branch relative on condition" esa
-a706 brct RI_A "branch relative on count" esa
-b241 cksm RRE "checksum" esa
-a70e chi RI "compare halfword immediate" esa
-a9 clcle RS "compare logical long extended" esa
-a708 lhi RI "load halfword immediate" esa
-a8 mvcle RS "move long extended" esa
-a70c mhi RI "multiply halfword immediate" esa
-b252 msr RRE "multiply single" esa
-71 ms RX "multiply single" esa
-a700 tmh RI_U "test under mask high" esa
-a701 tml RI_U "test under mask low" esa
-0700 nopr RR_B "no operation" esa
-0710 bor RR_B "branch on overflow / if ones" esa
-0720 bhr RR_B "branch on high" esa
-0720 bpr RR_B "branch on plus" esa
-0730 bnler RR_B "branch on not low or equal" esa
-0740 blr RR_B "branch on low" esa
-0740 bmr RR_B "branch on minus / if mixed" esa
-0750 bnher RR_B "branch on not high or equal" esa
-0760 blhr RR_B "branch on low or high" esa
-0770 bner RR_B "branch on not equal" esa
-0770 bnzr RR_B "branch on not zero / if not zeros" esa
-0780 ber RR_B "branch on equal" esa
-0780 bzr RR_B "branch on zero / if zeros" esa
-0790 bnlhr RR_B "branch on not low or high" esa
-07a0 bher RR_B "branch on high or equal" esa
-07b0 bnlr RR_B "branch on not low" esa
-07b0 bnmr RR_B "branch on not minus / if not mixed" esa
-07c0 bler RR_B "brach on low or equal" esa
-07d0 bnhr RR_B "branch on not high" esa
-07d0 bnpr RR_B "branch on not plus" esa
-07e0 bnor RR_B "branch on not overflow / if not ones" esa
-07f0 br RR_B "unconditional branch" esa
-4700 nop RX_B "no operation" esa
-4710 bo RX_B "branch on overflow / if ones" esa
-4720 bh RX_B "branch on high" esa
-4720 bp RX_B "branch on plus" esa
-4730 bnle RX_B "branch on not low or equal" esa
-4740 bl RX_B "branch on low" esa
-4740 bm RX_B "branch on minus / if mixed" esa
-4750 bnhe RX_B "branch on not high or equal" esa
-4760 blh RX_B "branch on low or high" esa
-4770 bne RX_B "branch on not equal" esa
-4770 bnz RX_B "branch on not zero / if not zeros" esa
-4780 be RX_B "branch on equal" esa
-4780 bz RX_B "branch on zero / if zeros" esa
-4790 bnlh RX_B "branch on not low or high" esa
-47a0 bhe RX_B "branch on high or equal" esa
-47b0 bnl RX_B "branch on not low" esa
-47b0 bnm RX_B "branch on not minus / if not mixed" esa
-47c0 ble RX_B "branch on low or equal" esa
-47d0 bnh RX_B "branch on not high" esa
-47d0 bnp RX_B "branch on not plus" esa
-47e0 bno RX_B "branch on not overflow / if not ones" esa
-47f0 b RX_B "unconditional branch" esa
-a714 jo RI_B "jump on overflow / if ones" esa
-a724 jh RI_B "jump on A high" esa
-a724 jp RI_B "jump on plus" esa
-a734 jnle RI_B "jump on not low or equal" esa
-a744 jl RI_B "jump on A low" esa
-a744 jm RI_B "jump on minus / if mixed" esa
-a754 jnhe RI_B "jump on not high or equal" esa
-a764 jlh RI_B "jump on low or high" esa
-a774 jne RI_B "jump on A not equal B" esa
-a774 jnz RI_B "jump on not zero / if not zeros" esa
-a784 je RI_B "jump on A equal B" esa
-a784 jz RI_B "jump on zero / if zeros" esa
-a794 jnlh RI_B "jump on not low or high" esa
-a7a4 jhe RI_B "jump on high or equal" esa
-a7b4 jnl RI_B "jump on A not low" esa
-a7b4 jnm RI_B "jump on not minus / if not mixed" esa
-a7c4 jle RI_B "jump on low or equal" esa
-a7d4 jnh RI_B "jump on A not high" esa
-a7d4 jnp RI_B "jump on not plus" esa
-a7e4 jno RI_B "jump on not overflow / if not ones" esa
-a7f4 j RI_B "jump" esa
-b34a axbr RRE_F "add extended bfp" esa
-b31a adbr RRE_F "add long bfp" esa
-ed000000001a adb RXE_F "add long bfp" esa
-b30a aebr RRE_F "add short bfp" esa
-ed000000000a aeb RXE_F "add short bfp" esa
-b349 cxbr RRE_F "compare extended bfp" esa
-b319 cdbr RRE_F "compare long bfp" esa
-ed0000000019 cdb RXE_F "compare long bfp" esa
-b309 cebr RRE_F "compare short bfp" esa
-ed0000000009 ceb RXE_F "compare short bfp" esa
-b348 kxbr RRE_F "compare and signal extended bfp" esa
-b318 kdbr RRE_F "compare and signal long bfp" esa
-ed0000000018 kdb RXE_F "compare and signal long bfp" esa
-b308 kebr RRE_F "compare and signal short bfp" esa
-ed0000000008 keb RXE_F "compare and signal short bfp" esa
-b396 cxfbr RRE_F "convert from fixed 32 to extended bfp" esa
-b395 cdfbr RRE_F "convert from fixed 32 to long bfp" esa
-b394 cefbr RRE_F "convert from fixed 32 to short bfp" esa
-b39a cfxbr RRF_M "convert to fixed extended bfp to 32" esa
-b399 cfdbr RRF_M "convert to fixed long bfp to 32" esa
-b398 cfebr RRF_M "convert to fixed short bfp to 32" esa
-b34d dxbr RRE_F "divide extended bfp" esa
-b31d ddbr RRE_F "divide long bfp" esa
-ed000000001d ddb RXE_F "divide long bfp" esa
-b30d debr RRE_F "divide short bfp" esa
-ed000000000d deb RXE_F "divide short bfp" esa
-b35b didbr RRF_RM "divide to integer long bfp" esa
-b353 diebr RRF_RM "divide to integer short bfp" esa
-b38c efpc RRE "extract fpc" esa
-b342 ltxbr RRE_F "load and test extended bfp" esa
-b312 ltdbr RRE_F "load and test long bfp" esa
-b302 ltebr RRE_F "load and test short bfp" esa
-b343 lcxbr RRE_F "load complement extended bfp" esa
-b313 lcdbr RRE_F "load complement long bfp" esa
-b303 lcebr RRE_F "load complement short bfp" esa
-b347 fixbr RRF_M "load fp integer extended bfp" esa
-b35f fidbr RRF_M "load fp integer long bfp" esa
-b357 fiebr RRF_M "load fp integer short bfp" esa
-b29d lfpc S "load fpc" esa
-b305 lxdbr RRE_F "load lengthened long to extended bfp" esa
-ed0000000005 lxdb RXE_F "load lengthened long to extended bfp" esa
-b306 lxebr RRE_F "load lengthened short to extended bfp" esa
-ed0000000006 lxeb RXE_F "load lengthened short to extended bfp" esa
-b304 ldebr RRE_F "load lengthened short to long bfp" esa
-ed0000000004 ldeb RXE_F "load lengthened short to long bfp" esa
-b341 lnxbr RRE_F "load negative extended bfp" esa
-b311 lndbr RRE_F "load negative long bfp" esa
-b301 lnebr RRE_F "load negative short bfp" esa
-b340 lpxbr RRE_F "load positive extended bfp" esa
-b310 lpdbr RRE_F "load positive long bfp" esa
-b300 lpebr RRE_F "load positive short bfp" esa
-b345 ldxbr RRE_F "load rounded extended to long bfp" esa
-b346 lexbr RRE_F "load rounded extended to short bfp" esa
-b344 ledbr RRE_F "load rounded long to short bfp" esa
-b34c mxbr RRE_F "multiply extended bfp" esa
-b31c mdbr RRE_F "multiply long bfp" esa
-ed000000001c mdb RXE_F "multiply long bfp" esa
-b307 mxdbr RRE_F "multiply long to extended bfp" esa
-ed0000000007 mxdb RXE_F "multiply long to extended bfp" esa
-b317 meebr RRE_F "multiply short bfp" esa
-ed0000000017 meeb RXE_F "multiply short bfp" esa
-b30c mdebr RRE_F "multiply short to long bfp" esa
-ed000000000c mdeb RXE_F "multiply short to long bfp" esa
-b31e madbr RRF_R "multiply and add long bfp" esa
-ed000000001e madb RXF "multiply and add long bfp" esa
-b30e maebr RRF_R "multiply and add short bfp" esa
-ed000000000e maeb RXF "multiply and add short bfp" esa
-b31f msdbr RRF_R "multiply and subtract long bfp" esa
-ed000000001f msdb RXF "multiply and subtract long bfp" esa
-b30f msebr RRF_R "multiply and subtract short bfp" esa
-ed000000000f mseb RXF "multiply and subtract short bfp" esa
-b384 sfpc RRE "set fpc" esa
-b299 srnm S "set rounding mode" esa
-b316 sqxbr RRE_F "square root extended bfp" esa
-b315 sqdbr RRE_F "square root long bfp" esa
-ed0000000015 sqdb RXE_F "square root long bfp" esa
-b314 sqebr RRE_F "square root short bfp" esa
-ed0000000014 sqeb RXE_F "square root short bfp" esa
-b29c stfpc S "store fpc" esa
-b34b sxbr RRE_F "subtract extended bfp" esa
-b31b sdbr RRE_F "subtract long bfp" esa
-ed000000001b sdb RXE_F "subtract long bfp" esa
-b30b sebr RRE_F "subtract short bfp" esa
-ed000000000b seb RXE_F "subtract short bfp" esa
-ed0000000012 tcxb RXE_F "test data class extended bfp" esa
-ed0000000011 tcdb RXE_F "test data class long bfp" esa
-ed0000000010 tceb RXE_F "test data class short bfp" esa
-b274 siga S "signal adapter" esa
+57 x RX_RRRD "exclusive OR" esa
+d7 xc SS_L0RDRD "exclusive OR" esa
+97 xi SI_URD "exclusive OR" esa
+17 xr RR_RR "exclusive OR" esa
+f8 zap SS_LLRDRD "zero and add" esa
+a70a ahi RI_RI "add halfword immediate" esa
+84 brxh RSI_RRP "branch relative on index high" esa
+85 brxle RSI_RRP "branch relative on index low or equal" esa
+a705 bras RI_RP "branch relative and save" esa
+a704 brc RI_UP "branch relative on condition" esa
+a706 brct RI_RP "branch relative on count" esa
+b241 cksm RRE_RR "checksum" esa
+a70e chi RI_RI "compare halfword immediate" esa
+a9 clcle RS_RRRD "compare logical long extended" esa
+a708 lhi RI_RI "load halfword immediate" esa
+a8 mvcle RS_RRRD "move long extended" esa
+a70c mhi RI_RI "multiply halfword immediate" esa
+b252 msr RRE_RR "multiply single" esa
+71 ms RX_RRRD "multiply single" esa
+a700 tmh RI_RU "test under mask high" esa
+a701 tml RI_RU "test under mask low" esa
+0700 nopr RR_0R "no operation" esa
+0710 bor RR_0R "branch on overflow / if ones" esa
+0720 bhr RR_0R "branch on high" esa
+0720 bpr RR_0R "branch on plus" esa
+0730 bnler RR_0R "branch on not low or equal" esa
+0740 blr RR_0R "branch on low" esa
+0740 bmr RR_0R "branch on minus / if mixed" esa
+0750 bnher RR_0R "branch on not high or equal" esa
+0760 blhr RR_0R "branch on low or high" esa
+0770 bner RR_0R "branch on not equal" esa
+0770 bnzr RR_0R "branch on not zero / if not zeros" esa
+0780 ber RR_0R "branch on equal" esa
+0780 bzr RR_0R "branch on zero / if zeros" esa
+0790 bnlhr RR_0R "branch on not low or high" esa
+07a0 bher RR_0R "branch on high or equal" esa
+07b0 bnlr RR_0R "branch on not low" esa
+07b0 bnmr RR_0R "branch on not minus / if not mixed" esa
+07c0 bler RR_0R "brach on low or equal" esa
+07d0 bnhr RR_0R "branch on not high" esa
+07d0 bnpr RR_0R "branch on not plus" esa
+07e0 bnor RR_0R "branch on not overflow / if not ones" esa
+07f0 br RR_0R "unconditional branch" esa
+4700 nop RX_0RRD "no operation" esa
+4710 bo RX_0RRD "branch on overflow / if ones" esa
+4720 bh RX_0RRD "branch on high" esa
+4720 bp RX_0RRD "branch on plus" esa
+4730 bnle RX_0RRD "branch on not low or equal" esa
+4740 bl RX_0RRD "branch on low" esa
+4740 bm RX_0RRD "branch on minus / if mixed" esa
+4750 bnhe RX_0RRD "branch on not high or equal" esa
+4760 blh RX_0RRD "branch on low or high" esa
+4770 bne RX_0RRD "branch on not equal" esa
+4770 bnz RX_0RRD "branch on not zero / if not zeros" esa
+4780 be RX_0RRD "branch on equal" esa
+4780 bz RX_0RRD "branch on zero / if zeros" esa
+4790 bnlh RX_0RRD "branch on not low or high" esa
+47a0 bhe RX_0RRD "branch on high or equal" esa
+47b0 bnl RX_0RRD "branch on not low" esa
+47b0 bnm RX_0RRD "branch on not minus / if not mixed" esa
+47c0 ble RX_0RRD "branch on low or equal" esa
+47d0 bnh RX_0RRD "branch on not high" esa
+47d0 bnp RX_0RRD "branch on not plus" esa
+47e0 bno RX_0RRD "branch on not overflow / if not ones" esa
+47f0 b RX_0RRD "unconditional branch" esa
+a714 jo RI_0P "jump on overflow / if ones" esa
+a724 jh RI_0P "jump on A high" esa
+a724 jp RI_0P "jump on plus" esa
+a734 jnle RI_0P "jump on not low or equal" esa
+a744 jl RI_0P "jump on A low" esa
+a744 jm RI_0P "jump on minus / if mixed" esa
+a754 jnhe RI_0P "jump on not high or equal" esa
+a764 jlh RI_0P "jump on low or high" esa
+a774 jne RI_0P "jump on A not equal B" esa
+a774 jnz RI_0P "jump on not zero / if not zeros" esa
+a784 je RI_0P "jump on A equal B" esa
+a784 jz RI_0P "jump on zero / if zeros" esa
+a794 jnlh RI_0P "jump on not low or high" esa
+a7a4 jhe RI_0P "jump on high or equal" esa
+a7b4 jnl RI_0P "jump on A not low" esa
+a7b4 jnm RI_0P "jump on not minus / if not mixed" esa
+a7c4 jle RI_0P "jump on low or equal" esa
+a7d4 jnh RI_0P "jump on A not high" esa
+a7d4 jnp RI_0P "jump on not plus" esa
+a7e4 jno RI_0P "jump on not overflow / if not ones" esa
+a7f4 j RI_0P "jump" esa
+b34a axbr RRE_FF "add extended bfp" esa
+b31a adbr RRE_FF "add long bfp" esa
+ed000000001a adb RXE_FRRD "add long bfp" esa
+b30a aebr RRE_FF "add short bfp" esa
+ed000000000a aeb RXE_FRRD "add short bfp" esa
+b349 cxbr RRE_FF "compare extended bfp" esa
+b319 cdbr RRE_FF "compare long bfp" esa
+ed0000000019 cdb RXE_FRRD "compare long bfp" esa
+b309 cebr RRE_FF "compare short bfp" esa
+ed0000000009 ceb RXE_FRRD "compare short bfp" esa
+b348 kxbr RRE_FF "compare and signal extended bfp" esa
+b318 kdbr RRE_FF "compare and signal long bfp" esa
+ed0000000018 kdb RXE_FRRD "compare and signal long bfp" esa
+b308 kebr RRE_FF "compare and signal short bfp" esa
+ed0000000008 keb RXE_FRRD "compare and signal short bfp" esa
+b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" esa
+b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" esa
+b394 cefbr RRE_RF "convert from fixed 32 to short bfp" esa
+b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" esa
+b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" esa
+b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" esa
+b34d dxbr RRE_FF "divide extended bfp" esa
+b31d ddbr RRE_FF "divide long bfp" esa
+ed000000001d ddb RXE_FRRD "divide long bfp" esa
+b30d debr RRE_FF "divide short bfp" esa
+ed000000000d deb RXE_FRRD "divide short bfp" esa
+b35b didbr RRF_FUFF "divide to integer long bfp" esa
+b353 diebr RRF_FUFF "divide to integer short bfp" esa
+b38c efpc RRE_RR "extract fpc" esa
+b342 ltxbr RRE_FF "load and test extended bfp" esa
+b312 ltdbr RRE_FF "load and test long bfp" esa
+b302 ltebr RRE_FF "load and test short bfp" esa
+b343 lcxbr RRE_FF "load complement extended bfp" esa
+b313 lcdbr RRE_FF "load complement long bfp" esa
+b303 lcebr RRE_FF "load complement short bfp" esa
+b347 fixbr RRF_U0FF "load fp integer extended bfp" esa
+b35f fidbr RRF_U0FF "load fp integer long bfp" esa
+b357 fiebr RRF_U0FF "load fp integer short bfp" esa
+b29d lfpc S_RD "load fpc" esa
+b305 lxdbr RRE_FF "load lengthened long to extended bfp" esa
+ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" esa
+b306 lxebr RRE_FF "load lengthened short to extended bfp" esa
+ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" esa
+b304 ldebr RRE_FF "load lengthened short to long bfp" esa
+ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" esa
+b341 lnxbr RRE_FF "load negative extended bfp" esa
+b311 lndbr RRE_FF "load negative long bfp" esa
+b301 lnebr RRE_FF "load negative short bfp" esa
+b340 lpxbr RRE_FF "load positive extended bfp" esa
+b310 lpdbr RRE_FF "load positive long bfp" esa
+b300 lpebr RRE_FF "load positive short bfp" esa
+b345 ldxbr RRE_FF "load rounded extended to long bfp" esa
+b346 lexbr RRE_FF "load rounded extended to short bfp" esa
+b344 ledbr RRE_FF "load rounded long to short bfp" esa
+b34c mxbr RRE_FF "multiply extended bfp" esa
+b31c mdbr RRE_FF "multiply long bfp" esa
+ed000000001c mdb RXE_FRRD "multiply long bfp" esa
+b307 mxdbr RRE_FF "multiply long to extended bfp" esa
+ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" esa
+b317 meebr RRE_FF "multiply short bfp" esa
+ed0000000017 meeb RXE_FRRD "multiply short bfp" esa
+b30c mdebr RRE_FF "multiply short to long bfp" esa
+ed000000000c mdeb RXE_FRRD "multiply short to long bfp" esa
+b31e madbr RRF_F0FF "multiply and add long bfp" esa
+ed000000001e madb RXF_FRRDF "multiply and add long bfp" esa
+b30e maebr RRF_F0FF "multiply and add short bfp" esa
+ed000000000e maeb RXF_FRRDF "multiply and add short bfp" esa
+b31f msdbr RRF_F0FF "multiply and subtract long bfp" esa
+ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" esa
+b30f msebr RRF_F0FF "multiply and subtract short bfp" esa
+ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" esa
+b384 sfpc RRE_RR "set fpc" esa
+b299 srnm S_RD "set rounding mode" esa
+b316 sqxbr RRE_FF "square root extended bfp" esa
+b315 sqdbr RRE_FF "square root long bfp" esa
+ed0000000015 sqdb RXE_FRRD "square root long bfp" esa
+b314 sqebr RRE_FF "square root short bfp" esa
+ed0000000014 sqeb RXE_FRRD "square root short bfp" esa
+b29c stfpc S_RD "store fpc" esa
+b34b sxbr RRE_FF "subtract extended bfp" esa
+b31b sdbr RRE_FF "subtract long bfp" esa
+ed000000001b sdb RXE_FRRD "subtract long bfp" esa
+b30b sebr RRE_FF "subtract short bfp" esa
+ed000000000b seb RXE_FRRD "subtract short bfp" esa
+ed0000000012 tcxb RXE_FRRD "test data class extended bfp" esa
+ed0000000011 tcdb RXE_FRRD "test data class long bfp" esa
+ed0000000010 tceb RXE_FRRD "test data class short bfp" esa
+b274 siga S_RD "signal adapter" esa
# are the following instructions confidential ??
-b2a6 cuutf RRE "convert unicode to utf-8" esa
-b2a7 cutfu RRE "convert utf-8 to unicode" esa
-ee plo SS_PLO "perform locked operation" esa
-b25a bsa RRE "branch and set authority" esa
-b277 rp S "resume program" esa
+b2a6 cuutf RRE_RR "convert unicode to utf-8" esa
+b2a7 cutfu RRE_RR "convert utf-8 to unicode" esa
+ee plo SS_RRRDRD2 "perform locked operation" esa
+b25a bsa RRE_RR "branch and set authority" esa
+b277 rp S_RD "resume program" esa
0107 sckpf E "set clock programmable field" esa
-b27d stsi S "store system information" esa
+b27d stsi S_RD "store system information" esa
01ff trap2 E "trap" esa
-b2ff trap4 S "trap4" esa
+b2ff trap4 S_RD "trap4" esa
# Here are the new esame instructions:
-b946 bctgr RRE "branch on count 64" esame
-b900 lpgr RRE "load positive 64" esame
-b910 lpgfr RRE "load positive 64<32" esame
-b901 lngr RRE "load negative 64" esame
-b911 lngfr RRE "load negative 64<32" esame
-b902 ltgr RRE "load and test 64" esame
-b912 ltgfr RRE "load and test 64<32" esame
-b903 lcgr RRE "load complement 64" esame
-b913 lcgfr RRE "load complement 64<32" esame
-b980 ngr RRE "and 64" esame
-b921 clgr RRE "compare logical 64" esame
-b931 clgfr RRE "compare logical 64<32" esame
-b981 ogr RRE "or 64" esame
-b982 xgr RRE "exclusive or 64" esame
-b904 lgr RRE "load 64" esame
-b914 lgfr RRE "load 64<32" esame
-b920 cgr RRE "compare 64" esame
-b930 cgfr RRE "compare 64<32" esame
-b908 agr RRE "add 64" esame
-b918 agfr RRE "add 64<32" esame
-b909 sgr RRE "subtract 64" esame
-b919 sgfr RRE "subtract 64<32" esame
-b90a algr RRE "add logical 64" esame
-b91a algfr RRE "add logical 64<32" esame
-b90b slgr RRE "subtract logical 64" esame
-b91b slgfr RRE "subtract logical 64<32" esame
-e30000000046 bctg RXE "branch on count 64" esame
-e3000000002e cvdg RXE "convert to decimal 64" esame
-e3000000000e cvbg RXE "convert to binary 64" esame
-e30000000024 stg RXE "store 64" esame
-e30000000080 ng RXE "and 64" esame
-e30000000021 clg RXE "compare logical 64" esame
-e30000000031 clgf RXE "comparee logical 64<32" esame
-e30000000081 og RXE "or 64" esame
-e30000000082 xg RXE "exclusive or 64" esame
-e30000000004 lg RXE "load 64" esame
-e30000000014 lgf RXE "load 64<32" esame
-e30000000015 lgh RXE "load halfword 64" esame
-e30000000020 cg RXE "compare 64" esame
-e30000000030 cgf RXE "compare 64<32" esame
-e30000000008 ag RXE "add 64" esame
-e30000000018 agf RXE "add 64<32" esame
-e30000000009 sg RXE "subtract 64" esame
-e30000000019 sgf RXE "subtract 64<32" esame
-e3000000000a alg RXE "add logical 64" esame
-e3000000001a algf RXE "add logical 64<32" esame
-e3000000000b slg RXE "subtract logical 64" esame
-e3000000001b slgf RXE "subtract logical 64<32" esame
-e3000000000c msg RXE "multiply single 64" esame
-e3000000001c msgf RXE "multiply single 64<32" esame
-ec0000000044 brxhg RIE_A "branch relative on index high 64" esame
-ec0000000045 brxlg RIE_A "branch relative on index low or equal 64" esame
-eb0000000044 bxhg RSE_R "branch on index high 64" esame
-eb0000000045 bxleg RSE_R "branch on index low or equal 64" esame
-eb000000000c srlg RSE_R "shift right single logical 64" esame
-eb000000000d sllg RSE_R "shift left single logical 64" esame
-eb000000000a srag RSE_R "shift right single 64" esame
-eb000000000b slag RSE_R "shift left single 64" esame
-eb0000000024 stmg RSE_R "store multiple 64" esame
-eb0000000026 stmh RSE_R "store multiple high" esame
-eb0000000004 lmg RSE_R "load multiple 64" esame
-eb0000000096 lmh RSE_R "load multiple high" esame
-ef lmd SS_LMD "load multiple disjoint" esame
-eb000000000f tracg RSE_R "trace 64" esame
-e30000000003 lrag RXE "load real address 64" esame
-e50000000002 strag SSE "store read address" esame
-eb0000000025 stctg RSE_R "store control 64" esame
-eb000000002f lctlg RSE_R "load control 64" esame
-eb0000000030 csg RSE_R "compare and swap 64" esame
-eb000000003e cdsg RSE_R "compare double and swap 64" esame
-eb0000000020 clmh RSE_M "compare logical characters under mask high" esame
-eb000000002c stcmh RSE_M "store characters under mask high" esame
-eb0000000080 icmh RSE_M "insert characters under mask high" esame
-a700 tmlh RI_U "test under mask low high" esame
-a702 tmhh RI_U "test under mask high high" esame
-a701 tmll RI_U "test under mask low low" esame
-a703 tmhl RI_U "test under mask high low" esame
-c004 brcl RIL_MA "branch relative on condition long" esame
-c014 jgo RIL_B "jump long on overflow / if ones" esame
-c024 jgh RIL_B "jump long on high" esame
-c024 jgp RIL_B "jump long on plus" esame
-c034 jgnle RIL_B "jump long on not low or equal" esame
-c044 jgl RIL_B "jump long on low" esame
-c044 jgm RIL_B "jump long on minus / if mixed" esame
-c054 jgnhe RIL_B "jump long on not high or equal" esame
-c064 jglh RIL_B "jump long on low or high" esame
-c074 jgne RIL_B "jump long on not equal" esame
-c074 jgnz RIL_B "jump long on not zero / if not zeros" esame
-c084 jge RIL_B "jump long on equal" esame
-c084 jgz RIL_B "jump long on zero / if zeros" esame
-c094 jgnlh RIL_B "jump long on not low or high" esame
-c0a4 jghe RIL_B "jump long on high or equal" esame
-c0b4 jgnl RIL_B "jump long on not low" esame
-c0b4 jgnm RIL_B "jump long on not minus / if not mixed" esame
-c0c4 jgle RIL_B "jump long on low or equal" esame
-c0d4 jgnh RIL_B "jump long on not high" esame
-c0d4 jgnp RIL_B "jump long on not plus" esame
-c0e4 jgno RIL_B "jump long on not overflow / if not ones" esame
-c0f4 jg RIL_B "jump long" esame
-c005 brasl RIL_A "branch relative and save long" esame
-a707 brctg RI_A "branch relative on count 64" esame
-a709 lghi RI "load halfword immediate 64" esame
-a70b aghi RI "add halfword immediate 64" esame
-a70d mghi RI "multiply halfword immediate 64" esame
-a70f cghi RI "compare halfword immediate 64" esame
-b925 sturg RRE "store using real address 64" esame
-b90e eregg RRE "extract stacked registers 64" esame
-b905 lurag RRE "load using real address 64" esame
-b90c msgr RRE "multiply single 64" esame
-b91c msgfr RRE "multiply single 64<32" esame
-b3a4 cegbr RRE "convert from fixed 64 to short bfp" esame
-b3a5 cdgbr RRE "convert from fixed 64 to long bfp" esame
-b3a6 cxgbr RRE "convert from fixed 64 to extended bfp" esame
-b3a8 cgebr RRF_M "convert to fixed short bfd to 64" esame
-b3a9 cgdbr RRF_M "convert to fixed long bfp to 64" esame
-b3aa cgxbr RRF_M "convert to fixed extended bfp to 64" esame
-b3c4 cegr RRE "convert from fixed 64 to short hfp" esame
-b3c5 cdgr RRE "convert from fixed 64 to long hfp" esame
-b3c6 cxgr RRE "convert from fixed 64 to extended hfp" esame
-b3c8 cger RRF_F "convert to fixed short hfp to 64" esame
-b3c9 cgdr RRF_F "convert to fixed long hfp to 64" esame
-b3ca cgxr RRF_F "convert to fixed extended hfp to 64" esame
+b946 bctgr RRE_RR "branch on count 64" esame
+b900 lpgr RRE_RR "load positive 64" esame
+b910 lpgfr RRE_RR "load positive 64<32" esame
+b901 lngr RRE_RR "load negative 64" esame
+b911 lngfr RRE_RR "load negative 64<32" esame
+b902 ltgr RRE_RR "load and test 64" esame
+b912 ltgfr RRE_RR "load and test 64<32" esame
+b903 lcgr RRE_RR "load complement 64" esame
+b913 lcgfr RRE_RR "load complement 64<32" esame
+b980 ngr RRE_RR "and 64" esame
+b921 clgr RRE_RR "compare logical 64" esame
+b931 clgfr RRE_RR "compare logical 64<32" esame
+b981 ogr RRE_RR "or 64" esame
+b982 xgr RRE_RR "exclusive or 64" esame
+b904 lgr RRE_RR "load 64" esame
+b914 lgfr RRE_RR "load 64<32" esame
+b920 cgr RRE_RR "compare 64" esame
+b930 cgfr RRE_RR "compare 64<32" esame
+b908 agr RRE_RR "add 64" esame
+b918 agfr RRE_RR "add 64<32" esame
+b909 sgr RRE_RR "subtract 64" esame
+b919 sgfr RRE_RR "subtract 64<32" esame
+b90a algr RRE_RR "add logical 64" esame
+b91a algfr RRE_RR "add logical 64<32" esame
+b90b slgr RRE_RR "subtract logical 64" esame
+b91b slgfr RRE_RR "subtract logical 64<32" esame
+e30000000046 bctg RXE_RRRD "branch on count 64" esame
+e3000000002e cvdg RXE_RRRD "convert to decimal 64" esame
+e3000000000e cvbg RXE_RRRD "convert to binary 64" esame
+e30000000024 stg RXE_RRRD "store 64" esame
+e30000000080 ng RXE_RRRD "and 64" esame
+e30000000021 clg RXE_RRRD "compare logical 64" esame
+e30000000031 clgf RXE_RRRD "comparee logical 64<32" esame
+e30000000081 og RXE_RRRD "or 64" esame
+e30000000082 xg RXE_RRRD "exclusive or 64" esame
+e30000000004 lg RXE_RRRD "load 64" esame
+e30000000014 lgf RXE_RRRD "load 64<32" esame
+e30000000015 lgh RXE_RRRD "load halfword 64" esame
+e30000000020 cg RXE_RRRD "compare 64" esame
+e30000000030 cgf RXE_RRRD "compare 64<32" esame
+e30000000008 ag RXE_RRRD "add 64" esame
+e30000000018 agf RXE_RRRD "add 64<32" esame
+e30000000009 sg RXE_RRRD "subtract 64" esame
+e30000000019 sgf RXE_RRRD "subtract 64<32" esame
+e3000000000a alg RXE_RRRD "add logical 64" esame
+e3000000001a algf RXE_RRRD "add logical 64<32" esame
+e3000000000b slg RXE_RRRD "subtract logical 64" esame
+e3000000001b slgf RXE_RRRD "subtract logical 64<32" esame
+e3000000000c msg RXE_RRRD "multiply single 64" esame
+e3000000001c msgf RXE_RRRD "multiply single 64<32" esame
+ec0000000044 brxhg RIE_RRP "branch relative on index high 64" esame
+ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" esame
+eb0000000044 bxhg RSE_RRRD "branch on index high 64" esame
+eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" esame
+eb000000000c srlg RSE_RRRD "shift right single logical 64" esame
+eb000000000d sllg RSE_RRRD "shift left single logical 64" esame
+eb000000000a srag RSE_RRRD "shift right single 64" esame
+eb000000000b slag RSE_RRRD "shift left single 64" esame
+eb0000000024 stmg RSE_RRRD "store multiple 64" esame
+eb0000000026 stmh RSE_RRRD "store multiple high" esame
+eb0000000004 lmg RSE_RRRD "load multiple 64" esame
+eb0000000096 lmh RSE_RRRD "load multiple high" esame
+ef lmd SS_RRRDRD3 "load multiple disjoint" esame
+eb000000000f tracg RSE_RRRD "trace 64" esame
+e30000000003 lrag RXE_RRRD "load real address 64" esame
+e50000000002 strag SSE_RDRD "store read address" esame
+eb0000000025 stctg RSE_RRRD "store control 64" esame
+eb000000002f lctlg RSE_RRRD "load control 64" esame
+eb0000000030 csg RSE_RRRD "compare and swap 64" esame
+eb000000003e cdsg RSE_RRRD "compare double and swap 64" esame
+eb0000000020 clmh RSE_RURD "compare logical characters under mask high" esame
+eb000000002c stcmh RSE_RURD "store characters under mask high" esame
+eb0000000080 icmh RSE_RURD "insert characters under mask high" esame
+a700 tmlh RI_RU "test under mask low high" esame
+a702 tmhh RI_RU "test under mask high high" esame
+a701 tmll RI_RU "test under mask low low" esame
+a703 tmhl RI_RU "test under mask high low" esame
+c004 brcl RIL_UP "branch relative on condition long" esame
+c014 jgo RIL_0P "jump long on overflow / if ones" esame
+c024 jgh RIL_0P "jump long on high" esame
+c024 jgp RIL_0P "jump long on plus" esame
+c034 jgnle RIL_0P "jump long on not low or equal" esame
+c044 jgl RIL_0P "jump long on low" esame
+c044 jgm RIL_0P "jump long on minus / if mixed" esame
+c054 jgnhe RIL_0P "jump long on not high or equal" esame
+c064 jglh RIL_0P "jump long on low or high" esame
+c074 jgne RIL_0P "jump long on not equal" esame
+c074 jgnz RIL_0P "jump long on not zero / if not zeros" esame
+c084 jge RIL_0P "jump long on equal" esame
+c084 jgz RIL_0P "jump long on zero / if zeros" esame
+c094 jgnlh RIL_0P "jump long on not low or high" esame
+c0a4 jghe RIL_0P "jump long on high or equal" esame
+c0b4 jgnl RIL_0P "jump long on not low" esame
+c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" esame
+c0c4 jgle RIL_0P "jump long on low or equal" esame
+c0d4 jgnh RIL_0P "jump long on not high" esame
+c0d4 jgnp RIL_0P "jump long on not plus" esame
+c0e4 jgno RIL_0P "jump long on not overflow / if not ones" esame
+c0f4 jg RIL_0P "jump long" esame
+c005 brasl RIL_RP "branch relative and save long" esame
+a707 brctg RI_RP "branch relative on count 64" esame
+a709 lghi RI_RI "load halfword immediate 64" esame
+a70b aghi RI_RI "add halfword immediate 64" esame
+a70d mghi RI_RI "multiply halfword immediate 64" esame
+a70f cghi RI_RI "compare halfword immediate 64" esame
+b925 sturg RRE_RR "store using real address 64" esame
+b90e eregg RRE_RR "extract stacked registers 64" esame
+b905 lurag RRE_RR "load using real address 64" esame
+b90c msgr RRE_RR "multiply single 64" esame
+b91c msgfr RRE_RR "multiply single 64<32" esame
+b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" esame
+b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" esame
+b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" esame
+b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" esame
+b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" esame
+b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" esame
+b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" esame
+b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" esame
+b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" esame
+b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" esame
+b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" esame
+b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" esame
010b tam E "test addressing mode" esame
010c sam24 E "set addressing mode 24" esame
010d sam31 E "set addressing mode 31" esame
010e sam64 E "set addressing mode 64" esame
-a500 iihh RI_U "insert immediate high high" esame
-a501 iihl RI_U "insert immediate high low" esame
-a502 iilh RI_U "insert immediate low high" esame
-a503 iill RI_U "insert immediate low low" esame
-a504 nihh RI_U "and immediate high high" esame
-a505 nihl RI_U "and immediate high low" esame
-a506 nilh RI_U "and immediate low high" esame
-a507 nill RI_U "and immediate low low" esame
-a508 oihh RI_U "or immediate high high" esame
-a509 oihl RI_U "or immediate high low" esame
-a50a oilh RI_U "or immediate low high" esame
-a50b oill RI_U "or immediate low low" esame
-a50c llihh RI_U "load logical immediate high high" esame
-a50d llihl RI_U "load logical immediate high low" esame
-a50e llilh RI_U "load logical immediate low high" esame
-a50f llill RI_U "load logical immediate low low" esame
-b2b1 stfl S "store facility list" esame
-b2b2 lpswe S "load psw extended" esame
-b90d dsgr RRE "divide single 64" esame
-b90f lrvgr RRE "load reversed 64" esame
-b916 llgfr RRE "load logical 64<32" esame
-b917 llgtr RRE "load logical thirty one bits" esame
-b91d dsgfr RRE "divide single 64<32" esame
-b91f lrvr RRE "load reversed 32" esame
-b986 mlgr RRE "multiply logical 64" esame
-b987 dlgr RRE "divide logical 64" esame
-b988 alcgr RRE "add logical with carry 64" esame
-b989 slbgr RRE "subtract logical with borrow 64" esame
-b98d epsw RRE "extract psw" esame
-b996 mlr RRE "multiply logical 32" esame
-b997 dlr RRE "divide logical 32" esame
-b998 alcr RRE "add logical with carry 32" esame
-b999 slbr RRE "subtract logical with borrow 32" esame
-b99d esea RRE_R "extract and set extended authority" esame
-c000 larl RIL_A "load address relative long" esame
-e3000000000d dsg RXE "divide single 64" esame
-e3000000000f lrvg RXE "load reversed 64" esame
-e30000000016 llgf RXE "load logical 64<32" esame
-e30000000017 llgt RXE "load logical thirty one bits" esame
-e3000000001d dsgf RXE "divide single 64<32" esame
-e3000000001e lrv RXE "load reversed 32" esame
-e3000000001f lrvh RXE "load reversed 16" esame
-e3000000002f strvg RXE "store reversed 64" esame
-e3000000003e strv RXE "store reversed 32" esame
-e3000000003f strvh RXE "store reversed 64" esame
-e30000000086 mlg RXE "multiply logical 64" esame
-e30000000087 dlg RXE "divide logical 64" esame
-e30000000088 alcg RXE "add logical with carry 64" esame
-e30000000089 slbg RXE "subtract logical with borrow 64" esame
-e3000000008e stpq RXE "store pair to quadword" esame
-e3000000008f lpq RXE "load pair from quadword" esame
-e30000000096 ml RXE "multiply logical 32" esame
-e30000000097 dl RXE "divide logical 32" esame
-e30000000098 alc RXE "add logical with carry 32" esame
-e30000000099 slb RXE "subtract logical with borrow 32" esame
-e30000000090 llgc RXE "load logical character" esame
-e30000000091 llgh RXE "load logical halfword" esame
-eb000000001c rllg RSE_R "rotate left single logical 64" esame
-eb000000001d rll RSE_R "rotate left single logical 32" esame
-b278 stcke S "store clock extended" esame
-b2a5 tre RRE "translate extended" esame
-eb000000008e mvclu RSE_R "move long unicode" esame
-e9 pka SS_L "pack ascii" esame
-e1 pku SS_L "pack unicode" esame
-b993 troo RRE "translate one to one" esame
-b992 trot RRE "translate one to two" esame
-b991 trto RRE "translate two to one" esame
-b990 trtt RRE "translate two to two" esame
-ea unpka SS_L "unpack ascii" esame
-e2 unpku SS_L "unpack unicode" esame
-b358 thder RRE "convert short bfp to long hfp" esame
-b359 thdr RRE "convert long bfp to long hfp" esame
-b350 tbedr RRF_M "convert long hfp to short bfp" esame
-b351 tbdr RRF_M "convert long hfp to long bfp" esame
-b374 lzer RRE_R "load short zero" esame
-b375 lzdr RRE_R "load long zero" esame
-b376 lzxr RRE_R "load extended zero" esame
+a500 iihh RI_RU "insert immediate high high" esame
+a501 iihl RI_RU "insert immediate high low" esame
+a502 iilh RI_RU "insert immediate low high" esame
+a503 iill RI_RU "insert immediate low low" esame
+a504 nihh RI_RU "and immediate high high" esame
+a505 nihl RI_RU "and immediate high low" esame
+a506 nilh RI_RU "and immediate low high" esame
+a507 nill RI_RU "and immediate low low" esame
+a508 oihh RI_RU "or immediate high high" esame
+a509 oihl RI_RU "or immediate high low" esame
+a50a oilh RI_RU "or immediate low high" esame
+a50b oill RI_RU "or immediate low low" esame
+a50c llihh RI_RU "load logical immediate high high" esame
+a50d llihl RI_RU "load logical immediate high low" esame
+a50e llilh RI_RU "load logical immediate low high" esame
+a50f llill RI_RU "load logical immediate low low" esame
+b2b1 stfl S_RD "store facility list" esame
+b2b2 lpswe S_RD "load psw extended" esame
+b90d dsgr RRE_RR "divide single 64" esame
+b90f lrvgr RRE_RR "load reversed 64" esame
+b916 llgfr RRE_RR "load logical 64<32" esame
+b917 llgtr RRE_RR "load logical thirty one bits" esame
+b91d dsgfr RRE_RR "divide single 64<32" esame
+b91f lrvr RRE_RR "load reversed 32" esame
+b986 mlgr RRE_RR "multiply logical 64" esame
+b987 dlgr RRE_RR "divide logical 64" esame
+b988 alcgr RRE_RR "add logical with carry 64" esame
+b989 slbgr RRE_RR "subtract logical with borrow 64" esame
+b98d epsw RRE_RR "extract psw" esame
+b996 mlr RRE_RR "multiply logical 32" esame
+b997 dlr RRE_RR "divide logical 32" esame
+b998 alcr RRE_RR "add logical with carry 32" esame
+b999 slbr RRE_RR "subtract logical with borrow 32" esame
+b99d esea RRE_R0 "extract and set extended authority" esame
+c000 larl RIL_RP "load address relative long" esame
+e3000000000d dsg RXE_RRRD "divide single 64" esame
+e3000000000f lrvg RXE_RRRD "load reversed 64" esame
+e30000000016 llgf RXE_RRRD "load logical 64<32" esame
+e30000000017 llgt RXE_RRRD "load logical thirty one bits" esame
+e3000000001d dsgf RXE_RRRD "divide single 64<32" esame
+e3000000001e lrv RXE_RRRD "load reversed 32" esame
+e3000000001f lrvh RXE_RRRD "load reversed 16" esame
+e3000000002f strvg RXE_RRRD "store reversed 64" esame
+e3000000003e strv RXE_RRRD "store reversed 32" esame
+e3000000003f strvh RXE_RRRD "store reversed 64" esame
+e30000000086 mlg RXE_RRRD "multiply logical 64" esame
+e30000000087 dlg RXE_RRRD "divide logical 64" esame
+e30000000088 alcg RXE_RRRD "add logical with carry 64" esame
+e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" esame
+e3000000008e stpq RXE_RRRD "store pair to quadword" esame
+e3000000008f lpq RXE_RRRD "load pair from quadword" esame
+e30000000096 ml RXE_RRRD "multiply logical 32" esame
+e30000000097 dl RXE_RRRD "divide logical 32" esame
+e30000000098 alc RXE_RRRD "add logical with carry 32" esame
+e30000000099 slb RXE_RRRD "subtract logical with borrow 32" esame
+e30000000090 llgc RXE_RRRD "load logical character" esame
+e30000000091 llgh RXE_RRRD "load logical halfword" esame
+eb000000001c rllg RSE_RRRD "rotate left single logical 64" esame
+eb000000001d rll RSE_RRRD "rotate left single logical 32" esame
+b278 stcke S_RD "store clock extended" esame
+b2a5 tre RRE_RR "translate extended" esame
+eb000000008e mvclu RSE_RRRD "move long unicode" esame
+e9 pka SS_L0RDRD "pack ascii" esame
+e1 pku SS_L0RDRD "pack unicode" esame
+b993 troo RRE_RR "translate one to one" esame
+b992 trot RRE_RR "translate one to two" esame
+b991 trto RRE_RR "translate two to one" esame
+b990 trtt RRE_RR "translate two to two" esame
+ea unpka SS_L0RDRD "unpack ascii" esame
+e2 unpku SS_L0RDRD "unpack unicode" esame
+b358 thder RRE_RR "convert short bfp to long hfp" esame
+b359 thdr RRE_RR "convert long bfp to long hfp" esame
+b350 tbedr RRF_U0FF "convert long hfp to short bfp" esame
+b351 tbdr RRF_U0FF "convert long hfp to long bfp" esame
+b374 lzer RRE_R0 "load short zero" esame
+b375 lzdr RRE_R0 "load long zero" esame
+b376 lzxr RRE_R0 "load extended zero" esame
[-- Attachment #3: binutils-test390.diff --]
[-- Type: text/x-diff, Size: 46124 bytes --]
diff -urN src/gas/testsuite/gas/s390/opcode.d src-s390/gas/testsuite/gas/s390/opcode.d
--- src/gas/testsuite/gas/s390/opcode.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,425 @@
+#name: s390 opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: 5a 65 af ff [ ]*a %r6,4095\(%r5,%r10\)
+ 4: 6a 65 af ff [ ]*ad %f6,4095\(%r5,%r10\)
+ 8: ed 65 af ff 00 1a [ ]*adb %f6,4095\(%r5,%r10\)
+ e: b3 1a 00 69 [ ]*adbr %f6,%f9
+ 12: 2a 69 [ ]*adr %f6,%f9
+ 14: 7a 65 af ff [ ]*ae %f6,4095\(%r5,%r10\)
+ 18: ed 65 af ff 00 0a [ ]*aeb %f6,4095\(%r5,%r10\)
+ 1e: b3 0a 00 69 [ ]*aebr %f6,%f9
+ 22: 3a 69 [ ]*aer %f6,%f9
+ 24: 4a 65 af ff [ ]*ah %r6,4095\(%r5,%r10\)
+ 28: a7 6a 80 01 [ ]*ahi %r6,-32767
+ 2c: 5e 65 af ff [ ]*al %r6,4095\(%r5,%r10\)
+ 30: 1e 69 [ ]*alr %r6,%r9
+ 32: fa 58 5f ff af ff [ ]*ap 4095\(6,%r5\),4095\(9,%r10\)
+ 38: 1a 69 [ ]*ar %r6,%r9
+ 3a: 7e 65 af ff [ ]*au %f6,4095\(%r5,%r10\)
+ 3e: 3e 69 [ ]*aur %f6,%f9
+ 40: 6e 65 af ff [ ]*aw %f6,4095\(%r5,%r10\)
+ 44: 2e 69 [ ]*awr %f6,%f9
+ 46: b3 4a 00 69 [ ]*axbr %f6,%f9
+ 4a: 36 69 [ ]*axr %f6,%f9
+ 4c: 47 f5 af ff [ ]*b 4095\(%r5,%r10\)
+ 50: b2 40 00 69 [ ]*bakr %r6,%r9
+ 54: 45 65 af ff [ ]*bal %r6,4095\(%r5,%r10\)
+ 58: 05 69 [ ]*balr %r6,%r9
+ 5a: 4d 65 af ff [ ]*bas %r6,4095\(%r5,%r10\)
+ 5e: 0d 69 [ ]*basr %r6,%r9
+ 60: 0c 69 [ ]*bassm %r6,%r9
+ 62: 47 65 af ff [ ]*blh 4095\(%r5,%r10\)
+ 66: 07 69 [ ]*blhr %r9
+ 68: 46 65 af ff [ ]*bct %r6,4095\(%r5,%r10\)
+ 6c: 06 69 [ ]*bctr %r6,%r9
+ 6e: 47 85 af ff [ ]*be 4095\(%r5,%r10\)
+ 72: 07 89 [ ]*ber %r9
+ 74: 47 25 af ff [ ]*bh 4095\(%r5,%r10\)
+ 78: 47 a5 af ff [ ]*bhe 4095\(%r5,%r10\)
+ 7c: 07 a9 [ ]*bher %r9
+ 7e: 07 29 [ ]*bhr %r9
+ 80: 47 45 af ff [ ]*bl 4095\(%r5,%r10\)
+ 84: 47 c5 af ff [ ]*ble 4095\(%r5,%r10\)
+ 88: 07 c9 [ ]*bler %r9
+ 8a: 47 65 af ff [ ]*blh 4095\(%r5,%r10\)
+ 8e: 07 69 [ ]*blhr %r9
+ 90: 07 49 [ ]*blr %r9
+ 92: 47 45 af ff [ ]*bl 4095\(%r5,%r10\)
+ 96: 07 49 [ ]*blr %r9
+ 98: 47 75 af ff [ ]*bne 4095\(%r5,%r10\)
+ 9c: 07 79 [ ]*bner %r9
+ 9e: 47 d5 af ff [ ]*bnh 4095\(%r5,%r10\)
+ a2: 47 55 af ff [ ]*bnhe 4095\(%r5,%r10\)
+ a6: 07 59 [ ]*bnher %r9
+ a8: 07 d9 [ ]*bnhr %r9
+ aa: 47 b5 af ff [ ]*bnl 4095\(%r5,%r10\)
+ ae: 47 35 af ff [ ]*bnle 4095\(%r5,%r10\)
+ b2: 07 39 [ ]*bnler %r9
+ b4: 47 95 af ff [ ]*bnlh 4095\(%r5,%r10\)
+ b8: 07 99 [ ]*bnlhr %r9
+ ba: 07 b9 [ ]*bnlr %r9
+ bc: 47 b5 af ff [ ]*bnl 4095\(%r5,%r10\)
+ c0: 07 b9 [ ]*bnlr %r9
+ c2: 47 e5 af ff [ ]*bno 4095\(%r5,%r10\)
+ c6: 07 e9 [ ]*bnor %r9
+ c8: 47 d5 af ff [ ]*bnh 4095\(%r5,%r10\)
+ cc: 07 d9 [ ]*bnhr %r9
+ ce: 47 75 af ff [ ]*bne 4095\(%r5,%r10\)
+ d2: 07 79 [ ]*bner %r9
+ d4: 47 15 af ff [ ]*bo 4095\(%r5,%r10\)
+ d8: 07 19 [ ]*bor %r9
+ da: 47 25 af ff [ ]*bh 4095\(%r5,%r10\)
+ de: 07 29 [ ]*bhr %r9
+ e0: 07 f9 [ ]*br %r9
+ e2: a7 95 00 00 [ ]*bras %r9,e2 <foo\+0xe2>
+ e6: a7 64 00 00 [ ]*jlh e6 <foo\+0xe6>
+ ea: a7 66 00 00 [ ]*brct %r6,ea <foo\+0xea>
+ ee: 84 69 00 00 [ ]*brxh %r6,%r9,ee <foo\+0xee>
+ f2: 85 69 00 00 [ ]*brxle %r6,%r9,f2 <foo\+0xf2>
+ f6: b2 5a 00 69 [ ]*bsa %r6,%r9
+ fa: b2 58 00 69 [ ]*bsg %r6,%r9
+ fe: 0b 69 [ ]*bsm %r6,%r9
+ 100: 86 69 5f ff [ ]*bxh %r6,%r9,4095\(%r5\)
+ 104: 87 69 5f ff [ ]*bxle %r6,%r9,4095\(%r5\)
+ 108: 47 85 af ff [ ]*be 4095\(%r5,%r10\)
+ 10c: 07 89 [ ]*ber %r9
+ 10e: 59 65 af ff [ ]*c %r6,4095\(%r5,%r10\)
+ 112: 69 65 af ff [ ]*cd %f6,4095\(%r5,%r10\)
+ 116: ed 65 af ff 00 19 [ ]*cdb %f6,4095\(%r5,%r10\)
+ 11c: b3 19 00 69 [ ]*cdbr %f6,%f9
+ 120: b3 95 00 69 [ ]*cdfbr %r6,%f9
+ 124: 29 69 [ ]*cdr %f6,%f9
+ 126: bb 69 5f ff [ ]*cds %r6,%r9,4095\(%r5\)
+ 12a: 79 65 af ff [ ]*ce %f6,4095\(%r5,%r10\)
+ 12e: ed 65 af ff 00 09 [ ]*ceb %f6,4095\(%r5,%r10\)
+ 134: b3 09 00 69 [ ]*cebr %f6,%f9
+ 138: b3 94 00 69 [ ]*cefbr %r6,%f9
+ 13c: 39 69 [ ]*cer %f6,%f9
+ 13e: b2 1a 5f ff [ ]*cfc 4095\(%r5\)
+ 142: b3 99 50 69 [ ]*cfdbr %f6,5,%r9
+ 146: b3 98 50 69 [ ]*cfebr %f6,5,%r9
+ 14a: b3 9a 50 69 [ ]*cfxbr %f6,5,%r9
+ 14e: 49 65 af ff [ ]*ch %r6,4095\(%r5,%r10\)
+ 152: a7 6e 80 01 [ ]*chi %r6,-32767
+ 156: b2 41 00 69 [ ]*cksm %r6,%r9
+ 15a: 55 65 af ff [ ]*cl %r6,4095\(%r5,%r10\)
+ 15e: d5 ff 5f ff af ff [ ]*clc 4095\(256,%r5\),4095\(%r10\)
+ 164: 0f 69 [ ]*clcl %r6,%r9
+ 166: a9 69 00 0a [ ]*clcle %r6,%r9,10
+ 16a: 95 ff 5f ff [ ]*cli 4095\(%r5\),255
+ 16e: bd 6a 5f ff [ ]*clm %r6,10,4095\(%r5\)
+ 172: 15 69 [ ]*clr %r6,%r9
+ 174: b2 5d 00 69 [ ]*clst %r6,%r9
+ 178: b2 63 00 69 [ ]*cmpsc %r6,%r9
+ 17c: f9 58 5f ff af ff [ ]*cp 4095\(6,%r5\),4095\(9,%r10\)
+ 182: b2 4d 00 69 [ ]*cpya %a6,%a9
+ 186: 19 69 [ ]*cr %r6,%r9
+ 188: ba 69 5f ff [ ]*cs %r6,%r9,4095\(%r5\)
+ 18c: b2 30 00 00 [ ]*csch
+ 190: b2 50 00 69 [ ]*csp %r6,%r9
+ 194: b2 57 00 69 [ ]*cuse %r6,%r9
+ 198: b2 a7 00 69 [ ]*cutfu %r6,%r9
+ 19c: b2 a6 00 69 [ ]*cuutf %r6,%r9
+ 1a0: 4f 65 af ff [ ]*cvb %r6,4095\(%r5,%r10\)
+ 1a4: 4e 65 af ff [ ]*cvd %r6,4095\(%r5,%r10\)
+ 1a8: b3 49 00 69 [ ]*cxbr %f6,%f9
+ 1ac: b3 96 00 69 [ ]*cxfbr %r6,%f9
+ 1b0: 5d 65 af ff [ ]*d %r6,4095\(%r5,%r10\)
+ 1b4: 6d 65 af ff [ ]*dd %f6,4095\(%r5,%r10\)
+ 1b8: ed 65 af ff 00 1d [ ]*ddb %f6,4095\(%r5,%r10\)
+ 1be: b3 1d 00 69 [ ]*ddbr %f6,%f9
+ 1c2: 2d 69 [ ]*ddr %f6,%f9
+ 1c4: 7d 65 af ff [ ]*de %f6,4095\(%r5,%r10\)
+ 1c8: ed 65 af ff 00 0d [ ]*deb %f6,4095\(%r5,%r10\)
+ 1ce: b3 0d 00 69 [ ]*debr %f6,%f9
+ 1d2: 3d 69 [ ]*der %f6,%f9
+ 1d4: 83 69 5f ff [ ]*diag %r6,%r9,4095\(%r5\)
+ 1d8: b3 5b 9a 65 [ ]*didbr %f6,%f9,%f5,10
+ 1dc: b3 53 9a 65 [ ]*diebr %f6,%f9,%f5,10
+ 1e0: fd 58 5f ff af ff [ ]*dp 4095\(6,%r5\),4095\(9,%r10\)
+ 1e6: 1d 69 [ ]*dr %r6,%r9
+ 1e8: b3 4d 00 69 [ ]*dxbr %f6,%f9
+ 1ec: b2 2d 00 60 [ ]*dxr %f6
+ 1f0: b2 4f 00 69 [ ]*ear %r6,%a9
+ 1f4: de ff 5f ff af ff [ ]*ed 4095\(256,%r5\),4095\(%r10\)
+ 1fa: df ff 5f ff af ff [ ]*edmk 4095\(256,%r5\),4095\(%r10\)
+ 200: b3 8c 00 69 [ ]*efpc %r6,%r9
+ 204: b2 26 00 60 [ ]*epar %r6
+ 208: b2 49 00 69 [ ]*ereg %r6,%r9
+ 20c: b2 27 00 60 [ ]*esar %r6
+ 210: b2 4a 00 69 [ ]*esta %r6,%r9
+ 214: 44 60 5f ff [ ]*ex %r6,4095\(%r5\)
+ 218: b3 5f 50 69 [ ]*fidbr %f6,5,%f9
+ 21c: b3 57 50 69 [ ]*fiebr %f6,5,%f9
+ 220: b3 47 50 69 [ ]*fixbr %f6,5,%f9
+ 224: 24 69 [ ]*hdr %f6,%f9
+ 226: 34 69 [ ]*her %f6,%f9
+ 228: b2 31 00 00 [ ]*hsch
+ 22c: b2 24 00 60 [ ]*iac %r6
+ 230: 43 65 af ff [ ]*ic %r6,4095\(%r5,%r10\)
+ 234: bf 6a 5f ff [ ]*icm %r6,10,4095\(%r5\)
+ 238: b2 0b 00 00 [ ]*ipk
+ 23c: b2 22 00 60 [ ]*ipm %r6
+ 240: b2 21 00 69 [ ]*ipte %r6,%r9
+ 244: b2 29 00 69 [ ]*iske %r6,%r9
+ 248: b2 23 00 69 [ ]*ivsk %r6,%r9
+ 24c: a7 f4 00 00 [ ]*j 24c <foo\+0x24c>
+ 250: a7 84 00 00 [ ]*je 250 <foo\+0x250>
+ 254: a7 24 00 00 [ ]*jh 254 <foo\+0x254>
+ 258: a7 a4 00 00 [ ]*jhe 258 <foo\+0x258>
+ 25c: a7 44 00 00 [ ]*jl 25c <foo\+0x25c>
+ 260: a7 c4 00 00 [ ]*jle 260 <foo\+0x260>
+ 264: a7 64 00 00 [ ]*jlh 264 <foo\+0x264>
+ 268: a7 44 00 00 [ ]*jl 268 <foo\+0x268>
+ 26c: a7 74 00 00 [ ]*jne 26c <foo\+0x26c>
+ 270: a7 54 00 00 [ ]*jnhe 270 <foo\+0x270>
+ 274: a7 b4 00 00 [ ]*jnl 274 <foo\+0x274>
+ 278: a7 34 00 00 [ ]*jnle 278 <foo\+0x278>
+ 27c: a7 94 00 00 [ ]*jnlh 27c <foo\+0x27c>
+ 280: a7 b4 00 00 [ ]*jnl 280 <foo\+0x280>
+ 284: a7 e4 00 00 [ ]*jno 284 <foo\+0x284>
+ 288: a7 d4 00 00 [ ]*jnh 288 <foo\+0x288>
+ 28c: a7 74 00 00 [ ]*jne 28c <foo\+0x28c>
+ 290: a7 14 00 00 [ ]*jo 290 <foo\+0x290>
+ 294: a7 24 00 00 [ ]*jh 294 <foo\+0x294>
+ 298: a7 84 00 00 [ ]*je 298 <foo\+0x298>
+ 29c: ed 65 af ff 00 18 [ ]*kdb %f6,4095\(%r5,%r10\)
+ 2a2: b3 18 00 69 [ ]*kdbr %f6,%f9
+ 2a6: ed 65 af ff 00 08 [ ]*keb %f6,4095\(%r5,%r10\)
+ 2ac: b3 08 00 69 [ ]*kebr %f6,%f9
+ 2b0: b3 48 00 69 [ ]*kxbr %f6,%f9
+ 2b4: 58 65 af ff [ ]*l %r6,4095\(%r5,%r10\)
+ 2b8: 41 65 af ff [ ]*la %r6,4095\(%r5,%r10\)
+ 2bc: 51 65 af ff [ ]*lae %r6,4095\(%r5,%r10\)
+ 2c0: 9a 69 5f ff [ ]*lam %a6,%a9,4095\(%r5\)
+ 2c4: e5 00 5f ff af ff [ ]*lasp 4095\(%r5\),4095\(%r10\)
+ 2ca: b3 13 00 69 [ ]*lcdbr %f6,%f9
+ 2ce: 23 69 [ ]*lcdr %f6,%f9
+ 2d0: b3 03 00 69 [ ]*lcebr %f6,%f9
+ 2d4: 33 69 [ ]*lcer %f6,%f9
+ 2d6: 13 69 [ ]*lcr %r6,%r9
+ 2d8: b7 69 5f ff [ ]*lctl %c6,%c9,4095\(%r5\)
+ 2dc: b3 43 00 69 [ ]*lcxbr %f6,%f9
+ 2e0: 68 60 5f ff [ ]*ld %f6,4095\(%r5\)
+ 2e4: ed 60 5f ff 00 04 [ ]*ldeb %f6,4095\(%r5\)
+ 2ea: b3 04 00 69 [ ]*ldebr %f6,%f9
+ 2ee: 28 69 [ ]*ldr %f6,%f9
+ 2f0: b3 45 00 69 [ ]*ldxbr %f6,%f9
+ 2f4: 78 60 5f ff [ ]*le %f6,4095\(%r5\)
+ 2f8: b3 44 00 69 [ ]*ledbr %f6,%f9
+ 2fc: 38 69 [ ]*ler %f6,%f9
+ 2fe: b3 46 00 69 [ ]*lexbr %f6,%f9
+ 302: b2 9d 5f ff [ ]*lfpc 4095\(%r5\)
+ 306: 48 60 5f ff [ ]*lh %r6,4095\(%r5\)
+ 30a: a7 68 80 01 [ ]*lhi %r6,-32767
+ 30e: 98 69 5f ff [ ]*lm %r6,%r9,4095\(%r5\)
+ 312: b3 11 00 69 [ ]*lndbr %f6,%f9
+ 316: 21 69 [ ]*lndr %f6,%f9
+ 318: b3 01 00 69 [ ]*lnebr %f6,%f9
+ 31c: 31 69 [ ]*lner %f6,%f9
+ 31e: 11 69 [ ]*lnr %r6,%r9
+ 320: b3 41 00 69 [ ]*lnxbr %f6,%f9
+ 324: b3 10 00 69 [ ]*lpdbr %f6,%f9
+ 328: 20 69 [ ]*lpdr %f6,%f9
+ 32a: b3 00 00 69 [ ]*lpebr %f6,%f9
+ 32e: 30 69 [ ]*lper %f6,%f9
+ 330: 10 69 [ ]*lpr %r6,%r9
+ 332: 82 00 5f ff [ ]*lpsw 4095\(%r5\)
+ 336: b3 40 00 69 [ ]*lpxbr %f6,%f9
+ 33a: 18 69 [ ]*lr %r6,%r9
+ 33c: b1 65 af ff [ ]*lra %r6,4095\(%r5,%r10\)
+ 340: 25 69 [ ]*lrdr %f6,%f9
+ 342: 35 69 [ ]*lrer %f6,%f9
+ 344: b3 12 00 69 [ ]*ltdbr %f6,%f9
+ 348: 22 69 [ ]*ltdr %f6,%f9
+ 34a: b3 02 00 69 [ ]*ltebr %f6,%f9
+ 34e: 32 69 [ ]*lter %f6,%f9
+ 350: 12 69 [ ]*ltr %r6,%r9
+ 352: b3 42 00 69 [ ]*ltxbr %f6,%f9
+ 356: b2 4b 00 69 [ ]*lura %r6,%r9
+ 35a: ed 65 af ff 00 05 [ ]*lxdb %f6,4095\(%r5,%r10\)
+ 360: b3 05 00 69 [ ]*lxdbr %f6,%f9
+ 364: ed 65 af ff 00 06 [ ]*lxeb %f6,4095\(%r5,%r10\)
+ 36a: b3 06 00 69 [ ]*lxebr %f6,%f9
+ 36e: 5c 65 af ff [ ]*m %r6,4095\(%r5,%r10\)
+ 372: ed 95 af ff 60 1e [ ]*madb %f6,%f9,4095\(%r5,%r10\)
+ 378: b3 1e 60 95 [ ]*madbr %f6,%f9,%f5
+ 37c: ed 95 af ff 60 0e [ ]*maeb %f6,%f9,4095\(%r5,%r10\)
+ 382: b3 0e 60 95 [ ]*maebr %f6,%f9,%f5
+ 386: af 06 5f ff [ ]*mc 4095\(%r5\),6
+ 38a: 6c 65 af ff [ ]*md %f6,4095\(%r5,%r10\)
+ 38e: ed 65 af ff 00 1c [ ]*mdb %f6,4095\(%r5,%r10\)
+ 394: b3 1c 00 69 [ ]*mdbr %f6,%f9
+ 398: ed 65 af ff 00 0c [ ]*mdeb %f6,4095\(%r5,%r10\)
+ 39e: b3 0c 00 69 [ ]*mdebr %f6,%f9
+ 3a2: 2c 69 [ ]*mdr %f6,%f9
+ 3a4: 7c 65 af ff [ ]*me %f6,4095\(%r5,%r10\)
+ 3a8: ed 65 af ff 00 17 [ ]*meeb %f6,4095\(%r5,%r10\)
+ 3ae: b3 17 00 69 [ ]*meebr %f6,%f9
+ 3b2: 3c 69 [ ]*mer %f6,%f9
+ 3b4: 4c 65 af ff [ ]*mh %r6,4095\(%r5,%r10\)
+ 3b8: a7 6c 80 01 [ ]*mhi %r6,-32767
+ 3bc: fc ff 5f ff af ff [ ]*mp 4095\(16,%r5\),4095\(16,%r10\)
+ 3c2: 1c 69 [ ]*mr %r6,%r9
+ 3c4: 71 65 af ff [ ]*ms %r6,4095\(%r5,%r10\)
+ 3c8: b2 32 5f ff [ ]*msch 4095\(%r5\)
+ 3cc: ed 95 af ff 60 1f [ ]*msdb %f6,%f9,4095\(%r5,%r10\)
+ 3d2: b3 1f 60 95 [ ]*msdbr %f6,%f9,%f5
+ 3d6: ed 95 af ff 60 0f [ ]*mseb %f6,%f9,4095\(%r5,%r10\)
+ 3dc: b3 0f 60 95 [ ]*msebr %f6,%f9,%f5
+ 3e0: b2 52 00 69 [ ]*msr %r6,%r9
+ 3e4: b2 47 00 60 [ ]*msta %r6
+ 3e8: d2 ff 5f ff af ff [ ]*mvc 4095\(256,%r5\),4095\(%r10\)
+ 3ee: e5 0f 5f ff af ff [ ]*mvcdk 4095\(%r5\),4095\(%r10\)
+ 3f4: e8 ff 5f ff af ff [ ]*mvcin 4095\(256,%r5\),4095\(%r10\)
+ 3fa: d9 69 5f ff af ff [ ]*mvck 4095\(%r6,%r5\),4095\(%r10\),%r9
+ 400: 0e 69 [ ]*mvcl %r6,%r9
+ 402: a8 69 00 0a [ ]*mvcle %r6,%r9,10
+ 406: da 69 5f ff af ff [ ]*mvcp 4095\(%r6,%r5\),4095\(%r10\),%r9
+ 40c: db 69 5f ff af ff [ ]*mvcs 4095\(%r6,%r5\),4095\(%r10\),%r9
+ 412: e5 0e 5f ff af ff [ ]*mvcsk 4095\(%r5\),4095\(%r10\)
+ 418: 92 ff 5f ff [ ]*mvi 4095\(%r5\),255
+ 41c: d1 ff 5f ff af ff [ ]*mvn 4095\(256,%r5\),4095\(%r10\)
+ 422: f1 ff 5f ff af ff [ ]*mvo 4095\(16,%r5\),4095\(16,%r10\)
+ 428: b2 54 00 69 [ ]*mvpg %r6,%r9
+ 42c: b2 55 00 69 [ ]*mvst %r6,%r9
+ 430: d3 ff 5f ff af ff [ ]*mvz 4095\(256,%r5\),4095\(%r10\)
+ 436: b3 4c 00 69 [ ]*mxbr %f6,%f9
+ 43a: 67 65 af ff [ ]*mxd %f6,4095\(%r5,%r10\)
+ 43e: ed 65 af ff 00 07 [ ]*mxdb %f6,4095\(%r5,%r10\)
+ 444: b3 07 00 69 [ ]*mxdbr %f6,%f9
+ 448: 27 69 [ ]*mxdr %f6,%f9
+ 44a: 26 69 [ ]*mxr %f6,%f9
+ 44c: 54 65 af ff [ ]*n %r6,4095\(%r5,%r10\)
+ 450: d4 ff 5f ff af ff [ ]*nc 4095\(256,%r5\),4095\(%r10\)
+ 456: 94 ff 5f ff [ ]*ni 4095\(%r5\),255
+ 45a: 47 05 af ff [ ]*bc 0,4095\(%r5,%r10\)
+ 45e: 07 06 [ ]*bcr 0,%r6
+ 460: 14 69 [ ]*nr %r6,%r9
+ 462: 56 65 af ff [ ]*o %r6,4095\(%r5,%r10\)
+ 466: d6 ff 5f ff af ff [ ]*oc 4095\(256,%r5\),4095\(%r10\)
+ 46c: 96 ff 5f ff [ ]*oi 4095\(%r5\),255
+ 470: 16 69 [ ]*or %r6,%r9
+ 472: f2 ff 5f ff af ff [ ]*pack 4095\(16,%r5\),4095\(16,%r10\)
+ 478: b2 48 00 00 [ ]*palb
+ 47c: b2 18 5f ff [ ]*pc 4095\(%r5\)
+ 480: ee 69 5f ff af ff [ ]*plo %r6,4095\(%r5\),%r9,4095\(%r10\)
+ 486: 01 01 [ ]*pr
+ 488: b2 28 00 69 [ ]*pt %r6,%r9
+ 48c: b2 0d 00 00 [ ]*ptlb
+ 490: b2 3b 00 00 [ ]*rchp
+ 494: b2 77 5f ff [ ]*rp 4095\(%r5\)
+ 498: b2 2a 00 69 [ ]*rrbe %r6,%r9
+ 49c: b2 38 00 00 [ ]*rsch
+ 4a0: 5b 65 af ff [ ]*s %r6,4095\(%r5,%r10\)
+ 4a4: b2 19 5f ff [ ]*sac 4095\(%r5\)
+ 4a8: b2 79 5f ff [ ]*sacf 4095\(%r5\)
+ 4ac: b2 37 00 00 [ ]*sal
+ 4b0: b2 4e 00 69 [ ]*sar %a6,%r9
+ 4b4: b2 3c 00 00 [ ]*schm
+ 4b8: b2 04 5f ff [ ]*sck 4095\(%r5\)
+ 4bc: b2 06 5f ff [ ]*sckc 4095\(%r5\)
+ 4c0: 01 07 [ ]*sckpf
+ 4c2: 6b 65 af ff [ ]*sd %f6,4095\(%r5,%r10\)
+ 4c6: ed 65 af ff 00 1b [ ]*sdb %f6,4095\(%r5,%r10\)
+ 4cc: b3 1b 00 69 [ ]*sdbr %f6,%f9
+ 4d0: 2b 69 [ ]*sdr %f6,%f9
+ 4d2: 7b 65 af ff [ ]*se %f6,4095\(%r5,%r10\)
+ 4d6: ed 65 af ff 00 0b [ ]*seb %f6,4095\(%r5,%r10\)
+ 4dc: b3 0b 00 69 [ ]*sebr %f6,%f9
+ 4e0: 3b 69 [ ]*ser %f6,%f9
+ 4e2: b3 84 00 69 [ ]*sfpc %r6,%r9
+ 4e6: 4b 65 af ff [ ]*sh %r6,4095\(%r5,%r10\)
+ 4ea: b2 14 5f ff [ ]*sie 4095\(%r5\)
+ 4ee: b2 74 5f ff [ ]*siga 4095\(%r5\)
+ 4f2: ae 69 5f ff [ ]*sigp %r6,%r9,4095\(%r5\)
+ 4f6: 5f 65 af ff [ ]*sl %r6,4095\(%r5,%r10\)
+ 4fa: 8b 60 5f ff [ ]*sla %r6,4095\(%r5\)
+ 4fe: 8f 60 5f ff [ ]*slda %r6,4095\(%r5\)
+ 502: 8d 60 5f ff [ ]*sldl %r6,4095\(%r5\)
+ 506: 89 60 5f ff [ ]*sll %r6,4095\(%r5\)
+ 50a: 1f 69 [ ]*slr %r6,%r9
+ 50c: fb ff 5f ff af ff [ ]*sp 4095\(16,%r5\),4095\(16,%r10\)
+ 512: b2 0a 5f ff [ ]*spka 4095\(%r5\)
+ 516: 04 60 [ ]*spm %r6
+ 518: b2 08 5f ff [ ]*spt 4095\(%r5\)
+ 51c: b2 10 5f ff [ ]*spx 4095\(%r5\)
+ 520: ed 65 af ff 00 15 [ ]*sqdb %f6,4095\(%r5,%r10\)
+ 526: b3 15 00 69 [ ]*sqdbr %f6,%f9
+ 52a: b2 44 00 60 [ ]*sqdr %f6
+ 52e: ed 65 af ff 00 14 [ ]*sqeb %f6,4095\(%r5,%r10\)
+ 534: b3 14 00 69 [ ]*sqebr %f6,%f9
+ 538: b2 45 00 60 [ ]*sqer %f6
+ 53c: b3 16 00 69 [ ]*sqxbr %f6,%f9
+ 540: 1b 69 [ ]*sr %r6,%r9
+ 542: 8a 60 5f ff [ ]*sra %r6,4095\(%r5\)
+ 546: 8e 60 5f ff [ ]*srda %r6,4095\(%r5\)
+ 54a: 8c 60 5f ff [ ]*srdl %r6,4095\(%r5\)
+ 54e: 88 60 5f ff [ ]*srl %r6,4095\(%r5\)
+ 552: b2 99 5f ff [ ]*srnm 4095\(%r5\)
+ 556: f0 fa 5f ff af ff [ ]*srp 4095\(16,%r5\),4095\(%r10\),10
+ 55c: b2 5e 00 69 [ ]*srst %r6,%r9
+ 560: b2 25 00 60 [ ]*ssar %r6
+ 564: b2 33 5f ff [ ]*ssch 4095\(%r5\)
+ 568: b2 2b 00 69 [ ]*sske %r6,%r9
+ 56c: 80 00 5f ff [ ]*ssm 4095\(%r5\)
+ 570: 50 65 af ff [ ]*st %r6,4095\(%r5,%r10\)
+ 574: 9b 69 5f ff [ ]*stam %a6,%a9,4095\(%r5\)
+ 578: b2 12 5f ff [ ]*stap 4095\(%r5\)
+ 57c: 42 65 af ff [ ]*stc %r6,4095\(%r5,%r10\)
+ 580: b2 05 5f ff [ ]*stck 4095\(%r5\)
+ 584: b2 07 5f ff [ ]*stckc 4095\(%r5\)
+ 588: be 6f 5f ff [ ]*stcm %r6,15,4095\(%r5\)
+ 58c: b2 3a 5f ff [ ]*stcps 4095\(%r5\)
+ 590: b2 39 5f ff [ ]*stcrw 4095\(%r5\)
+ 594: b6 69 5f ff [ ]*stctl %c6,%c9,4095\(%r5\)
+ 598: 60 65 af ff [ ]*std %f6,4095\(%r5,%r10\)
+ 59c: 70 65 af ff [ ]*ste %f6,4095\(%r5,%r10\)
+ 5a0: b2 9c 5f ff [ ]*stfpc 4095\(%r5\)
+ 5a4: 40 65 af ff [ ]*sth %r6,4095\(%r5,%r10\)
+ 5a8: b2 02 5f ff [ ]*stidp 4095\(%r5\)
+ 5ac: 90 69 5f ff [ ]*stm %r6,%r9,4095\(%r5\)
+ 5b0: ac ff 5f ff [ ]*stnsm 4095\(%r5\),255
+ 5b4: ad ff 5f ff [ ]*stosm 4095\(%r5\),255
+ 5b8: b2 09 5f ff [ ]*stpt 4095\(%r5\)
+ 5bc: b2 11 5f ff [ ]*stpx 4095\(%r5\)
+ 5c0: b2 34 5f ff [ ]*stsch 4095\(%r5\)
+ 5c4: b2 7d 5f ff [ ]*stsi 4095\(%r5\)
+ 5c8: b2 46 00 69 [ ]*stura %r6,%r9
+ 5cc: 7f 65 af ff [ ]*su %f6,4095\(%r5,%r10\)
+ 5d0: 3f 69 [ ]*sur %f6,%f9
+ 5d2: 0a ff [ ]*svc 255
+ 5d4: 6f 65 af ff [ ]*sw %f6,4095\(%r5,%r10\)
+ 5d8: 2f 69 [ ]*swr %f6,%f9
+ 5da: b3 4b 00 69 [ ]*sxbr %f6,%f9
+ 5de: 37 69 [ ]*sxr %f6,%f9
+ 5e0: b2 4c 00 69 [ ]*tar %a6,%r9
+ 5e4: b2 2c 00 06 [ ]*tb %r6
+ 5e8: ed 65 af ff 00 11 [ ]*tcdb %f6,4095\(%r5,%r10\)
+ 5ee: ed 65 af ff 00 10 [ ]*tceb %f6,4095\(%r5,%r10\)
+ 5f4: ed 65 af ff 00 12 [ ]*tcxb %f6,4095\(%r5,%r10\)
+ 5fa: 91 ff 5f ff [ ]*tm 4095\(%r5\),255
+ 5fe: a7 60 ff ff [ ]*tmh %r6,65535
+ 602: a7 61 ff ff [ ]*tml %r6,65535
+ 606: b2 36 5f ff [ ]*tpi 4095\(%r5\)
+ 60a: e5 01 5f ff af ff [ ]*tprot 4095\(%r5\),4095\(%r10\)
+ 610: dc ff 5f ff af ff [ ]*tr 4095\(256,%r5\),4095\(%r10\)
+ 616: 99 69 5f ff [ ]*trace %r6,%r9,4095\(%r5\)
+ 61a: 01 ff [ ]*trap2
+ 61c: b2 ff 5f ff [ ]*trap4 4095\(%r5\)
+ 620: dd ff 5f ff af ff [ ]*trt 4095\(256,%r5\),4095\(%r10\)
+ 626: 93 00 5f ff [ ]*ts 4095\(%r5\)
+ 62a: b2 35 5f ff [ ]*tsch 4095\(%r5\)
+ 62e: f3 ff 5f ff af ff [ ]*unpk 4095\(16,%r5\),4095\(16,%r10\)
+ 634: 01 02 [ ]*upt
+ 636: 57 65 af ff [ ]*x %r6,4095\(%r5,%r10\)
+ 63a: d7 ff 5f ff af ff [ ]*xc 4095\(256,%r5\),4095\(%r10\)
+ 640: 97 ff 5f ff [ ]*xi 4095\(%r5\),255
+ 644: 17 69 [ ]*xr %r6,%r9
+ 646: f8 ff 5f ff af ff [ ]*zap 4095\(16,%r5\),4095\(16,%r10\)
diff -urN src/gas/testsuite/gas/s390/opcode.s src-s390/gas/testsuite/gas/s390/opcode.s
--- src/gas/testsuite/gas/s390/opcode.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,419 @@
+.text
+foo:
+ a %r6,4095(%r5,%r10)
+ ad %f6,4095(%r5,%r10)
+ adb %f6,4095(%r5,%r10)
+ adbr %f6,%f9
+ adr %f6,%f9
+ ae %f6,4095(%r5,%r10)
+ aeb %f6,4095(%r5,%r10)
+ aebr %f6,%f9
+ aer %f6,%f9
+ ah %r6,4095(%r5,%r10)
+ ahi %r6,-32767
+ al %r6,4095(%r5,%r10)
+ alr %r6,%r9
+ ap 4095(6,%r5),4095(9,%r10)
+ ar %r6,%r9
+ au %f6,4095(%r5,%r10)
+ aur %f6,%f9
+ aw %f6,4095(%r5,%r10)
+ awr %f6,%f9
+ axbr %f6,%f9
+ axr %f6,%f9
+ b 4095(%r5,%r10)
+ bakr %r6,%r9
+ bal %r6,4095(%r5,%r10)
+ balr %r6,%r9
+ bas %r6,4095(%r5,%r10)
+ basr %r6,%r9
+ bassm %r6,%r9
+ bc 6,4095(%r5,%r10)
+ bcr 6,%r9
+ bct %r6,4095(%r5,%r10)
+ bctr %r6,%r9
+ be 4095(%r5,%r10)
+ ber %r9
+ bh 4095(%r5,%r10)
+ bhe 4095(%r5,%r10)
+ bher %r9
+ bhr %r9
+ bl 4095(%r5,%r10)
+ ble 4095(%r5,%r10)
+ bler %r9
+ blh 4095(%r5,%r10)
+ blhr %r9
+ blr %r9
+ bm 4095(%r5,%r10)
+ bmr %r9
+ bne 4095(%r5,%r10)
+ bner %r9
+ bnh 4095(%r5,%r10)
+ bnhe 4095(%r5,%r10)
+ bnher %r9
+ bnhr %r9
+ bnl 4095(%r5,%r10)
+ bnle 4095(%r5,%r10)
+ bnler %r9
+ bnlh 4095(%r5,%r10)
+ bnlhr %r9
+ bnlr %r9
+ bnm 4095(%r5,%r10)
+ bnmr %r9
+ bno 4095(%r5,%r10)
+ bnor %r9
+ bnp 4095(%r5,%r10)
+ bnpr %r9
+ bnz 4095(%r5,%r10)
+ bnzr %r9
+ bo 4095(%r5,%r10)
+ bor %r9
+ bp 4095(%r5,%r10)
+ bpr %r9
+ br %r9
+ bras %r9,.
+ brc 6,.
+ brct 6,.
+ brxh %r6,%r9,.
+ brxle %r6,%r9,.
+ bsa %r6,%r9
+ bsg %r6,%r9
+ bsm %r6,%r9
+ bxh %r6,%r9,4095(%r5)
+ bxle %r6,%r9,4095(%r5)
+ bz 4095(%r5,%r10)
+ bzr %r9
+ c %r6,4095(%r5,%r10)
+ cd %f6,4095(%r5,%r10)
+ cdb %f6,4095(%r5,%r10)
+ cdbr %f6,%f9
+ cdfbr %r6,%f9
+ cdr %f6,%f9
+ cds %r6,%r9,4095(%r5)
+ ce %f6,4095(%r5,%r10)
+ ceb %f6,4095(%r5,%r10)
+ cebr %f6,%f9
+ cefbr %r6,%f9
+ cer %f6,%f9
+ cfc 4095(%r5)
+ cfdbr %f6,5,%r9
+ cfebr %f6,5,%r9
+ cfxbr %f6,5,%r9
+ ch %r6,4095(%r5,%r10)
+ chi %r6,-32767
+ cksm %r6,%r9
+ cl %r6,4095(%r5,%r10)
+ clc 4095(256,%r5),4095(%r10)
+ clcl %r6,%r9
+ clcle %r6,%r9,10
+ cli 4095(%r5),255
+ clm %r6,10,4095(%r5)
+ clr %r6,%r9
+ clst %r6,%r9
+ cmpsc %r6,%r9
+ cp 4095(6,%r5),4095(9,%r10)
+ cpya %a6,%a9
+ cr %r6,%r9
+ cs %r6,%r9,4095(%r5)
+ csch
+ csp %r6,%r9
+ cuse %r6,%r9
+ cutfu %r6,%r9
+ cuutf %r6,%r9
+ cvb %r6,4095(%r5,%r10)
+ cvd %r6,4095(%r5,%r10)
+ cxbr %f6,%f9
+ cxfbr %r6,%f9
+ d %r6,4095(%r5,%r10)
+ dd %f6,4095(%r5,%r10)
+ ddb %f6,4095(%r5,%r10)
+ ddbr %f6,%f9
+ ddr %f6,%f9
+ de %f6,4095(%r5,%r10)
+ deb %f6,4095(%r5,%r10)
+ debr %f6,%f9
+ der %f6,%f9
+ diag %r6,%r9,4095(%r5)
+ didbr %f6,%r9,%r5,10
+ diebr %f6,%r9,%r5,10
+ dp 4095(6,%r5),4095(9,%r10)
+ dr %r6,%r9
+ dxbr %f6,%f9
+ dxr %f6
+ ear %r6,%a9
+ ed 4095(256,%r5),4095(%r10)
+ edmk 4095(256,%r5),4095(%r10)
+ efpc %r6,%r9
+ epar %r6
+ ereg %r6,%r9
+ esar %r6
+ esta %r6,%r9
+ ex %r6,4095(%r5)
+ fidbr %r6,5,%r9
+ fiebr %r6,5,%r9
+ fixbr %r6,5,%r9
+ hdr %f6,%f9
+ her %f6,%f9
+ hsch
+ iac %r6
+ ic %r6,4095(%r5,%r10)
+ icm %r6,10,4095(%r5)
+ ipk
+ ipm %r6
+ ipte %r6,%r9
+ iske %r6,%r9
+ ivsk %r6,%r9
+ j .
+ je .
+ jh .
+ jhe .
+ jl .
+ jle .
+ jlh .
+ jm .
+ jne .
+ jnhe .
+ jnl .
+ jnle .
+ jnlh .
+ jnm .
+ jno .
+ jnp .
+ jnz .
+ jo .
+ jp .
+ jz .
+ kdb %f6,4095(%r5,%r10)
+ kdbr %f6,%f9
+ keb %f6,4095(%r5,%r10)
+ kebr %f6,%f9
+ kxbr %f6,%f9
+ l %r6,4095(%r5,%r10)
+ la %r6,4095(%r5,%r10)
+ lae %r6,4095(%r5,%r10)
+ lam %a6,%a9,4095(%r5)
+ lasp 4095(%r5),4095(%r10)
+ lcdbr %f6,%f9
+ lcdr %f6,%f9
+ lcebr %f6,%f9
+ lcer %f6,%f9
+ lcr %r6,%r9
+ lctl %c6,%c9,4095(%r5)
+ lcxbr %f6,%f9
+ ld %f6,4095(%r5)
+ ldeb %f6,4095(%r5)
+ ldebr %f6,%f9
+ ldr %f6,%f9
+ ldxbr %f6,%f9
+ le %f6,4095(%r5)
+ ledbr %f6,%f9
+ ler %f6,%f9
+ lexbr %f6,%f9
+ lfpc 4095(%r5)
+ lh %r6,4095(%r5)
+ lhi %r6,-32767
+ lm %r6,%r9,4095(%r5)
+ lndbr %f6,%f9
+ lndr %f6,%f9
+ lnebr %f6,%f9
+ lner %f6,%f9
+ lnr %r6,%r9
+ lnxbr %f6,%f9
+ lpdbr %f6,%f9
+ lpdr %f6,%f9
+ lpebr %f6,%f9
+ lper %f6,%f9
+ lpr %r6,%r9
+ lpsw 4095(%r5)
+ lpxbr %f6,%f9
+ lr %r6,%r9
+ lra %r6,4095(%r5,%r10)
+ lrdr %f6,%f9
+ lrer %f6,%f9
+ ltdbr %f6,%f9
+ ltdr %f6,%f9
+ ltebr %f6,%f9
+ lter %f6,%f9
+ ltr %r6,%r9
+ ltxbr %f6,%f9
+ lura %r6,%r9
+ lxdb %f6,4095(%r5,%r10)
+ lxdbr %f6,%f9
+ lxeb %f6,4095(%r5,%r10)
+ lxebr %f6,%f9
+ m %r6,4095(%r5,%r10)
+ madb %f6,%f9,4095(%r5,%r10)
+ madbr %f6,%f9,%f5
+ maeb %f6,%f9,4095(%r5,%r10)
+ maebr %f6,%f9,%f5
+ mc 4095(%r5),6
+ md %f6,4095(%r5,%r10)
+ mdb %f6,4095(%f5,%f10)
+ mdbr %f6,%f9
+ mdeb %f6,4095(%f5,%f10)
+ mdebr %f6,%f9
+ mdr %f6,%f9
+ me %f6,4095(%r5,%r10)
+ meeb %f6,4095(%r5,%r10)
+ meebr %f6,%f9
+ mer %f6,%f9
+ mh %r6,4095(%r5,%r10)
+ mhi %r6,-32767
+ mp 4095(16,%r5),4095(16,%r10)
+ mr %r6,%r9
+ ms %r6,4095(%r5,%r10)
+ msch 4095(%r5)
+ msdb %f6,%f9,4095(%r5,%r10)
+ msdbr %f6,%f9,%f5
+ mseb %f6,%f9,4095(%r5,%r10)
+ msebr %f6,%f9,%f5
+ msr %r6,%r9
+ msta %r6
+ mvc 4095(256,%r5),4095(%r10)
+ mvcdk 4095(%r5),4095(%r10)
+ mvcin 4095(256,%r5),4095(%r10)
+ mvck 4095(%r6,%r5),4095(%r10),%r9
+ mvcl %r6,%r9
+ mvcle %r6,%r9,10
+ mvcp 4095(%r6,%r5),4095(%r10),%r9
+ mvcs 4095(%r6,%r5),4095(%r10),%r9
+ mvcsk 4095(%r5),4095(%r10)
+ mvi 4095(%r5),255
+ mvn 4095(256,%r5),4095(%r10)
+ mvo 4095(16,%r5),4095(16,%r10)
+ mvpg %r6,%r9
+ mvst %r6,%r9
+ mvz 4095(256,%r5),4095(%r10)
+ mxbr %f6,%f9
+ mxd %f6,4095(%r5,%r10)
+ mxdb %f6,4095(%r5,%r10)
+ mxdbr %f6,%f9
+ mxdr %r6,%r9
+ mxr %r6,%r9
+ n %r6,4095(%r5,%r10)
+ nc 4095(256,%r5),4095(%r10)
+ ni 4095(%r5),255
+ nop 4095(%r5,%r10)
+ nopr %r6
+ nr %r6,%r9
+ o %r6,4095(%r5,%r10)
+ oc 4095(256,%r5),4095(%r10)
+ oi 4095(%r5),255
+ or %r6,%r9
+ pack 4095(16,%r5),4095(16,%r10)
+ palb
+ pc 4095(%r5)
+ plo %r6,4095(%r5),%r9,4095(%r10)
+ pr
+ pt %r6,%r9
+ ptlb
+ rchp
+ rp 4095(%r5)
+ rrbe %r6,%r9
+ rsch
+ s %r6,4095(%r5,%r10)
+ sac 4095(%r5)
+ sacf 4095(%r5)
+ sal
+ sar %a6,%r9
+ schm
+ sck 4095(%r5)
+ sckc 4095(%r5)
+ sckpf
+ sd %f6,4095(%r5,%r10)
+ sdb %f6,4095(%r5,%r10)
+ sdbr %f6,%f9
+ sdr %f6,%f9
+ se %f6,4095(%r5,%r10)
+ seb %f6,4095(%r5,%r10)
+ sebr %f6,%f9
+ ser %r6,%r9
+ sfpc %r6,%r9
+ sh %r6,4095(%r5,%r10)
+ sie 4095(%r5)
+ siga 4095(%r5)
+ sigp %r6,%r9,4095(%r5)
+ sl %r6,4095(%r5,%r10)
+ sla %r6,4095(%r5)
+ slda %r6,4095(%r5)
+ sldl %r6,4095(%r5)
+ sll %r6,4095(%r5)
+ slr %r6,%r9
+ sp 4095(16,%r5),4095(16,%r10)
+ spka 4095(%r5)
+ spm %r6
+ spt 4095(%r5)
+ spx 4095(%r5)
+ sqdb %f6,4095(%r5,%r10)
+ sqdbr %f6,%f9
+ sqdr %f6
+ sqeb %f6,4095(%r5,%r10)
+ sqebr %f6,%f9
+ sqer %f6
+ sqxbr %f6,%f9
+ sr %r6,%r9
+ sra %r6,4095(%r5)
+ srda %r6,4095(%r5)
+ srdl %r6,4095(%r5)
+ srl %r6,4095(%r5)
+ srnm 4095(%r5)
+ srp 4095(16,%r5),4095(%r10),10
+ srst %r6,%r9
+ ssar %r6
+ ssch 4095(%r5)
+ sske %r6,%r9
+ ssm 4095(%r5)
+ st %r6,4095(%r5,%r10)
+ stam %a6,%a9,4095(%r5)
+ stap 4095(%r5)
+ stc %r6,4095(%r5,%r10)
+ stck 4095(%r5)
+ stckc 4095(%r5)
+ stcm %r6,15,4095(%r5)
+ stcps 4095(%r5)
+ stcrw 4095(%r5)
+ stctl %c6,%c9,4095(%r5)
+ std %f6,4095(%r5,%r10)
+ ste %f6,4095(%r5,%r10)
+ stfpc 4095(%r5)
+ sth %r6,4095(%r5,%r10)
+ stidp 4095(%r5)
+ stm %r6,%r9,4095(%r5)
+ stnsm 4095(%r5),255
+ stosm 4095(%r5),255
+ stpt 4095(%r5)
+ stpx 4095(%r5)
+ stsch 4095(%r5)
+ stsi 4095(%r5)
+ stura %r6,%r9
+ su %f6,4095(%r5,%r10)
+ sur %r6,%r9
+ svc 255
+ sw %f6,4095(%r5,%r10)
+ swr %f6,%f9
+ sxbr %f6,%f9
+ sxr %r6,%r9
+ tar %a6,%r9
+ tb %r6
+ tcdb %f6,4095(%r5,%r10)
+ tceb %f6,4095(%r5,%r10)
+ tcxb %f6,4095(%r5,%r10)
+ tm 4095(%r5),255
+ tmh %r6,65535
+ tml %r6,65535
+ tpi 4095(%r5)
+ tprot 4095(%r5),4095(%r10)
+ tr 4095(256,%r5),4095(%r10)
+ trace %r6,%r9,4095(%r5)
+ trap2
+ trap4 4095(%r5)
+ trt 4095(256,%r5),4095(%r10)
+ ts 4095(%r5)
+ tsch 4095(%r5)
+ unpk 4095(16,%r5),4095(16,%r10)
+ upt
+ x %r6,4095(%r5,%r10)
+ xc 4095(256,%r5),4095(%r10)
+ xi 4095(%r5),255
+ xr %r6,%r9
+ zap 4095(16,%r5),4095(16,%r10)
diff -urN src/gas/testsuite/gas/s390/opcode64.d src-s390/gas/testsuite/gas/s390/opcode64.d
--- src/gas/testsuite/gas/s390/opcode64.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode64.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,211 @@
+#name: s390x opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: e3 95 af ff 00 08 [ ]*ag %r9,4095\(%r5,%r10\)
+ 6: e3 95 af ff 00 18 [ ]*agf %r9,4095\(%r5,%r10\)
+ c: b9 18 00 96 [ ]*agfr %r9,%r6
+ 10: a7 9b 80 01 [ ]*aghi %r9,-32767
+ 14: b9 08 00 96 [ ]*agr %r9,%r6
+ 18: e3 95 af ff 00 98 [ ]*alc %r9,4095\(%r5,%r10\)
+ 1e: e3 95 af ff 00 88 [ ]*alcg %r9,4095\(%r5,%r10\)
+ 24: b9 88 00 96 [ ]*alcgr %r9,%r6
+ 28: b9 98 00 96 [ ]*alcr %r9,%r6
+ 2c: e3 95 af ff 00 0a [ ]*alg %r9,4095\(%r5,%r10\)
+ 32: e3 95 af ff 00 1a [ ]*algf %r9,4095\(%r5,%r10\)
+ 38: b9 1a 00 96 [ ]*algfr %r9,%r6
+ 3c: b9 0a 00 96 [ ]*algr %r9,%r6
+ 40: e3 65 af ff 00 46 [ ]*bctg %r6,4095\(%r5,%r10\)
+ 46: b9 46 00 69 [ ]*bctgr %r6,%r9
+ 4a: c0 65 00 00 00 00 [ ]*brasl %r6,4a <foo\+0x4a>
+ 50: c0 f4 00 00 00 00 [ ]*jg 50 <foo\+0x50>
+ 56: a7 67 00 00 [ ]*brctg %r6,56 <foo\+0x56>
+ 5a: ec 69 00 00 00 44 [ ]*brxhg %r6,%r9,5a <foo\+0x5a>
+ 60: ec 69 00 00 00 45 [ ]*brxlg %r6,%r9,60 <foo\+0x60>
+ 66: eb 69 5f ff 00 44 [ ]*bxhg %r6,%r9,4095\(%r5\)
+ 6c: eb 69 5f ff 00 45 [ ]*bxleg %r6,%r9,4095\(%r5\)
+ 72: b3 a5 00 69 [ ]*cdgbr %r6,%r9
+ 76: b3 c5 00 69 [ ]*cdgr %r6,%r9
+ 7a: eb 69 5f ff 00 3e [ ]*cdsg %r6,%r9,4095\(%r5\)
+ 80: b3 a4 00 69 [ ]*cegbr %r6,%r9
+ 84: b3 c4 00 69 [ ]*cegr %r6,%r9
+ 88: e3 65 af ff 00 20 [ ]*cg %r6,4095\(%r5,%r10\)
+ 8e: b3 a9 f0 69 [ ]*cgdbr %f6,15,%r9
+ 92: b3 c9 90 65 [ ]*cgdr %f6,9,%r5
+ 96: b3 a8 f0 69 [ ]*cgebr %f6,15,%r9
+ 9a: b3 c8 90 65 [ ]*cger %f6,9,%r5
+ 9e: e3 65 af ff 00 30 [ ]*cgf %r6,4095\(%r5,%r10\)
+ a4: b9 30 00 69 [ ]*cgfr %r6,%r9
+ a8: a7 6f 80 01 [ ]*cghi %r6,-32767
+ ac: b9 20 00 69 [ ]*cgr %r6,%r9
+ b0: b3 aa f0 69 [ ]*cgxbr %f6,15,%r9
+ b4: b3 ca 90 65 [ ]*cgxr %f6,9,%r5
+ b8: e3 65 af ff 00 21 [ ]*clg %r6,4095\(%r5,%r10\)
+ be: e3 65 af ff 00 31 [ ]*clgf %r6,4095\(%r5,%r10\)
+ c4: b9 31 00 69 [ ]*clgfr %r6,%r9
+ c8: b9 21 00 69 [ ]*clgr %r6,%r9
+ cc: eb 6a 5f ff 00 20 [ ]*clmh %r6,10,4095\(%r5\)
+ d2: eb 69 5f ff 00 30 [ ]*csg %r6,%r9,4095\(%r5\)
+ d8: e3 65 af ff 00 0e [ ]*cvbg %r6,4095\(%r5,%r10\)
+ de: e3 65 af ff 00 2e [ ]*cvdg %r6,4095\(%r5,%r10\)
+ e4: b3 a6 00 69 [ ]*cxgbr %r6,%r9
+ e8: b3 c6 00 69 [ ]*cxgr %r6,%r9
+ ec: e3 65 af ff 00 97 [ ]*dl %r6,4095\(%r5,%r10\)
+ f2: e3 65 af ff 00 87 [ ]*dlg %r6,4095\(%r5,%r10\)
+ f8: b9 87 00 69 [ ]*dlgr %r6,%r9
+ fc: b9 97 00 69 [ ]*dlr %r6,%r9
+ 100: e3 65 af ff 00 0d [ ]*dsg %r6,4095\(%r5,%r10\)
+ 106: e3 65 af ff 00 1d [ ]*dsgf %r6,4095\(%r5,%r10\)
+ 10c: b9 1d 00 69 [ ]*dsgfr %r6,%r9
+ 110: b9 0d 00 69 [ ]*dsgr %r6,%r9
+ 114: b9 8d 00 69 [ ]*epsw %r6,%r9
+ 118: b9 0e 00 69 [ ]*eregg %r6,%r9
+ 11c: b9 9d 00 60 [ ]*esea %r6
+ 120: eb 6a 5f ff 00 80 [ ]*icmh %r6,10,4095\(%r5\)
+ 126: a5 60 ff ff [ ]*iihh %r6,65535
+ 12a: a5 61 ff ff [ ]*iihl %r6,65535
+ 12e: a5 62 ff ff [ ]*iilh %r6,65535
+ 132: a5 63 ff ff [ ]*iill %r6,65535
+ 136: c0 f4 00 00 00 00 [ ]*jg 136 <foo\+0x136>
+ 13c: c0 84 00 00 00 00 [ ]*jge 13c <foo\+0x13c>
+ 142: c0 24 00 00 00 00 [ ]*jgh 142 <foo\+0x142>
+ 148: c0 a4 00 00 00 00 [ ]*jghe 148 <foo\+0x148>
+ 14e: c0 44 00 00 00 00 [ ]*jgl 14e <foo\+0x14e>
+ 154: c0 c4 00 00 00 00 [ ]*jgle 154 <foo\+0x154>
+ 15a: c0 64 00 00 00 00 [ ]*jglh 15a <foo\+0x15a>
+ 160: c0 44 00 00 00 00 [ ]*jgl 160 <foo\+0x160>
+ 166: c0 74 00 00 00 00 [ ]*jgne 166 <foo\+0x166>
+ 16c: c0 d4 00 00 00 00 [ ]*jgnh 16c <foo\+0x16c>
+ 172: c0 54 00 00 00 00 [ ]*jgnhe 172 <foo\+0x172>
+ 178: c0 b4 00 00 00 00 [ ]*jgnl 178 <foo\+0x178>
+ 17e: c0 34 00 00 00 00 [ ]*jgnle 17e <foo\+0x17e>
+ 184: c0 94 00 00 00 00 [ ]*jgnlh 184 <foo\+0x184>
+ 18a: c0 b4 00 00 00 00 [ ]*jgnl 18a <foo\+0x18a>
+ 190: c0 e4 00 00 00 00 [ ]*jgno 190 <foo\+0x190>
+ 196: c0 d4 00 00 00 00 [ ]*jgnh 196 <foo\+0x196>
+ 19c: c0 74 00 00 00 00 [ ]*jgne 19c <foo\+0x19c>
+ 1a2: c0 14 00 00 00 00 [ ]*jgo 1a2 <foo\+0x1a2>
+ 1a8: c0 24 00 00 00 00 [ ]*jgh 1a8 <foo\+0x1a8>
+ 1ae: c0 84 00 00 00 00 [ ]*jge 1ae <foo\+0x1ae>
+ 1b4: c0 60 00 00 00 00 [ ]*larl %r6,1b4 <foo\+0x1b4>
+ 1ba: b9 13 00 69 [ ]*lcgfr %r6,%r9
+ 1be: b9 03 00 69 [ ]*lcgr %r6,%r9
+ 1c2: eb 69 5f ff 00 2f [ ]*lctlg %r6,%r9,4095\(%r5\)
+ 1c8: e3 65 af ff 00 04 [ ]*lg %r6,4095\(%r5,%r10\)
+ 1ce: e3 65 af ff 00 14 [ ]*lgf %r6,4095\(%r5,%r10\)
+ 1d4: b9 14 00 69 [ ]*lgfr %r6,%r9
+ 1d8: e3 65 af ff 00 15 [ ]*lgh %r6,4095\(%r5,%r10\)
+ 1de: a7 69 80 01 [ ]*lghi %r6,-32767
+ 1e2: b9 04 00 69 [ ]*lgr %r6,%r9
+ 1e6: e3 65 af ff 00 90 [ ]*llgc %r6,4095\(%r5,%r10\)
+ 1ec: e3 65 af ff 00 16 [ ]*llgf %r6,4095\(%r5,%r10\)
+ 1f2: b9 16 00 69 [ ]*llgfr %r6,%r9
+ 1f6: e3 65 af ff 00 91 [ ]*llgh %r6,4095\(%r5,%r10\)
+ 1fc: e3 65 af ff 00 17 [ ]*llgt %r6,4095\(%r5,%r10\)
+ 202: b9 17 00 69 [ ]*llgtr %r6,%r9
+ 206: a5 6c ff ff [ ]*llihh %r6,65535
+ 20a: a5 6d ff ff [ ]*llihl %r6,65535
+ 20e: a5 6e ff ff [ ]*llilh %r6,65535
+ 212: a5 6f ff ff [ ]*llill %r6,65535
+ 216: ef 69 5f ff af ff [ ]*lmd %r6,%r9,4095\(%r5\),4095\(%r10\)
+ 21c: eb 69 5f ff 00 04 [ ]*lmg %r6,%r9,4095\(%r5\)
+ 222: eb 69 5f ff 00 96 [ ]*lmh %r6,%r9,4095\(%r5\)
+ 228: b9 11 00 69 [ ]*lngfr %r6,%r9
+ 22c: b9 01 00 69 [ ]*lngr %r6,%r9
+ 230: b9 10 00 69 [ ]*lpgfr %r6,%r9
+ 234: b9 00 00 69 [ ]*lpgr %r6,%r9
+ 238: e3 65 af ff 00 8f [ ]*lpq %r6,4095\(%r5,%r10\)
+ 23e: b2 b2 5f ff [ ]*lpswe 4095\(%r5\)
+ 242: e3 65 af ff 00 03 [ ]*lrag %r6,4095\(%r5,%r10\)
+ 248: e3 65 af ff 00 1e [ ]*lrv %r6,4095\(%r5,%r10\)
+ 24e: e3 65 af ff 00 0f [ ]*lrvg %r6,4095\(%r5,%r10\)
+ 254: b9 0f 00 69 [ ]*lrvgr %r6,%r9
+ 258: e3 65 af ff 00 1f [ ]*lrvh %r6,4095\(%r5,%r10\)
+ 25e: b9 1f 00 69 [ ]*lrvr %r6,%r9
+ 262: b9 12 00 69 [ ]*ltgfr %r6,%r9
+ 266: b9 02 00 69 [ ]*ltgr %r6,%r9
+ 26a: b9 05 00 69 [ ]*lurag %r6,%r9
+ 26e: b3 75 00 60 [ ]*lzdr %r6
+ 272: b3 74 00 60 [ ]*lzer %r6
+ 276: b3 76 00 60 [ ]*lzxr %r6
+ 27a: a7 6d 80 01 [ ]*mghi %r6,-32767
+ 27e: e3 65 af ff 00 96 [ ]*ml %r6,4095\(%r5,%r10\)
+ 284: e3 65 af ff 00 86 [ ]*mlg %r6,4095\(%r5,%r10\)
+ 28a: b9 86 00 69 [ ]*mlgr %r6,%r9
+ 28e: b9 96 00 69 [ ]*mlr %r6,%r9
+ 292: e3 65 af ff 00 0c [ ]*msg %r6,4095\(%r5,%r10\)
+ 298: e3 65 af ff 00 1c [ ]*msgf %r6,4095\(%r5,%r10\)
+ 29e: b9 1c 00 69 [ ]*msgfr %r6,%r9
+ 2a2: b9 0c 00 69 [ ]*msgr %r6,%r9
+ 2a6: eb 69 5f ff 00 8e [ ]*mvclu %r6,%r9,4095\(%r5\)
+ 2ac: e3 65 af ff 00 80 [ ]*ng %r6,4095\(%r5,%r10\)
+ 2b2: b9 80 00 69 [ ]*ngr %r6,%r9
+ 2b6: a5 64 ff ff [ ]*nihh %r6,65535
+ 2ba: a5 65 ff ff [ ]*nihl %r6,65535
+ 2be: a5 66 ff ff [ ]*nilh %r6,65535
+ 2c2: a5 67 ff ff [ ]*nill %r6,65535
+ 2c6: e3 65 af ff 00 81 [ ]*og %r6,4095\(%r5,%r10\)
+ 2cc: b9 81 00 69 [ ]*ogr %r6,%r9
+ 2d0: a5 68 ff ff [ ]*oihh %r6,65535
+ 2d4: a5 69 ff ff [ ]*oihl %r6,65535
+ 2d8: a5 6a ff ff [ ]*oilh %r6,65535
+ 2dc: a5 6b ff ff [ ]*oill %r6,65535
+ 2e0: e9 ff 5f ff af ff [ ]*pka 4095\(256,%r5\),4095\(%r10\)
+ 2e6: e1 ff 5f ff af ff [ ]*pku 4095\(256,%r5\),4095\(%r10\)
+ 2ec: eb 69 5f ff 00 1d [ ]*rll %r6,%r9,4095\(%r5\)
+ 2f2: eb 69 5f ff 00 1c [ ]*rllg %r6,%r9,4095\(%r5\)
+ 2f8: 01 0c [ ]*sam24
+ 2fa: 01 0d [ ]*sam31
+ 2fc: 01 0e [ ]*sam64
+ 2fe: e3 65 af ff 00 09 [ ]*sg %r6,4095\(%r5,%r10\)
+ 304: e3 65 af ff 00 19 [ ]*sgf %r6,4095\(%r5,%r10\)
+ 30a: b9 19 00 69 [ ]*sgfr %r6,%r9
+ 30e: b9 09 00 69 [ ]*sgr %r6,%r9
+ 312: eb 69 5f ff 00 0b [ ]*slag %r6,%r9,4095\(%r5\)
+ 318: e3 65 af ff 00 99 [ ]*slb %r6,4095\(%r5,%r10\)
+ 31e: e3 65 af ff 00 89 [ ]*slbg %r6,4095\(%r5,%r10\)
+ 324: b9 89 00 69 [ ]*slbgr %r6,%r9
+ 328: b9 99 00 69 [ ]*slbr %r6,%r9
+ 32c: e3 65 af ff 00 0b [ ]*slg %r6,4095\(%r5,%r10\)
+ 332: e3 65 af ff 00 1b [ ]*slgf %r6,4095\(%r5,%r10\)
+ 338: b9 1b 00 69 [ ]*slgfr %r6,%r9
+ 33c: b9 0b 00 69 [ ]*slgr %r6,%r9
+ 340: eb 69 5f ff 00 0d [ ]*sllg %r6,%r9,4095\(%r5\)
+ 346: eb 69 5f ff 00 0a [ ]*srag %r6,%r9,4095\(%r5\)
+ 34c: eb 69 5f ff 00 0c [ ]*srlg %r6,%r9,4095\(%r5\)
+ 352: b2 78 5f ff [ ]*stcke 4095\(%r5\)
+ 356: eb 6a 5f ff 00 2c [ ]*stcmh %r6,10,4095\(%r5\)
+ 35c: eb 69 5f ff 00 25 [ ]*stctg %r6,%r9,4095\(%r5\)
+ 362: b2 b1 5f ff [ ]*stfl 4095\(%r5\)
+ 366: e3 65 af ff 00 24 [ ]*stg %r6,4095\(%r5,%r10\)
+ 36c: eb 69 5f ff 00 24 [ ]*stmg %r6,%r9,4095\(%r5\)
+ 372: eb 69 5f ff 00 26 [ ]*stmh %r6,%r9,4095\(%r5\)
+ 378: e3 65 af ff 00 8e [ ]*stpq %r6,4095\(%r5,%r10\)
+ 37e: e5 00 5f ff 9f ff [ ]*lasp 4095\(%r5\),4095\(%r9\)
+ 384: e3 65 af ff 00 3e [ ]*strv %r6,4095\(%r5,%r10\)
+ 38a: e3 65 af ff 00 2f [ ]*strvg %r6,4095\(%r5,%r10\)
+ 390: e3 65 af ff 00 3f [ ]*strvh %r6,4095\(%r5,%r10\)
+ 396: b9 25 00 69 [ ]*sturg %r6,%r9
+ 39a: 01 0b [ ]*tam
+ 39c: b3 51 f0 69 [ ]*tbdr %f6,15,%f9
+ 3a0: b3 50 f0 69 [ ]*tbedr %f6,15,%f9
+ 3a4: b3 58 00 69 [ ]*thder %r6,%r9
+ 3a8: b3 59 00 69 [ ]*thdr %r6,%r9
+ 3ac: a7 62 ff ff [ ]*tmhh %r6,65535
+ 3b0: a7 63 ff ff [ ]*tmhl %r6,65535
+ 3b4: a7 60 ff ff [ ]*tmh %r6,65535
+ 3b8: a7 61 ff ff [ ]*tml %r6,65535
+ 3bc: eb 69 5f ff 00 0f [ ]*tracg %r6,%r9,4095\(%r5\)
+ 3c2: b2 a5 00 69 [ ]*tre %r6,%r9
+ 3c6: b9 93 00 69 [ ]*troo %r6,%r9
+ 3ca: b9 92 00 69 [ ]*trot %r6,%r9
+ 3ce: b9 91 00 69 [ ]*trto %r6,%r9
+ 3d2: b9 90 00 69 [ ]*trtt %r6,%r9
+ 3d6: ea ff 5f ff af ff [ ]*unpka 4095\(256,%r5\),4095\(%r10\)
+ 3dc: e2 ff 5f ff af ff [ ]*unpku 4095\(256,%r5\),4095\(%r10\)
+ 3e2: e3 65 af ff 00 82 [ ]*xg %r6,4095\(%r5,%r10\)
+ 3e8: b9 82 00 69 [ ]*xgr %r6,%r9
diff -urN src/gas/testsuite/gas/s390/opcode64.s src-s390/gas/testsuite/gas/s390/opcode64.s
--- src/gas/testsuite/gas/s390/opcode64.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode64.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,205 @@
+.text
+foo:
+ ag %r9,4095(%r5,%r10)
+ agf %r9,4095(%r5,%r10)
+ agfr %r9,%r6
+ aghi %r9,-32767
+ agr %r9,%r6
+ alc %r9,4095(%r5,%r10)
+ alcg %r9,4095(%r5,%r10)
+ alcgr %r9,%r6
+ alcr %r9,%r6
+ alg %r9,4095(%r5,%r10)
+ algf %r9,4095(%r5,%r10)
+ algfr %r9,%r6
+ algr %r9,%r6
+ bctg %r6,4095(%r5,%r10)
+ bctgr %r6,%r9
+ brasl %r6,.
+ brcl 15,.
+ brctg %r6,.
+ brxhg %r6,%r9,.
+ brxlg %r6,%r9,.
+ bxhg %r6,%r9,4095(%r5)
+ bxleg %r6,%r9,4095(%r5)
+ cdgbr %r6,%r9
+ cdgr %r6,%r9
+ cdsg %r6,%r9,4095(%r5)
+ cegbr %r6,%r9
+ cegr %r6,%r9
+ cg %r6,4095(%r5,%r10)
+ cgdbr %r6,15,%r9
+ cgdr %f6,9,%r5
+ cgebr %r6,15,%r9
+ cger %f6,9,%r5
+ cgf %r6,4095(%r5,%r10)
+ cgfr %r6,%r9
+ cghi %r6,-32767
+ cgr %r6,%r9
+ cgxbr %r6,15,%r9
+ cgxr %f6,9,%r5
+ clg %r6,4095(%r5,%r10)
+ clgf %r6,4095(%r5,%r10)
+ clgfr %r6,%r9
+ clgr %r6,%r9
+ clmh %r6,10,4095(%r5)
+ csg %r6,%r9,4095(%r5)
+ cvbg %r6,4095(%r5,%r10)
+ cvdg %r6,4095(%r5,%r10)
+ cxgbr %r6,%r9
+ cxgr %r6,%r9
+ dl %r6,4095(%r5,%r10)
+ dlg %r6,4095(%r5,%r10)
+ dlgr %r6,%r9
+ dlr %r6,%r9
+ dsg %r6,4095(%r5,%r10)
+ dsgf %r6,4095(%r5,%r10)
+ dsgfr %r6,%r9
+ dsgr %r6,%r9
+ epsw %r6,%r9
+ eregg %r6,%r9
+ esea %r6
+ icmh %r6,10,4095(%r5)
+ iihh %r6,65535
+ iihl %r6,65535
+ iilh %r6,65535
+ iill %r6,65535
+ jg .
+ jge .
+ jgh .
+ jghe .
+ jgl .
+ jgle .
+ jglh .
+ jgm .
+ jgne .
+ jgnh .
+ jgnhe .
+ jgnl .
+ jgnle .
+ jgnlh .
+ jgnm .
+ jgno .
+ jgnp .
+ jgnz .
+ jgo .
+ jgp .
+ jgz .
+ larl %r6,.
+ lcgfr %r6,%r9
+ lcgr %r6,%r9
+ lctlg %r6,%r9,4095(%r5)
+ lg %r6,4095(%r5,%r10)
+ lgf %r6,4095(%r5,%r10)
+ lgfr %r6,%r9
+ lgh %r6,4095(%r5,%r10)
+ lghi %r6,-32767
+ lgr %r6,%r9
+ llgc %r6,4095(%r5,%r10)
+ llgf %r6,4095(%r5,%r10)
+ llgfr %r6,%r9
+ llgh %r6,4095(%r5,%r10)
+ llgt %r6,4095(%r5,%r10)
+ llgtr %r6,%r9
+ llihh %r6,65535
+ llihl %r6,65535
+ llilh %r6,65535
+ llill %r6,65535
+ lmd %r6,%r9,4095(%r5),4095(%r10)
+ lmg %r6,%r9,4095(%r5)
+ lmh %r6,%r9,4095(%r5)
+ lngfr %r6,%r9
+ lngr %r6,%r9
+ lpgfr %r6,%r9
+ lpgr %r6,%r9
+ lpq %r6,4095(%r5,%r10)
+ lpswe 4095(%r5)
+ lrag %r6,4095(%r5,%r10)
+ lrv %r6,4095(%r5,%r10)
+ lrvg %r6,4095(%r5,%r10)
+ lrvgr %r6,%r9
+ lrvh %r6,4095(%r5,%r10)
+ lrvr %r6,%r9
+ ltgfr %r6,%r9
+ ltgr %r6,%r9
+ lurag %r6,%r9
+ lzdr %r6
+ lzer %r6
+ lzxr %r6
+ mghi %r6,-32767
+ ml %r6,4095(%r5,%r10)
+ mlg %r6,4095(%r5,%r10)
+ mlgr %r6,%r9
+ mlr %r6,%r9
+ msg %r6,4095(%r5,%r10)
+ msgf %r6,4095(%r5,%r10)
+ msgfr %r6,%r9
+ msgr %r6,%r9
+ mvclu %r6,%r9,4095(%r5)
+ ng %r6,4095(%r5,%r10)
+ ngr %r6,%r9
+ nihh %r6,65535
+ nihl %r6,65535
+ nilh %r6,65535
+ nill %r6,65535
+ og %r6,4095(%r5,%r10)
+ ogr %r6,%r9
+ oihh %r6,65535
+ oihl %r6,65535
+ oilh %r6,65535
+ oill %r6,65535
+ pka 4095(256,%r5),4095(%r10)
+ pku 4095(256,%r5),4095(%r10)
+ rll %r6,%r9,4095(%r5)
+ rllg %r6,%r9,4095(%r5)
+ sam24
+ sam31
+ sam64
+ sg %r6,4095(%r5,%r10)
+ sgf %r6,4095(%r5,%r10)
+ sgfr %r6,%r9
+ sgr %r6,%r9
+ slag %r6,%r9,4095(%r5)
+ slb %r6,4095(%r5,%r10)
+ slbg %r6,4095(%r5,%r10)
+ slbgr %r6,%r9
+ slbr %r6,%r9
+ slg %r6,4095(%r5,%r10)
+ slgf %r6,4095(%r5,%r10)
+ slgfr %r6,%r9
+ slgr %r6,%r9
+ sllg %r6,%r9,4095(%r5)
+ srag %r6,%r9,4095(%r5)
+ srlg %r6,%r9,4095(%r5)
+ stcke 4095(%r5)
+ stcmh %r6,10,4095(%r5)
+ stctg %r6,%r9,4095(%r5)
+ stfl 4095(%r5)
+ stg %r6,4095(%r5,%r10)
+ stmg %r6,%r9,4095(%r5)
+ stmh %r6,%r9,4095(%r5)
+ stpq %r6,4095(%r5,%r10)
+ strag 4095(%r5),4095(%r9)
+ strv %r6,4095(%r5,%r10)
+ strvg %r6,4095(%r5,%r10)
+ strvh %r6,4095(%r5,%r10)
+ sturg %r6,%r9
+ tam
+ tbdr %r6,15,%r9
+ tbedr %r6,15,%r9
+ thder %r6,%r9
+ thdr %r6,%r9
+ tmhh %r6,65535
+ tmhl %r6,65535
+ tmlh %r6,65535
+ tmll %r6,65535
+ tracg %r6,%r9,4095(%r5)
+ tre %r6,%r9
+ troo %r6,%r9
+ trot %r6,%r9
+ trto %r6,%r9
+ trtt %r6,%r9
+ unpka 4095(256,%r5),4095(%r10)
+ unpku 4095(256,%r5),4095(%r10)
+ xg %r6,4095(%r5,%r10)
+ xgr %r6,%r9
diff -urN src/gas/testsuite/gas/s390/operands.d src-s390/gas/testsuite/gas/s390/operands.d
--- src/gas/testsuite/gas/s390/operands.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,23 @@
+#name: s390 operands
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: 01 01 [ ]*pr
+ 2: a7 1a 80 01 [ ]*ahi %r1,-32767
+ 6: 18 12 [ ]*lr %r1,%r2
+ 8: b2 5e 00 12 [ ]*srst %r1,%r2
+ c: b3 5b 93 12 [ ]*didbr %f1,%f9,%f2,3
+ 10: ba 12 40 03 [ ]*cs %r1,%r2,3\(%r4\)
+ 14: 84 12 00 00 [ ]*brxh %r1,%r2,14 <foo\+0x14>
+[ ]*16: R_390_PC16DBL test_rsi\+0x2
+ 18: 58 13 40 02 [ ]*l %r1,2\(%r3,%r4\)
+ 1c: ed 10 30 02 00 1a [ ]*adb %f1,2\(%r3\)
+ 22: ed 24 50 03 10 1e [ ]*madb %f1,%f2,3\(%r4,%r5\)
+ 28: b2 33 20 01 [ ]*ssch 1\(%r2\)
+ 2c: 92 03 20 01 [ ]*mvi 1\(%r2\),3
+ 30: d2 26 30 01 50 04 [ ]*mvc 1\(39,%r3\),4\(%r5\)
+ 36: e5 01 20 01 40 03 [ ]*tprot 1\(%r2\),3\(%r4\)
diff -urN src/gas/testsuite/gas/s390/operands.s src-s390/gas/testsuite/gas/s390/operands.s
--- src/gas/testsuite/gas/s390/operands.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,16 @@
+.text
+foo:
+ .insn e,0x0101
+ .insn ri,0xa70a0000,%r1,-32767
+ .insn rr,0x1800,%r1,%r2
+ .insn rre,0xb25e0000,%r1,%r2
+ .insn rrf,0xb35b0000,%f1,%f2,9,%f3
+ .insn rs,0xba000000,%r1,%r2,3(%r4)
+ .insn rsi,0x84000000,%r1,%r2,test_rsi
+ .insn rx,0x58000000,%r1,2(%r3,%r4)
+ .insn rxe,0xed000000001a,%f1,2(%r3)
+ .insn rxf,0xed000000001e,%f1,%f2,3(%r4,%r5)
+ .insn s,0xb2330000,1(%r2)
+ .insn si,0x92000000,1(%r2),3
+ .insn ss,0xd20000000000,1(2,%r3),4(%r5),6
+ .insn sse,0xe50100000000,1(%r2),3(%r4)
diff -urN src/gas/testsuite/gas/s390/operands64.d src-s390/gas/testsuite/gas/s390/operands64.d
--- src/gas/testsuite/gas/s390/operands64.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands64.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,14 @@
+#name: s390x operands
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: ec 12 00 00 00 45 [ ]*brxlg %r1,%r2,0 <foo>
+[ ]*2: R_390_PC16DBL test_rie\+0x2
+ 6: c0 e5 00 00 00 00 [ ]*brasl %r14,6 <foo\+0x6>
+[ ]*8: R_390_PC32DBL test_ril\+0x2
+ c: eb 12 40 03 00 0d [ ]*sllg %r1,%r2,3\(%r4\)
+ 12: 07 07 [ ]*bcr 0,%r7
diff -urN src/gas/testsuite/gas/s390/operands64.s src-s390/gas/testsuite/gas/s390/operands64.s
--- src/gas/testsuite/gas/s390/operands64.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands64.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,6 @@
+.text
+foo:
+ .insn rie,0xec0000000045,%r1,%r2,test_rie
+ .insn ril,0xc00500000000,%r14,test_ril
+ .insn rse,0xeb000000000d,%r1,%r2,3(%r4)
+
diff -urN src/gas/testsuite/gas/s390/reloc.d src-s390/gas/testsuite/gas/s390/reloc.d
--- src/gas/testsuite/gas/s390/reloc.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,31 @@
+#name: s390 reloc
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: d2 00 10 00 20 00 [ ]*mvc 0\(1,%r1\),0\(%r2\)
+[ ]*1: R_390_8 test_R_390_8
+ 6: 58 01 20 00 [ ]*l %r0,0\(%r1,%r2\)
+[ ]*8: R_390_12 test_R_390_12
+ a: a7 08 00 00 [ ]*lhi %r0,0
+[ ]*c: R_390_16 test_R_390_16
+[ ]*...
+[ ]*e: R_390_32 test_R_390_32
+[ ]*12: R_390_PC32 test_R_390_PC32\+0x12
+ 16: 58 01 20 00 [ ]*l %r0,0\(%r1,%r2\)
+[ ]*18: R_390_GOT12 test_R_390_GOT12
+[ ]*...
+[ ]*1a: R_390_GOT32 test_R_390_GOT32
+[ ]*1e: R_390_PLT32 test_R_390_PLT32
+ 22: a7 08 00 00 [ ]*lhi %r0,0
+[ ]*24: R_390_GOT16 test_R_390_GOT16
+ 26: a7 08 00 00 [ ]*lhi %r0,0
+[ ]*28: R_390_16 test_R_390_PC16\+0x26
+ 2a: a7 e5 00 00 [ ]*bras %r14,2a <foo\+0x2a>
+[ ]*2c: R_390_PC16DBL test_R_390_PC16DBL\+0x2
+ 2e: a7 e5 00 00 [ ]*bras %r14,2e <foo\+0x2e>
+[ ]*30: R_390_PC16DBL test_R_390_PLT16DBL\+0x2
+ 32: 07 07 [ ]*bcr 0,%r7
diff -urN src/gas/testsuite/gas/s390/reloc.s src-s390/gas/testsuite/gas/s390/reloc.s
--- src/gas/testsuite/gas/s390/reloc.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,14 @@
+.text
+foo:
+ mvc 0(test_R_390_8,%r1),0(%r2)
+ l %r0,test_R_390_12(%r1,%r2)
+ lhi %r0,test_R_390_16
+ .long test_R_390_32
+ .long test_R_390_PC32-foo
+ l %r0,test_R_390_GOT12@GOT(%r1,%r2)
+ .long test_R_390_GOT32@GOT
+ .long test_R_390_PLT32@PLT
+ lhi %r0,test_R_390_GOT16@GOT
+ lhi %r0,test_R_390_PC16-foo
+ bras %r14,test_R_390_PC16DBL
+ bras %r14,test_R_390_PLT16DBL
diff -urN src/gas/testsuite/gas/s390/reloc64.d src-s390/gas/testsuite/gas/s390/reloc64.d
--- src/gas/testsuite/gas/s390/reloc64.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc64.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,20 @@
+#name: s390x reloc
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: c0 e5 00 00 00 00 [ ]*brasl %r14,0 <foo>
+[ ]*2: R_390_PC32DBL test_R_390_PC32DBL\+0x2
+ 6: c0 e5 00 00 00 00 [ ]*brasl %r14,6 <foo\+0x6>
+[ ]*8: R_390_PC32DBL test_R_390_PLT32DBL\+0x2
+[ ]*...
+[ ]*c: R_390_64 test_R_390_64
+[ ]*14: R_390_PC64 test_R_390_PC64\+0x14
+[ ]*1c: R_390_GOT64 test_R_390_GOT64
+[ ]*24: R_390_PLT64 test_R_390_PLT64
+ 2c: c0 10 00 00 00 00 [ ]*larl %r1,2c <foo\+0x2c>
+[ ]*2e: R_390_GOTENT test_R_390_GOTENT\+0x2
+ 32: 07 07 [ ]*bcr 0,%r7
diff -urN src/gas/testsuite/gas/s390/reloc64.s src-s390/gas/testsuite/gas/s390/reloc64.s
--- src/gas/testsuite/gas/s390/reloc64.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc64.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,9 @@
+.text
+foo:
+ brasl %r14,test_R_390_PC32DBL
+ brasl %r14,test_R_390_PLT32DBL
+ .quad test_R_390_64
+ .quad test_R_390_PC64-foo
+ .quad test_R_390_GOT64@GOT
+ .quad test_R_390_PLT64@PLT
+ larl %r1,test_R_390_GOTENT@GOT
diff -urN src/gas/testsuite/gas/s390/s390.exp src-s390/gas/testsuite/gas/s390/s390.exp
--- src/gas/testsuite/gas/s390/s390.exp Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/s390.exp Fri Sep 14 18:47:22 2001
@@ -0,0 +1,35 @@
+#
+# s390/s390x tests
+#
+proc run_list_test { name opts } {
+ global srcdir subdir
+ set testname "s390 $name"
+ set file $srcdir/$subdir/$name
+ gas_run ${name}.s $opts ">&dump.out"
+ if { [regexp_diff "dump.out" "${file}.l"] } then {
+ fail $testname
+ verbose "output is [file_contents "dump.out"]" 2
+ exit
+ return
+ }
+ pass $testname
+}
+
+if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then {
+
+ run_dump_test "opcode"
+ run_dump_test "reloc"
+ run_dump_test "operands"
+
+# # PIC is only supported on ELF targets.
+# if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"] ) } then {
+# run_dump_test "s390pic"
+# }
+}
+
+if [istarget "s390x-*-*"] then {
+
+ run_dump_test "opcode64"
+ run_dump_test "reloc64"
+ run_dump_test "operands64"
+}
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
2001-09-14 13:10 Martin Schwidefsky
@ 2001-09-14 13:18 ` DJ Delorie
0 siblings, 0 replies; 14+ messages in thread
From: DJ Delorie @ 2001-09-14 13:18 UTC (permalink / raw)
To: schwidefsky; +Cc: binutils
That looks OK to me. Don't forget the ChangeLog entry, and review the
diffs for configure to make sure you aren't making spurious changes
due to autoconf version drift, post the final patch with the other
changes, and I'll re-review it. Whew.
> Index: configure.in
> ===================================================================
> RCS file: /cvs/src/src/opcodes/configure.in,v
> retrieving revision 1.22
> diff -u -r1.22 configure.in
> --- configure.in 2001/08/10 10:56:46 1.22
> +++ configure.in 2001/09/14 20:09:34
> @@ -82,6 +82,8 @@
>
> . ${srcdir}/../bfd/configure.host
>
> +BFD_CC_FOR_BUILD
> +
> AC_SUBST(HDEFINES)
> AC_PROG_INSTALL
>
> What do you think?
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
@ 2001-09-14 13:10 Martin Schwidefsky
2001-09-14 13:18 ` DJ Delorie
0 siblings, 1 reply; 14+ messages in thread
From: Martin Schwidefsky @ 2001-09-14 13:10 UTC (permalink / raw)
To: DJ Delorie; +Cc: binutils
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 746 bytes --]
>If you want to add logic to set CC_FOR_BUILD properly in
>opcodes/configure, that would be OK.
Ok, I think I found an easy way to do this:
Index: configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.22
diff -u -r1.22 configure.in
--- configure.in 2001/08/10 10:56:46 1.22
+++ configure.in 2001/09/14 20:09:34
@@ -82,6 +82,8 @@
. ${srcdir}/../bfd/configure.host
+BFD_CC_FOR_BUILD
+
AC_SUBST(HDEFINES)
AC_PROG_INSTALL
What do you think?
blue skies,
Martin
Linux/390 Design & Development, IBM Deutschland Entwicklung GmbH
Schönaicherstr. 220, D-71032 Böblingen, Telefon: 49 - (0)7031 - 16-2247
E-Mail: schwidefsky@de.ibm.com
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
2001-09-14 12:46 Martin Schwidefsky
@ 2001-09-14 12:50 ` DJ Delorie
0 siblings, 0 replies; 14+ messages in thread
From: DJ Delorie @ 2001-09-14 12:50 UTC (permalink / raw)
To: schwidefsky; +Cc: binutils
> Any reason why I can't/shouldn't use CC_FOR_BUILD ??
Because it's not defined by configure. Look for it in your build's
opcodes/Makefile and you'll see this:
CC_FOR_BUILD = @CC_FOR_BUILD@
The only time you can use this is when you call "make" from the top of
the tree, and only because the top Makefile overrides this when it
runs opcodes's Makefile. However, if you type "make" in opcodes, it
will break.
If you want to add logic to set CC_FOR_BUILD properly in
opcodes/configure, that would be OK.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
@ 2001-09-14 12:46 Martin Schwidefsky
2001-09-14 12:50 ` DJ Delorie
0 siblings, 1 reply; 14+ messages in thread
From: Martin Schwidefsky @ 2001-09-14 12:46 UTC (permalink / raw)
To: DJ Delorie; +Cc: binutils
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 934 bytes --]
>> Hmm, if --host doesn't match --build it doesn't work though. Too bad.
Any
>> idea how to fix this?
>
>1. Use a portable shell script (ick).
>
>2. Go through gyrations to find a native compiler (like gcc does).
>
>3. Make it a maintainer-mode-only thing, and also stipulate native
> only in configure, so it just doesn't run when it can't (you'd have
> to worry about updating a file in the source tree, which might be
> on a read-only filesystem).
>
>4. Just don't do that :-)
What about 5:
s390-mkopc: s390-mkopc.c
$(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c
s390-opc.tab: s390-mkopc s390-opc.txt
./s390-mkopc < $(srcdir)/src-opc.txt > s390-opc.tab
Any reason why I can't/shouldn't use CC_FOR_BUILD ??
blue skies,
Martin
Linux/390 Design & Development, IBM Deutschland Entwicklung GmbH
Schönaicherstr. 220, D-71032 Böblingen, Telefon: 49 - (0)7031 - 16-2247
E-Mail: schwidefsky@de.ibm.com
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
2001-09-14 12:31 Martin Schwidefsky
@ 2001-09-14 12:34 ` DJ Delorie
0 siblings, 0 replies; 14+ messages in thread
From: DJ Delorie @ 2001-09-14 12:34 UTC (permalink / raw)
To: schwidefsky; +Cc: binutils
> Hmm, if --host doesn't match --build it doesn't work though. Too bad. Any
> idea how to fix this?
1. Use a portable shell script (ick).
2. Go through gyrations to find a native compiler (like gcc does).
3. Make it a maintainer-mode-only thing, and also stipulate native
only in configure, so it just doesn't run when it can't (you'd have
to worry about updating a file in the source tree, which might be
on a read-only filesystem).
4. Just don't do that :-)
I'm not sure which makes the most sense, though.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
@ 2001-09-14 12:31 Martin Schwidefsky
2001-09-14 12:34 ` DJ Delorie
0 siblings, 1 reply; 14+ messages in thread
From: Martin Schwidefsky @ 2001-09-14 12:31 UTC (permalink / raw)
To: DJ Delorie; +Cc: binutils
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 739 bytes --]
>>You can't do this, because the machine you're building on won't always
>>be the machine you're building for or the machine you're targetting.
>>
>>+s390-mkopc: s390-mkopc.o
>>+ $(LINK) s390-mkopc.o $(LIBIBERY)
>>+
>>+s390-mkopc.o: s390-mkopc.c
>>+
>>+s390-opc.tab: s390-mkopc s390-opc.txt
>>+ ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab
>>+
>
>At least cross compiling the s/390 binutils on my Intel machine works fine.
Hmm, if --host doesn't match --build it doesn't work though. Too bad. Any
idea how to fix this?
blue skies,
Martin
Linux/390 Design & Development, IBM Deutschland Entwicklung GmbH
Schönaicherstr. 220, D-71032 Böblingen, Telefon: 49 - (0)7031 - 16-2247
E-Mail: schwidefsky@de.ibm.com
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
2001-09-14 12:24 Martin Schwidefsky
@ 2001-09-14 12:27 ` DJ Delorie
0 siblings, 0 replies; 14+ messages in thread
From: DJ Delorie @ 2001-09-14 12:27 UTC (permalink / raw)
To: schwidefsky; +Cc: binutils
Consider using a Solaris box to cross-build a cygwin->s/390 cross
compiler. This is probably the hardest case to get right (and the one
most often forgotten!)
When you build s390-mkopc you're using a cross compiler. The
resulting s390-mkopc binary runs on cygwin, but you're building on
Solaris. You can't run it.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
@ 2001-09-14 12:24 Martin Schwidefsky
2001-09-14 12:27 ` DJ Delorie
0 siblings, 1 reply; 14+ messages in thread
From: Martin Schwidefsky @ 2001-09-14 12:24 UTC (permalink / raw)
To: DJ Delorie; +Cc: binutils
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 629 bytes --]
>You can't do this, because the machine you're building on won't always
>be the machine you're building for or the machine you're targetting.
>
>+s390-mkopc: s390-mkopc.o
>+ $(LINK) s390-mkopc.o $(LIBIBERY)
>+
>+s390-mkopc.o: s390-mkopc.c
>+
>+s390-opc.tab: s390-mkopc s390-opc.txt
>+ ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab
>+
At least cross compiling the s/390 binutils on my Intel machine works fine.
blue skies,
Martin
Linux/390 Design & Development, IBM Deutschland Entwicklung GmbH
Schönaicherstr. 220, D-71032 Böblingen, Telefon: 49 - (0)7031 - 16-2247
E-Mail: schwidefsky@de.ibm.com
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Automatic opcode table generation and gas test cases for s/390.
2001-09-14 12:06 Martin Schwidefsky
@ 2001-09-14 12:14 ` DJ Delorie
0 siblings, 0 replies; 14+ messages in thread
From: DJ Delorie @ 2001-09-14 12:14 UTC (permalink / raw)
To: schwidefsky; +Cc: binutils
You can't do this, because the machine you're building on won't always
be the machine you're building for or the machine you're targetting.
+s390-mkopc: s390-mkopc.o
+ $(LINK) s390-mkopc.o $(LIBIBERY)
+
+s390-mkopc.o: s390-mkopc.c
+
+s390-opc.tab: s390-mkopc s390-opc.txt
+ ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab
+
^ permalink raw reply [flat|nested] 14+ messages in thread
* Automatic opcode table generation and gas test cases for s/390.
@ 2001-09-14 12:06 Martin Schwidefsky
2001-09-14 12:14 ` DJ Delorie
0 siblings, 1 reply; 14+ messages in thread
From: Martin Schwidefsky @ 2001-09-14 12:06 UTC (permalink / raw)
To: binutils
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 2388 bytes --]
Hi,
I found some time and could do some improvements to the s/390 backend
of the binutils. I have two patches that I'd like to get integrated:
1) binutils-optab390.diff
I have changed the macros that are used to define the opcode table. I
find the new method much more sensible since it is easier to choose
the correct format just by looking at the binary representation of the
instruction. In addition I removed the pregenerated opcode table from
s390-opc.c and modified the make process so that the opcode table is
generated automagically from s390-opc.txt.
ChangeLog for gas:
2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
* tc-s390.c (s390_insn): Add code to cope with 6 byte O_constants
in 64 bit mode and make format "e" work.
ChangeLog for opcodes:
2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
* Makefile.am: Add rules and dependencies to create the s/390 opcode
table out of s390-opc.txt automatically.
* s390-mkopc.c (dumpTable): Change output to create a complete file.
* s390-opc.c: New improved opcode format macros and remove the
pregenerated opcode table.
* s390-opc.txt: Adapt to new improved opcode format macros.
(See attached file: binutils-optab390.diff)
2) binutils-test390.diff
This second patch is dependent on the first and adds test cases for
the S/390 gas. opcode.s and opcode64.s test the 31 and 64 bit
instructions, operands.s and operands64.s test the .insn pseudo
instruction with the different instruction formats and reloc.s
and reloc64.s test the special s/390 relocations.
ChangeLog for gas/testsuite:
2001-09-14 Martin Schwidefsky <schwidefsky@de.ibm.com>
* gas/s390/opcode.d: New file.
* gas/s390/opcode.s: New file.
* gas/s390/opcode64.d: New file.
* gas/s390/opcode64.s: New file.
* gas/s390/operands.d: New file.
* gas/s390/operands.s: New file.
* gas/s390/operands64.d: New file.
* gas/s390/operands64.s: New file.
* gas/s390/reloc.d: New file.
* gas/s390/reloc.s: New file.
* gas/s390/reloc64.d: New file.
* gas/s390/reloc64.s: New file.
* gas/s390/s390.exp: New file.
(See attached file: binutils-test390.diff)
blue skies,
Martin
Linux/390 Design & Development, IBM Deutschland Entwicklung GmbH
Schönaicherstr. 220, D-71032 Böblingen, Telefon: 49 - (0)7031 - 16-2247
E-Mail: schwidefsky@de.ibm.com
[-- Attachment #2: binutils-optab390.diff --]
[-- Type: text/x-diff, Size: 119207 bytes --]
diff -urN src/gas/config/tc-s390.c src-s390/gas/config/tc-s390.c
--- src/gas/config/tc-s390.c Fri Sep 14 15:57:42 2001
+++ src-s390/gas/config/tc-s390.c Fri Sep 14 18:23:52 2001
@@ -1354,8 +1354,9 @@
expression (&exp);
if (exp.X_op == O_constant)
{
- if (opformat->oplen == 4 ||
- (opformat->oplen == 2 && exp.X_op < 0x10000))
+ if ((opformat->oplen == 6 && exp.X_op > 0 && exp.X_op < (1ULL << 48)) ||
+ (opformat->oplen == 4 && exp.X_op > 0 && exp.X_op < (1ULL << 32)) ||
+ (opformat->oplen == 2 && exp.X_op > 0 && exp.X_op < (1ULL << 16)))
md_number_to_chars (insn, exp.X_add_number, opformat->oplen);
else
as_bad (_("Invalid .insn format\n"));
@@ -1375,12 +1376,14 @@
}
else
as_bad (_("second operand of .insn not a constant\n"));
- if (*input_line_pointer++ != ',')
- as_bad (_("missing comma after insn constant\n"));
+ if (strcmp(opformat->name, "e") != 0 && *input_line_pointer++ != ',')
+ as_bad (_("missing comma after insn constant\n"));
+
if ((s = strchr (input_line_pointer, '\n')) != NULL)
*s = '\0';
- input_line_pointer = md_gather_operands (input_line_pointer, insn, opformat);
+ input_line_pointer = md_gather_operands (input_line_pointer, insn,
+ opformat);
if (s != NULL)
*s = '\n';
demand_empty_rest_of_line ();
diff -urN src/opcodes/Makefile.am src-s390/opcodes/Makefile.am
--- src/opcodes/Makefile.am Thu Jul 26 21:09:11 2001
+++ src-s390/opcodes/Makefile.am Fri Sep 14 18:23:52 2001
@@ -109,6 +109,7 @@
pj-opc.c \
ppc-dis.c \
ppc-opc.c \
+ s390-mkopc.c \
s390-opc.c \
s390-dis.c \
sh-dis.c \
@@ -305,6 +306,14 @@
ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c
+s390-mkopc: s390-mkopc.o
+ $(LINK) s390-mkopc.o $(LIBIBERY)
+
+s390-mkopc.o: s390-mkopc.c
+
+s390-opc.tab: s390-mkopc s390-opc.txt
+ ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab
+
# This dependency stuff is copied from BFD.
DEP: dep.sed $(CFILES) $(HFILES) config.h
@@ -526,7 +535,8 @@
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h
ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/opcode/ppc.h opintl.h
-s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h
+s390-opc.lo: s390-opc.c s390-opc.tab $(INCDIR)/ansidecl.h \
+ $(INCDIR)/opcode/s390.h
s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/s390.h
sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff -urN src/opcodes/s390-mkopc.c src-s390/opcodes/s390-mkopc.c
--- src/opcodes/s390-mkopc.c Thu Mar 15 11:50:43 2001
+++ src-s390/opcodes/s390-mkopc.c Fri Sep 14 18:23:52 2001
@@ -99,6 +99,18 @@
no_ops++;
}
+static char file_header[] =
+ "/* The opcode table. This file was generated by s390-mkopc.\n\n"
+ " The format of the opcode table is:\n\n"
+ " NAME OPCODE MASK OPERANDS\n\n"
+ " Name is the name of the instruction.\n"
+ " OPCODE is the instruction opcode.\n"
+ " MASK is the opcode mask; this is used to tell the disassembler\n"
+ " which bits in the actual opcode must match OPCODE.\n"
+ " OPERANDS is the list of operands.\n\n"
+ " The disassembler reads the table in order and prints the first\n"
+ " instruction which matches. */\n\n"
+ "const struct s390_opcode s390_opcodes[] =\n {\n";
/*
* `dumpTable': write opcode table
@@ -110,7 +122,7 @@
int ix;
/* Write hash table entries (slots). */
- printf("const struct s390_opcode s390_opcodes[] = {\n");
+ printf(file_header);
for (ix = 0; ix < no_ops; ix++) {
printf(" { \"%s\", ", op_array[ix].mnemonic);
for (str = op_array[ix].opcode; *str != 0; str++)
diff -urN src/opcodes/s390-opc.c src-s390/opcodes/s390-opc.c
--- src/opcodes/s390-opc.c Fri Sep 14 16:00:09 2001
+++ src-s390/opcodes/s390-opc.c Fri Sep 14 18:26:03 2001
@@ -137,857 +137,182 @@
#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
(x >> 16) & 255, (x >> 8) & 255, x & 255}
-#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
-#define INSTR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
-#define INSTR_RR_M 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
-#define INSTR_RR_B 2, { R_12, 0,0,0,0,0 } /* e.g. br */
-#define INSTR_RR_I 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
-#define INSTR_RR_R 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
-#define INSTR_RR_E 2, { R_8,R_12,0,0,0,0 } /* e.g. aer */
-#define INSTR_RR_D 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
-#define INSTR_RR_X 2, { R_8,R_12,0,0,0,0 } /* e.g. mxr */
-#define INSTR_RR_ED 2, { F_8,F_12,0,0,0,0 } /* e.g. mer */
-#define INSTR_RR_DE 2, { F_8,F_12,0,0,0,0 } /* e.g. lrer */
-#define INSTR_RR_DX 2, { F_8,F_12,0,0,0,0 } /* e.g. mxdr */
-#define INSTR_RR_XD 2, { F_8,F_12,0,0,0,0 } /* e.g. lrdr */
-#define INSTR_RRE 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
-#define INSTR_RRE_A 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
-#define INSTR_RRE_F 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
-#define INSTR_RRE_O 4, { 0,0,0,0,0,0 } /* e.g. palb */
-#define INSTR_RRE_R 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
-#define INSTR_RRE_R2 4, { R_28,0,0,0,0,0 } /* e.g. tb */
-#define INSTR_RRE_E 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
-#define INSTR_RRE_D 4, { F_24,0,0,0,0,0 } /* e.g. sqdr */
-#define INSTR_RRE_X 4, { F_24,0,0,0,0,0 } /* e.g. dxr */
-#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
-#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
-#define INSTR_RRF_M 4, { R_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr*/
-#define INSTR_RRF_RM 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. didbr*/
-#define INSTR_RRF_R 4, { R_16,R_24,R_28,0,0,0 } /* e.g. madbr*/
-#define INSTR_RRF_F 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr*/
-#define INSTR_RS 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
-#define INSTR_RS_A 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
-#define INSTR_RS_C 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
-#define INSTR_RS_M 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
-#define INSTR_RS_S 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
-#define INSTR_RS_D 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sldl */
-#define INSTR_RX 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
-#define INSTR_RX_M 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
-#define INSTR_RX_B 4, { D_20,X_12,B_16,0,0,0 } /* e.g. b */
-#define INSTR_RX_E 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
-#define INSTR_RX_D 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ad */
-#define INSTR_RX_ED 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. me */
-#define INSTR_RX_DX 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */
-#define INSTR_RXE 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. agr */
-#define INSTR_RXE_F 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
-#define INSTR_RXF 6, { F_32,D_20,X_12,B_16,F_8,0 } /* e.g. madb */
-#define INSTR_S 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
-#define INSTR_S_O 4, { 0,0,0,0,0,0 } /* e.g. hsch */
-#define INSTR_SI 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
-#define INSTR_SS_RR 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
-#define INSTR_SS_LL 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
-#define INSTR_SS_LI 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
-#define INSTR_SS_L 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
-#define INSTR_SS_LMD 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
-#define INSTR_SS_PLO 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
-#define INSTR_SSE 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
-#define INSTR_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
-#define INSTR_RI_U 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
-#define INSTR_RI_A 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
-#define INSTR_RI_MA 4, { U4_8,J16_16,0,0,0 } /* e.g. brc */
-#define INSTR_RI_B 4, { J16_16,0,0,0,0 } /* e.g. j */
-#define INSTR_RSI_A 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
-#define INSTR_RSE 6, { R_8,D_20,B_16,R_12,0,0 } /* e.g. lmg */
-#define INSTR_RSE_M 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
-#define INSTR_RSE_R 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
-#define INSTR_RIE_A 6, { R_8,J16_16,R_12,0,0,0 } /* e.g. brxhg */
-#define INSTR_RIL_A 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
-#define INSTR_RIL_B 6, { J32_16,0,0,0,0,0 } /* e.g. jg */
-#define INSTR_RIL_MA 6, { R_8,J32_16,0,0,0,0 } /* e.g. brcl */
-
-#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_B { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_I { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_R { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_E { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_D { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_X { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_ED { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_DE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_DX { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RR_XD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_A { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_F { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_O { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
-#define MASK_RRE_R { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_R2 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_E { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_D { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_X { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
-#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
-#define MASK_RRF_M { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRF_RM { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRF_R { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RRF_F { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_A { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_C { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_S { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RS_D { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_B { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_E { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_D { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_ED { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RX_DX { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RXE { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXE_F { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_S { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_S_O { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
-#define MASK_SI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_LL { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_LI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_L { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_LMD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SS_PLO { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_SSE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_U { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_A { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_MA { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RI_B { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RSI_A { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RSE { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RSE_M { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RSE_R { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RIE_A { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RIL_A { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RIL_B { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RIL_M { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
-#define MASK_RIL_MA { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+/* The new format of the INSTR_x_y and MASK_x_y defines is based
+ on the following rules:
+ 1) the middle part of the definition (x in INSTR_x_y) is the official
+ names of the instruction format that you can find in the principals
+ of operation.
+ 2) the last part of the definition (y in INSTR_x_y) gives you an idea
+ which operands the binary represenation of the instruction has.
+ The meanings of the letters in y are:
+ a - access register
+ c - control register
+ d - displacement, 12 bit
+ f - floating pointer register
+ i - signed integer, 4 or 8 bit
+ l - length, 4 or 8 bit
+ p - pc relative
+ r - general purpose register
+ u - unsigned integer, 4 or 8 bit
+ 0 - operand skipped.
+ The order of the letters reflects the layout of the format in
+ storage and not the order of the paramaters of the instructions.
+ The use of the letters is not a 100% match with the PoP but it is
+ quite close.
+
+ For example the instruction "mvo" is defined in the PoP as follows:
+
+ MVO D1(L1,B1),D2(L2,B2) [SS]
+
+ --------------------------------------
+ | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
+ --------------------------------------
+ 0 8 12 16 20 32 36
+
+ The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
+
+#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
+#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
+#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
+#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
+#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
+#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */
+#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
+#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
+#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
+#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
+#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
+#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
+#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
+#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
+#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
+#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
+#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
+#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
+#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
+#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
+#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
+#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
+#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
+#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */
+#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */
+#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */
+#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
+#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
+#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
+#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
+#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
+#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
+#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
+#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
+#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
+#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
+#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
+#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
+#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
+#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
+#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
+#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
+#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
+#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
+#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
+#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
+#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
+#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
+#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
+#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
+#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
+#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
+#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
+#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
+#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
+#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
+#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
+#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
+
+#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
+#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
+#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
+#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
+#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
+#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
const struct s390_opcode s390_opformats[] =
{
{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3 },
- { "ri", OP8(0x00LL), MASK_RI, INSTR_RI, 3 },
- { "ri_a", OP8(0x00LL), MASK_RI_A, INSTR_RI_A, 3 },
- { "ri_b", OP8(0x00LL), MASK_RI_B, INSTR_RI_B, 3 },
- { "ri_ma", OP8(0x00LL), MASK_RI_MA, INSTR_RI_MA, 3 },
- { "ri_u", OP8(0x00LL), MASK_RI_U, INSTR_RI_U, 3 },
- { "rie_a", OP8(0x00LL), MASK_RIE_A, INSTR_RIE_A, 3 },
- { "ril_a", OP8(0x00LL), MASK_RIL_A, INSTR_RIL_A, 3 },
- { "ril_b", OP8(0x00LL), MASK_RIL_B, INSTR_RIL_B, 3 },
- { "ril_ma", OP8(0x00LL), MASK_RIL_MA, INSTR_RIL_MA, 3 },
- { "rr", OP8(0x00LL), MASK_RR, INSTR_RR, 3 },
- { "rr_b", OP8(0x00LL), MASK_RR_B, INSTR_RR_B, 3 },
- { "rr_d", OP8(0x00LL), MASK_RR_D, INSTR_RR_D, 3 },
- { "rr_de", OP8(0x00LL), MASK_RR_DE, INSTR_RR_DE, 3 },
- { "rr_dx", OP8(0x00LL), MASK_RR_DX, INSTR_RR_DX, 3 },
- { "rr_e", OP8(0x00LL), MASK_RR_E, INSTR_RR_E, 3 },
- { "rr_ed", OP8(0x00LL), MASK_RR_ED, INSTR_RR_ED, 3 },
- { "rr_i", OP8(0x00LL), MASK_RR_I, INSTR_RR_I, 3 },
- { "rr_m", OP8(0x00LL), MASK_RR_M, INSTR_RR_M, 3 },
- { "rr_r", OP8(0x00LL), MASK_RR_R, INSTR_RR_R, 3 },
- { "rr_x", OP8(0x00LL), MASK_RR_X, INSTR_RR_X, 3 },
- { "rr_xd", OP8(0x00LL), MASK_RR_XD, INSTR_RR_XD, 3 },
- { "rre", OP8(0x00LL), MASK_RRE, INSTR_RRE, 3 },
- { "rre_a", OP8(0x00LL), MASK_RRE_A, INSTR_RRE_A, 3 },
- { "rre_ar", OP8(0x00LL), MASK_RRE_AR, INSTR_RRE_AR, 3 },
- { "rre_d", OP8(0x00LL), MASK_RRE_D, INSTR_RRE_D, 3 },
- { "rre_e", OP8(0x00LL), MASK_RRE_E, INSTR_RRE_E, 3 },
- { "rre_f", OP8(0x00LL), MASK_RRE_F, INSTR_RRE_F, 3 },
- { "rre_o", OP8(0x00LL), MASK_RRE_O, INSTR_RRE_O, 3 },
- { "rre_r", OP8(0x00LL), MASK_RRE_R, INSTR_RRE_R, 3 },
- { "rre_r2", OP8(0x00LL), MASK_RRE_R2, INSTR_RRE_R2, 3 },
- { "rre_ra", OP8(0x00LL), MASK_RRE_RA, INSTR_RRE_RA, 3 },
- { "rre_x", OP8(0x00LL), MASK_RRE_X, INSTR_RRE_X, 3 },
- { "rrf_f", OP8(0x00LL), MASK_RRF_F, INSTR_RRF_F, 3 },
- { "rrf_m", OP8(0x00LL), MASK_RRF_M, INSTR_RRF_M, 3 },
- { "rrf_r", OP8(0x00LL), MASK_RRF_R, INSTR_RRF_R, 3 },
- { "rrf_rm", OP8(0x00LL), MASK_RRF_RM, INSTR_RRF_RM, 3 },
- { "rs", OP8(0x00LL), MASK_RS, INSTR_RS, 3 },
- { "rs_a", OP8(0x00LL), MASK_RS_A, INSTR_RS_A, 3 },
- { "rs_c", OP8(0x00LL), MASK_RS_C, INSTR_RS_C, 3 },
- { "rs_d", OP8(0x00LL), MASK_RS_D, INSTR_RS_D, 3 },
- { "rs_m", OP8(0x00LL), MASK_RS_M, INSTR_RS_M, 3 },
- { "rs_s", OP8(0x00LL), MASK_RS_S, INSTR_RS_S, 3 },
- { "rse", OP8(0x00LL), MASK_RSE, INSTR_RSE, 3 },
- { "rse_m", OP8(0x00LL), MASK_RSE_M, INSTR_RSE_M, 3 },
- { "rse_r", OP8(0x00LL), MASK_RSE_R, INSTR_RSE_R, 3 },
- { "rsi_a", OP8(0x00LL), MASK_RSI_A, INSTR_RSI_A, 3 },
- { "rx", OP8(0x00LL), MASK_RX, INSTR_RX, 3 },
- { "rx_b", OP8(0x00LL), MASK_RX_B, INSTR_RX_B, 3 },
- { "rx_d", OP8(0x00LL), MASK_RX_D, INSTR_RX_D, 3 },
- { "rx_dx", OP8(0x00LL), MASK_RX_DX, INSTR_RX_DX, 3 },
- { "rx_e", OP8(0x00LL), MASK_RX_E, INSTR_RX_E, 3 },
- { "rx_ed", OP8(0x00LL), MASK_RX_ED, INSTR_RX_ED, 3 },
- { "rx_m", OP8(0x00LL), MASK_RX_M, INSTR_RX_M, 3 },
- { "rxe", OP8(0x00LL), MASK_RXE, INSTR_RXE, 3 },
- { "rxe_f", OP8(0x00LL), MASK_RXE_F, INSTR_RXE_F, 3 },
- { "rxf", OP8(0x00LL), MASK_RXF, INSTR_RXF, 3 },
- { "s", OP8(0x00LL), MASK_S, INSTR_S, 3 },
- { "si", OP8(0x00LL), MASK_SI, INSTR_SI, 3 },
- { "ss_l", OP8(0x00LL), MASK_SS_L, INSTR_SS_L, 3 },
- { "ss_li", OP8(0x00LL), MASK_SS_LI, INSTR_SS_LI, 3 },
- { "ss_ll", OP8(0x00LL), MASK_SS_LL, INSTR_SS_LL, 3 },
- { "ss_lmd", OP8(0x00LL), MASK_SS_LMD, INSTR_SS_LMD, 3 },
- { "ss_plo", OP8(0x00LL), MASK_SS_PLO, INSTR_SS_PLO, 3 },
- { "ss_rr", OP8(0x00LL), MASK_SS_RR, INSTR_SS_RR, 3 },
- { "sse", OP8(0x00LL), MASK_SSE, INSTR_SSE, 3 },
+ { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3 },
+ { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3 },
+ { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3 },
+ { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3 },
+ { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3 },
+ { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3 },
+ { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3 },
+ { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3 },
+ { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3 },
+ { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3 },
+ { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3 },
+ { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3 },
+ { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3 },
+ { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3 },
+ { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3 },
+ { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3 },
};
const int s390_num_opformats =
sizeof (s390_opformats) / sizeof (s390_opformats[0]);
-/* The opcode table.
-
- The format of the opcode table is:
-
- NAME OPCODE MASK OPERANDS
-
- NAME is the name of the instruction.
- OPCODE is the instruction opcode.
- MASK is the opcode mask; this is used to tell the disassembler
- which bits in the actual opcode must match OPCODE.
- OPERANDS is the list of operands.
-
- The disassembler reads the table in order and prints the first
- instruction which matches. */
-
-const struct s390_opcode s390_opcodes[] =
- {
- { "dp", OP8(0xfdLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "mp", OP8(0xfcLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "sp", OP8(0xfbLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "ap", OP8(0xfaLL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "cp", OP8(0xf9LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "zap", OP8(0xf8LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "unpk", OP8(0xf3LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "pack", OP8(0xf2LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "mvo", OP8(0xf1LL), MASK_SS_LL, INSTR_SS_LL, 3},
- { "srp", OP8(0xf0LL), MASK_SS_LI, INSTR_SS_LI, 3},
- { "lmd", OP8(0xefLL), MASK_SS_LMD, INSTR_SS_LMD, 2},
- { "plo", OP8(0xeeLL), MASK_SS_PLO, INSTR_SS_PLO, 3},
- { "msdb", OP48(0xed000000001fLL), MASK_RXF, INSTR_RXF, 3},
- { "madb", OP48(0xed000000001eLL), MASK_RXF, INSTR_RXF, 3},
- { "ddb", OP48(0xed000000001dLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mdb", OP48(0xed000000001cLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "sdb", OP48(0xed000000001bLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "adb", OP48(0xed000000001aLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "cdb", OP48(0xed0000000019LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "kdb", OP48(0xed0000000018LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "meeb", OP48(0xed0000000017LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "sqdb", OP48(0xed0000000015LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "sqeb", OP48(0xed0000000014LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "tcxb", OP48(0xed0000000012LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "tcdb", OP48(0xed0000000011LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "tceb", OP48(0xed0000000010LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mseb", OP48(0xed000000000fLL), MASK_RXF, INSTR_RXF, 3},
- { "maeb", OP48(0xed000000000eLL), MASK_RXF, INSTR_RXF, 3},
- { "deb", OP48(0xed000000000dLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mdeb", OP48(0xed000000000cLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "seb", OP48(0xed000000000bLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "aeb", OP48(0xed000000000aLL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "ceb", OP48(0xed0000000009LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "keb", OP48(0xed0000000008LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "mxdb", OP48(0xed0000000007LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "lxeb", OP48(0xed0000000006LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "lxdb", OP48(0xed0000000005LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "ldeb", OP48(0xed0000000004LL), MASK_RXE_F, INSTR_RXE_F, 3},
- { "brxlg", OP48(0xec0000000045LL), MASK_RIE_A, INSTR_RIE_A, 2},
- { "brxhg", OP48(0xec0000000044LL), MASK_RIE_A, INSTR_RIE_A, 2},
- { "lmh", OP48(0xeb0000000096LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "icmh", OP48(0xeb0000000080LL), MASK_RSE_M, INSTR_RSE_M, 2},
- { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "csg", OP48(0xeb0000000030LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_M, INSTR_RSE_M, 2},
- { "stmh", OP48(0xeb0000000026LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "stctg", OP48(0xeb0000000025LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "stmg", OP48(0xeb0000000024LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "clmh", OP48(0xeb0000000020LL), MASK_RSE_M, INSTR_RSE_M, 2},
- { "rll", OP48(0xeb000000001dLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "rllg", OP48(0xeb000000001cLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "tracg", OP48(0xeb000000000fLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "sllg", OP48(0xeb000000000dLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "srlg", OP48(0xeb000000000cLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "slag", OP48(0xeb000000000bLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "srag", OP48(0xeb000000000aLL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "lmg", OP48(0xeb0000000004LL), MASK_RSE_R, INSTR_RSE_R, 2},
- { "unpka", OP8(0xeaLL), MASK_SS_L, INSTR_SS_L, 2},
- { "pka", OP8(0xe9LL), MASK_SS_L, INSTR_SS_L, 2},
- { "mvcin", OP8(0xe8LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvcdk", OP16(0xe50fLL), MASK_SSE, INSTR_SSE, 3},
- { "mvcsk", OP16(0xe50eLL), MASK_SSE, INSTR_SSE, 3},
- { "tprot", OP16(0xe501LL), MASK_SSE, INSTR_SSE, 3},
- { "strag", OP48(0xe50000000002LL), MASK_SSE, INSTR_SSE, 2},
- { "lasp", OP16(0xe500LL), MASK_SSE, INSTR_SSE, 3},
- { "slb", OP48(0xe30000000099LL), MASK_RXE, INSTR_RXE, 2},
- { "alc", OP48(0xe30000000098LL), MASK_RXE, INSTR_RXE, 2},
- { "dl", OP48(0xe30000000097LL), MASK_RXE, INSTR_RXE, 2},
- { "ml", OP48(0xe30000000096LL), MASK_RXE, INSTR_RXE, 2},
- { "llgh", OP48(0xe30000000091LL), MASK_RXE, INSTR_RXE, 2},
- { "llgc", OP48(0xe30000000090LL), MASK_RXE, INSTR_RXE, 2},
- { "lpq", OP48(0xe3000000008fLL), MASK_RXE, INSTR_RXE, 2},
- { "stpq", OP48(0xe3000000008eLL), MASK_RXE, INSTR_RXE, 2},
- { "slbg", OP48(0xe30000000089LL), MASK_RXE, INSTR_RXE, 2},
- { "alcg", OP48(0xe30000000088LL), MASK_RXE, INSTR_RXE, 2},
- { "dlg", OP48(0xe30000000087LL), MASK_RXE, INSTR_RXE, 2},
- { "mlg", OP48(0xe30000000086LL), MASK_RXE, INSTR_RXE, 2},
- { "xg", OP48(0xe30000000082LL), MASK_RXE, INSTR_RXE, 2},
- { "og", OP48(0xe30000000081LL), MASK_RXE, INSTR_RXE, 2},
- { "ng", OP48(0xe30000000080LL), MASK_RXE, INSTR_RXE, 2},
- { "bctg", OP48(0xe30000000046LL), MASK_RXE, INSTR_RXE, 2},
- { "strvh", OP48(0xe3000000003fLL), MASK_RXE, INSTR_RXE, 2},
- { "strv", OP48(0xe3000000003eLL), MASK_RXE, INSTR_RXE, 2},
- { "clgf", OP48(0xe30000000031LL), MASK_RXE, INSTR_RXE, 2},
- { "cgf", OP48(0xe30000000030LL), MASK_RXE, INSTR_RXE, 2},
- { "strvg", OP48(0xe3000000002fLL), MASK_RXE, INSTR_RXE, 2},
- { "cvdg", OP48(0xe3000000002eLL), MASK_RXE, INSTR_RXE, 2},
- { "stg", OP48(0xe30000000024LL), MASK_RXE, INSTR_RXE, 2},
- { "clg", OP48(0xe30000000021LL), MASK_RXE, INSTR_RXE, 2},
- { "cg", OP48(0xe30000000020LL), MASK_RXE, INSTR_RXE, 2},
- { "lrvh", OP48(0xe3000000001fLL), MASK_RXE, INSTR_RXE, 2},
- { "lrv", OP48(0xe3000000001eLL), MASK_RXE, INSTR_RXE, 2},
- { "dsgf", OP48(0xe3000000001dLL), MASK_RXE, INSTR_RXE, 2},
- { "msgf", OP48(0xe3000000001cLL), MASK_RXE, INSTR_RXE, 2},
- { "slgf", OP48(0xe3000000001bLL), MASK_RXE, INSTR_RXE, 2},
- { "algf", OP48(0xe3000000001aLL), MASK_RXE, INSTR_RXE, 2},
- { "sgf", OP48(0xe30000000019LL), MASK_RXE, INSTR_RXE, 2},
- { "agf", OP48(0xe30000000018LL), MASK_RXE, INSTR_RXE, 2},
- { "llgt", OP48(0xe30000000017LL), MASK_RXE, INSTR_RXE, 2},
- { "llgf", OP48(0xe30000000016LL), MASK_RXE, INSTR_RXE, 2},
- { "lgh", OP48(0xe30000000015LL), MASK_RXE, INSTR_RXE, 2},
- { "lgf", OP48(0xe30000000014LL), MASK_RXE, INSTR_RXE, 2},
- { "lrvg", OP48(0xe3000000000fLL), MASK_RXE, INSTR_RXE, 2},
- { "cvbg", OP48(0xe3000000000eLL), MASK_RXE, INSTR_RXE, 2},
- { "dsg", OP48(0xe3000000000dLL), MASK_RXE, INSTR_RXE, 2},
- { "msg", OP48(0xe3000000000cLL), MASK_RXE, INSTR_RXE, 2},
- { "slg", OP48(0xe3000000000bLL), MASK_RXE, INSTR_RXE, 2},
- { "alg", OP48(0xe3000000000aLL), MASK_RXE, INSTR_RXE, 2},
- { "sg", OP48(0xe30000000009LL), MASK_RXE, INSTR_RXE, 2},
- { "ag", OP48(0xe30000000008LL), MASK_RXE, INSTR_RXE, 2},
- { "lg", OP48(0xe30000000004LL), MASK_RXE, INSTR_RXE, 2},
- { "lrag", OP48(0xe30000000003LL), MASK_RXE, INSTR_RXE, 2},
- { "unpku", OP8(0xe2LL), MASK_SS_L, INSTR_SS_L, 2},
- { "pku", OP8(0xe1LL), MASK_SS_L, INSTR_SS_L, 2},
- { "edmk", OP8(0xdfLL), MASK_SS_L, INSTR_SS_L, 3},
- { "ed", OP8(0xdeLL), MASK_SS_L, INSTR_SS_L, 3},
- { "trt", OP8(0xddLL), MASK_SS_L, INSTR_SS_L, 3},
- { "tr", OP8(0xdcLL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvcs", OP8(0xdbLL), MASK_SS_RR, INSTR_SS_RR, 3},
- { "mvcp", OP8(0xdaLL), MASK_SS_RR, INSTR_SS_RR, 3},
- { "mvck", OP8(0xd9LL), MASK_SS_RR, INSTR_SS_RR, 3},
- { "xc", OP8(0xd7LL), MASK_SS_L, INSTR_SS_L, 3},
- { "oc", OP8(0xd6LL), MASK_SS_L, INSTR_SS_L, 3},
- { "clc", OP8(0xd5LL), MASK_SS_L, INSTR_SS_L, 3},
- { "nc", OP8(0xd4LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvz", OP8(0xd3LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvc", OP8(0xd2LL), MASK_SS_L, INSTR_SS_L, 3},
- { "mvn", OP8(0xd1LL), MASK_SS_L, INSTR_SS_L, 3},
- { "jg", OP16(0xc0f4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgno", OP16(0xc0e4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnh", OP16(0xc0d4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnp", OP16(0xc0d4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgle", OP16(0xc0c4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnl", OP16(0xc0b4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnm", OP16(0xc0b4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jghe", OP16(0xc0a4LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnlh", OP16(0xc094LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jge", OP16(0xc084LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgz", OP16(0xc084LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgne", OP16(0xc074LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnz", OP16(0xc074LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jglh", OP16(0xc064LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnhe", OP16(0xc054LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgl", OP16(0xc044LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgm", OP16(0xc044LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgnle", OP16(0xc034LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgh", OP16(0xc024LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgp", OP16(0xc024LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "jgo", OP16(0xc014LL), MASK_RIL_B, INSTR_RIL_B, 2},
- { "brasl", OP16(0xc005LL), MASK_RIL_A, INSTR_RIL_A, 2},
- { "brcl", OP16(0xc004LL), MASK_RIL_MA, INSTR_RIL_MA, 2},
- { "larl", OP16(0xc000LL), MASK_RIL_A, INSTR_RIL_A, 2},
- { "icm", OP8(0xbfLL), MASK_RS_M, INSTR_RS_M, 3},
- { "stcm", OP8(0xbeLL), MASK_RS_M, INSTR_RS_M, 3},
- { "clm", OP8(0xbdLL), MASK_RS_M, INSTR_RS_M, 3},
- { "cds", OP8(0xbbLL), MASK_RS, INSTR_RS, 3},
- { "cs", OP8(0xbaLL), MASK_RS, INSTR_RS, 3},
- { "esea", OP16(0xb99dLL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "slbr", OP16(0xb999LL), MASK_RRE, INSTR_RRE, 2},
- { "alcr", OP16(0xb998LL), MASK_RRE, INSTR_RRE, 2},
- { "dlr", OP16(0xb997LL), MASK_RRE, INSTR_RRE, 2},
- { "mlr", OP16(0xb996LL), MASK_RRE, INSTR_RRE, 2},
- { "epsw", OP16(0xb98dLL), MASK_RRE, INSTR_RRE, 2},
- { "slbgr", OP16(0xb989LL), MASK_RRE, INSTR_RRE, 2},
- { "alcgr", OP16(0xb988LL), MASK_RRE, INSTR_RRE, 2},
- { "dlgr", OP16(0xb987LL), MASK_RRE, INSTR_RRE, 2},
- { "mlgr", OP16(0xb986LL), MASK_RRE, INSTR_RRE, 2},
- { "troo", OP16(0xb993LL), MASK_RRE, INSTR_RRE, 2},
- { "trot", OP16(0xb992LL), MASK_RRE, INSTR_RRE, 2},
- { "trto", OP16(0xb991LL), MASK_RRE, INSTR_RRE, 2},
- { "trtt", OP16(0xb990LL), MASK_RRE, INSTR_RRE, 2},
- { "xgr", OP16(0xb982LL), MASK_RRE, INSTR_RRE, 2},
- { "ogr", OP16(0xb981LL), MASK_RRE, INSTR_RRE, 2},
- { "ngr", OP16(0xb980LL), MASK_RRE, INSTR_RRE, 2},
- { "bctgr", OP16(0xb946LL), MASK_RRE, INSTR_RRE, 2},
- { "clgfr", OP16(0xb931LL), MASK_RRE, INSTR_RRE, 2},
- { "cgfr", OP16(0xb930LL), MASK_RRE, INSTR_RRE, 2},
- { "sturg", OP16(0xb925LL), MASK_RRE, INSTR_RRE, 2},
- { "clgr", OP16(0xb921LL), MASK_RRE, INSTR_RRE, 2},
- { "cgr", OP16(0xb920LL), MASK_RRE, INSTR_RRE, 2},
- { "lrvr", OP16(0xb91fLL), MASK_RRE, INSTR_RRE, 2},
- { "dsgfr", OP16(0xb91dLL), MASK_RRE, INSTR_RRE, 2},
- { "msgfr", OP16(0xb91cLL), MASK_RRE, INSTR_RRE, 2},
- { "slgfr", OP16(0xb91bLL), MASK_RRE, INSTR_RRE, 2},
- { "algfr", OP16(0xb91aLL), MASK_RRE, INSTR_RRE, 2},
- { "sgfr", OP16(0xb919LL), MASK_RRE, INSTR_RRE, 2},
- { "agfr", OP16(0xb918LL), MASK_RRE, INSTR_RRE, 2},
- { "llgtr", OP16(0xb917LL), MASK_RRE, INSTR_RRE, 2},
- { "llgfr", OP16(0xb916LL), MASK_RRE, INSTR_RRE, 2},
- { "lgfr", OP16(0xb914LL), MASK_RRE, INSTR_RRE, 2},
- { "lcgfr", OP16(0xb913LL), MASK_RRE, INSTR_RRE, 2},
- { "ltgfr", OP16(0xb912LL), MASK_RRE, INSTR_RRE, 2},
- { "lngfr", OP16(0xb911LL), MASK_RRE, INSTR_RRE, 2},
- { "lpgfr", OP16(0xb910LL), MASK_RRE, INSTR_RRE, 2},
- { "lrvgr", OP16(0xb90fLL), MASK_RRE, INSTR_RRE, 2},
- { "eregg", OP16(0xb90eLL), MASK_RRE, INSTR_RRE, 2},
- { "dsgr", OP16(0xb90dLL), MASK_RRE, INSTR_RRE, 2},
- { "msgr", OP16(0xb90cLL), MASK_RRE, INSTR_RRE, 2},
- { "slgr", OP16(0xb90bLL), MASK_RRE, INSTR_RRE, 2},
- { "algr", OP16(0xb90aLL), MASK_RRE, INSTR_RRE, 2},
- { "sgr", OP16(0xb909LL), MASK_RRE, INSTR_RRE, 2},
- { "agr", OP16(0xb908LL), MASK_RRE, INSTR_RRE, 2},
- { "lurag", OP16(0xb905LL), MASK_RRE, INSTR_RRE, 2},
- { "lgr", OP16(0xb904LL), MASK_RRE, INSTR_RRE, 2},
- { "lcgr", OP16(0xb903LL), MASK_RRE, INSTR_RRE, 2},
- { "ltgr", OP16(0xb902LL), MASK_RRE, INSTR_RRE, 2},
- { "lngr", OP16(0xb901LL), MASK_RRE, INSTR_RRE, 2},
- { "lpgr", OP16(0xb900LL), MASK_RRE, INSTR_RRE, 2},
- { "lctl", OP8(0xb7LL), MASK_RS_C, INSTR_RS_C, 3},
- { "stctl", OP8(0xb6LL), MASK_RS_C, INSTR_RS_C, 3},
- { "cgxr", OP16(0xb3caLL), MASK_RRF_F, INSTR_RRF_F, 2},
- { "cgdr", OP16(0xb3c9LL), MASK_RRF_F, INSTR_RRF_F, 2},
- { "cger", OP16(0xb3c8LL), MASK_RRF_F, INSTR_RRF_F, 2},
- { "cxgr", OP16(0xb3c6LL), MASK_RRE, INSTR_RRE, 2},
- { "cdgr", OP16(0xb3c5LL), MASK_RRE, INSTR_RRE, 2},
- { "cegr", OP16(0xb3c4LL), MASK_RRE, INSTR_RRE, 2},
- { "cgxbr", OP16(0xb3aaLL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "cgdbr", OP16(0xb3a9LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "cgebr", OP16(0xb3a8LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "cxgbr", OP16(0xb3a6LL), MASK_RRE, INSTR_RRE, 2},
- { "cdgbr", OP16(0xb3a5LL), MASK_RRE, INSTR_RRE, 2},
- { "cegbr", OP16(0xb3a4LL), MASK_RRE, INSTR_RRE, 2},
- { "cfxbr", OP16(0xb39aLL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "cfdbr", OP16(0xb399LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "cfebr", OP16(0xb398LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "cxfbr", OP16(0xb396LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cdfbr", OP16(0xb395LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cefbr", OP16(0xb394LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "efpc", OP16(0xb38cLL), MASK_RRE, INSTR_RRE, 3},
- { "sfpc", OP16(0xb384LL), MASK_RRE, INSTR_RRE, 3},
- { "lzxr", OP16(0xb376LL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "lzdr", OP16(0xb375LL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "lzer", OP16(0xb374LL), MASK_RRE_R, INSTR_RRE_R, 2},
- { "fidbr", OP16(0xb35fLL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "didbr", OP16(0xb35bLL), MASK_RRF_RM, INSTR_RRF_RM, 3},
- { "thdr", OP16(0xb359LL), MASK_RRE, INSTR_RRE, 2},
- { "thder", OP16(0xb358LL), MASK_RRE, INSTR_RRE, 2},
- { "fiebr", OP16(0xb357LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "diebr", OP16(0xb353LL), MASK_RRF_RM, INSTR_RRF_RM, 3},
- { "tbdr", OP16(0xb351LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "tbedr", OP16(0xb350LL), MASK_RRF_M, INSTR_RRF_M, 2},
- { "dxbr", OP16(0xb34dLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mxbr", OP16(0xb34cLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sxbr", OP16(0xb34bLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "axbr", OP16(0xb34aLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cxbr", OP16(0xb349LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "kxbr", OP16(0xb348LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "fixbr", OP16(0xb347LL), MASK_RRF_M, INSTR_RRF_M, 3},
- { "lexbr", OP16(0xb346LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ldxbr", OP16(0xb345LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ledbr", OP16(0xb344LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lcxbr", OP16(0xb343LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ltxbr", OP16(0xb342LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lnxbr", OP16(0xb341LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lpxbr", OP16(0xb340LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "msdbr", OP16(0xb31fLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "madbr", OP16(0xb31eLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "ddbr", OP16(0xb31dLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mdbr", OP16(0xb31cLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sdbr", OP16(0xb31bLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "adbr", OP16(0xb31aLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cdbr", OP16(0xb319LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "kdbr", OP16(0xb318LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "meebr", OP16(0xb317LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sqxbr", OP16(0xb316LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sqdbr", OP16(0xb315LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sqebr", OP16(0xb314LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lcdbr", OP16(0xb313LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ltdbr", OP16(0xb312LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lndbr", OP16(0xb311LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lpdbr", OP16(0xb310LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "msebr", OP16(0xb30fLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "maebr", OP16(0xb30eLL), MASK_RRF_R, INSTR_RRF_R, 3},
- { "debr", OP16(0xb30dLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mdebr", OP16(0xb30cLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "sebr", OP16(0xb30bLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "aebr", OP16(0xb30aLL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "cebr", OP16(0xb309LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "kebr", OP16(0xb308LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "mxdbr", OP16(0xb307LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lxebr", OP16(0xb306LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lxdbr", OP16(0xb305LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ldebr", OP16(0xb304LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lcebr", OP16(0xb303LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "ltebr", OP16(0xb302LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lnebr", OP16(0xb301LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "lpebr", OP16(0xb300LL), MASK_RRE_F, INSTR_RRE_F, 3},
- { "trap4", OP16(0xb2ffLL), MASK_S, INSTR_S, 3},
- { "lpswe", OP16(0xb2b2LL), MASK_S, INSTR_S, 2},
- { "stfl", OP16(0xb2b1LL), MASK_S, INSTR_S, 2},
- { "cutfu", OP16(0xb2a7LL), MASK_RRE, INSTR_RRE, 3},
- { "cuutf", OP16(0xb2a6LL), MASK_RRE, INSTR_RRE, 3},
- { "tre", OP16(0xb2a5LL), MASK_RRE, INSTR_RRE, 2},
- { "lfpc", OP16(0xb29dLL), MASK_S, INSTR_S, 3},
- { "stfpc", OP16(0xb29cLL), MASK_S, INSTR_S, 3},
- { "srnm", OP16(0xb299LL), MASK_S, INSTR_S, 3},
- { "stsi", OP16(0xb27dLL), MASK_S, INSTR_S, 3},
- { "sacf", OP16(0xb279LL), MASK_S, INSTR_S, 3},
- { "stcke", OP16(0xb278LL), MASK_S, INSTR_S, 2},
- { "rp", OP16(0xb277LL), MASK_S, INSTR_S, 3},
- { "siga", OP16(0xb274LL), MASK_S, INSTR_S, 3},
- { "cmpsc", OP16(0xb263LL), MASK_RRE, INSTR_RRE, 3},
- { "srst", OP16(0xb25eLL), MASK_RRE, INSTR_RRE, 3},
- { "clst", OP16(0xb25dLL), MASK_RRE, INSTR_RRE, 3},
- { "bsa", OP16(0xb25aLL), MASK_RRE, INSTR_RRE, 3},
- { "bsg", OP16(0xb258LL), MASK_RRE, INSTR_RRE, 3},
- { "cuse", OP16(0xb257LL), MASK_RRE, INSTR_RRE, 3},
- { "mvst", OP16(0xb255LL), MASK_RRE, INSTR_RRE, 3},
- { "mvpg", OP16(0xb254LL), MASK_RRE, INSTR_RRE, 3},
- { "msr", OP16(0xb252LL), MASK_RRE, INSTR_RRE, 3},
- { "csp", OP16(0xb250LL), MASK_RRE, INSTR_RRE, 3},
- { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3},
- { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3},
- { "cpya", OP16(0xb24dLL), MASK_RRE_A, INSTR_RRE_A, 3},
- { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3},
- { "lura", OP16(0xb24bLL), MASK_RRE, INSTR_RRE, 3},
- { "esta", OP16(0xb24aLL), MASK_RRE, INSTR_RRE, 3},
- { "ereg", OP16(0xb249LL), MASK_RRE, INSTR_RRE, 3},
- { "palb", OP16(0xb248LL), MASK_RRE_O, INSTR_RRE_O, 3},
- { "msta", OP16(0xb247LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "stura", OP16(0xb246LL), MASK_RRE, INSTR_RRE, 3},
- { "sqer", OP16(0xb245LL), MASK_RRE_E, INSTR_RRE_E, 3},
- { "sqdr", OP16(0xb244LL), MASK_RRE_D, INSTR_RRE_D, 3},
- { "cksm", OP16(0xb241LL), MASK_RRE, INSTR_RRE, 3},
- { "bakr", OP16(0xb240LL), MASK_RRE, INSTR_RRE, 3},
- { "schm", OP16(0xb23cLL), MASK_S_O, INSTR_S_O, 3},
- { "rchp", OP16(0xb23bLL), MASK_S_O, INSTR_S_O, 3},
- { "stcps", OP16(0xb23aLL), MASK_S, INSTR_S, 3},
- { "stcrw", OP16(0xb239LL), MASK_S, INSTR_S, 3},
- { "rsch", OP16(0xb238LL), MASK_S_O, INSTR_S_O, 3},
- { "sal", OP16(0xb237LL), MASK_S_O, INSTR_S_O, 3},
- { "tpi", OP16(0xb236LL), MASK_S, INSTR_S, 3},
- { "tsch", OP16(0xb235LL), MASK_S, INSTR_S, 3},
- { "stsch", OP16(0xb234LL), MASK_S, INSTR_S, 3},
- { "ssch", OP16(0xb233LL), MASK_S, INSTR_S, 3},
- { "msch", OP16(0xb232LL), MASK_S, INSTR_S, 3},
- { "hsch", OP16(0xb231LL), MASK_S_O, INSTR_S_O, 3},
- { "csch", OP16(0xb230LL), MASK_S_O, INSTR_S_O, 3},
- { "dxr", OP16(0xb22dLL), MASK_RRE_X, INSTR_RRE_X, 3},
- { "tb", OP16(0xb22cLL), MASK_RRE_R2, INSTR_RRE_R2, 3},
- { "sske", OP16(0xb22bLL), MASK_RRE, INSTR_RRE, 3},
- { "rrbe", OP16(0xb22aLL), MASK_RRE, INSTR_RRE, 3},
- { "iske", OP16(0xb229LL), MASK_RRE, INSTR_RRE, 3},
- { "pt", OP16(0xb228LL), MASK_RRE, INSTR_RRE, 3},
- { "esar", OP16(0xb227LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "epar", OP16(0xb226LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "ssar", OP16(0xb225LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "iac", OP16(0xb224LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "ivsk", OP16(0xb223LL), MASK_RRE, INSTR_RRE, 3},
- { "ipm", OP16(0xb222LL), MASK_RRE_R, INSTR_RRE_R, 3},
- { "ipte", OP16(0xb221LL), MASK_RRE, INSTR_RRE, 3},
- { "cfc", OP16(0xb21aLL), MASK_S, INSTR_S, 3},
- { "sac", OP16(0xb219LL), MASK_S, INSTR_S, 3},
- { "pc", OP16(0xb218LL), MASK_S, INSTR_S, 3},
- { "sie", OP16(0xb214LL), MASK_S, INSTR_S, 3},
- { "stap", OP16(0xb212LL), MASK_S, INSTR_S, 3},
- { "stpx", OP16(0xb211LL), MASK_S, INSTR_S, 3},
- { "spx", OP16(0xb210LL), MASK_S, INSTR_S, 3},
- { "ptlb", OP16(0xb20dLL), MASK_S_O, INSTR_S_O, 3},
- { "ipk", OP16(0xb20bLL), MASK_S_O, INSTR_S_O, 3},
- { "spka", OP16(0xb20aLL), MASK_S, INSTR_S, 3},
- { "stpt", OP16(0xb209LL), MASK_S, INSTR_S, 3},
- { "spt", OP16(0xb208LL), MASK_S, INSTR_S, 3},
- { "stckc", OP16(0xb207LL), MASK_S, INSTR_S, 3},
- { "sckc", OP16(0xb206LL), MASK_S, INSTR_S, 3},
- { "stck", OP16(0xb205LL), MASK_S, INSTR_S, 3},
- { "sck", OP16(0xb204LL), MASK_S, INSTR_S, 3},
- { "stidp", OP16(0xb202LL), MASK_S, INSTR_S, 3},
- { "lra", OP8(0xb1LL), MASK_RX, INSTR_RX, 3},
- { "mc", OP8(0xafLL), MASK_SI, INSTR_SI, 3},
- { "sigp", OP8(0xaeLL), MASK_RS, INSTR_RS, 3},
- { "stosm", OP8(0xadLL), MASK_SI, INSTR_SI, 3},
- { "stnsm", OP8(0xacLL), MASK_SI, INSTR_SI, 3},
- { "clcle", OP8(0xa9LL), MASK_RS, INSTR_RS, 3},
- { "mvcle", OP8(0xa8LL), MASK_RS, INSTR_RS, 3},
- { "j", OP16(0xa7f4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jno", OP16(0xa7e4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnh", OP16(0xa7d4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnp", OP16(0xa7d4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jle", OP16(0xa7c4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnl", OP16(0xa7b4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnm", OP16(0xa7b4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jhe", OP16(0xa7a4LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnlh", OP16(0xa794LL), MASK_RI_B, INSTR_RI_B, 3},
- { "je", OP16(0xa784LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jz", OP16(0xa784LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jne", OP16(0xa774LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnz", OP16(0xa774LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jlh", OP16(0xa764LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnhe", OP16(0xa754LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jl", OP16(0xa744LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jm", OP16(0xa744LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jnle", OP16(0xa734LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jh", OP16(0xa724LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jp", OP16(0xa724LL), MASK_RI_B, INSTR_RI_B, 3},
- { "jo", OP16(0xa714LL), MASK_RI_B, INSTR_RI_B, 3},
- { "cghi", OP16(0xa70fLL), MASK_RI, INSTR_RI, 2},
- { "chi", OP16(0xa70eLL), MASK_RI, INSTR_RI, 3},
- { "mghi", OP16(0xa70dLL), MASK_RI, INSTR_RI, 2},
- { "mhi", OP16(0xa70cLL), MASK_RI, INSTR_RI, 3},
- { "aghi", OP16(0xa70bLL), MASK_RI, INSTR_RI, 2},
- { "ahi", OP16(0xa70aLL), MASK_RI, INSTR_RI, 3},
- { "lghi", OP16(0xa709LL), MASK_RI, INSTR_RI, 2},
- { "lhi", OP16(0xa708LL), MASK_RI, INSTR_RI, 3},
- { "brctg", OP16(0xa707LL), MASK_RI_A, INSTR_RI_A, 2},
- { "brct", OP16(0xa706LL), MASK_RI_A, INSTR_RI_A, 3},
- { "bras", OP16(0xa705LL), MASK_RI_A, INSTR_RI_A, 3},
- { "brc", OP16(0xa704LL), MASK_RI_MA, INSTR_RI_MA, 3},
- { "tmhl", OP16(0xa703LL), MASK_RI_U, INSTR_RI_U, 2},
- { "tmhh", OP16(0xa702LL), MASK_RI_U, INSTR_RI_U, 2},
- { "tml", OP16(0xa701LL), MASK_RI_U, INSTR_RI_U, 3},
- { "tmll", OP16(0xa701LL), MASK_RI_U, INSTR_RI_U, 2},
- { "tmh", OP16(0xa700LL), MASK_RI_U, INSTR_RI_U, 3},
- { "tmlh", OP16(0xa700LL), MASK_RI_U, INSTR_RI_U, 2},
- { "llill", OP16(0xa50fLL), MASK_RI_U, INSTR_RI_U, 2},
- { "llilh", OP16(0xa50eLL), MASK_RI_U, INSTR_RI_U, 2},
- { "llihl", OP16(0xa50dLL), MASK_RI_U, INSTR_RI_U, 2},
- { "llihh", OP16(0xa50cLL), MASK_RI_U, INSTR_RI_U, 2},
- { "oill", OP16(0xa50bLL), MASK_RI_U, INSTR_RI_U, 2},
- { "oilh", OP16(0xa50aLL), MASK_RI_U, INSTR_RI_U, 2},
- { "oihl", OP16(0xa509LL), MASK_RI_U, INSTR_RI_U, 2},
- { "oihh", OP16(0xa508LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nill", OP16(0xa507LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nilh", OP16(0xa506LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nihl", OP16(0xa505LL), MASK_RI_U, INSTR_RI_U, 2},
- { "nihh", OP16(0xa504LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iill", OP16(0xa503LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iilh", OP16(0xa502LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iihl", OP16(0xa501LL), MASK_RI_U, INSTR_RI_U, 2},
- { "iihh", OP16(0xa500LL), MASK_RI_U, INSTR_RI_U, 2},
- { "stam", OP8(0x9bLL), MASK_RS_A, INSTR_RS_A, 3},
- { "lam", OP8(0x9aLL), MASK_RS_A, INSTR_RS_A, 3},
- { "trace", OP8(0x99LL), MASK_RS, INSTR_RS, 3},
- { "lm", OP8(0x98LL), MASK_RS, INSTR_RS, 3},
- { "xi", OP8(0x97LL), MASK_SI, INSTR_SI, 3},
- { "oi", OP8(0x96LL), MASK_SI, INSTR_SI, 3},
- { "cli", OP8(0x95LL), MASK_SI, INSTR_SI, 3},
- { "ni", OP8(0x94LL), MASK_SI, INSTR_SI, 3},
- { "ts", OP8(0x93LL), MASK_S, INSTR_S, 3},
- { "mvi", OP8(0x92LL), MASK_SI, INSTR_SI, 3},
- { "tm", OP8(0x91LL), MASK_SI, INSTR_SI, 3},
- { "stm", OP8(0x90LL), MASK_RS, INSTR_RS, 3},
- { "slda", OP8(0x8fLL), MASK_RS_D, INSTR_RS_D, 3},
- { "srda", OP8(0x8eLL), MASK_RS_D, INSTR_RS_D, 3},
- { "sldl", OP8(0x8dLL), MASK_RS_D, INSTR_RS_D, 3},
- { "srdl", OP8(0x8cLL), MASK_RS_D, INSTR_RS_D, 3},
- { "sla", OP8(0x8bLL), MASK_RS_S, INSTR_RS_S, 3},
- { "sra", OP8(0x8aLL), MASK_RS_S, INSTR_RS_S, 3},
- { "sll", OP8(0x89LL), MASK_RS_S, INSTR_RS_S, 3},
- { "srl", OP8(0x88LL), MASK_RS_S, INSTR_RS_S, 3},
- { "bxle", OP8(0x87LL), MASK_RS, INSTR_RS, 3},
- { "bxh", OP8(0x86LL), MASK_RS, INSTR_RS, 3},
- { "brxle", OP8(0x85LL), MASK_RSI_A, INSTR_RSI_A, 3},
- { "brxh", OP8(0x84LL), MASK_RSI_A, INSTR_RSI_A, 3},
- { "diag", OP8(0x83LL), MASK_RS, INSTR_RS, 3},
- { "lpsw", OP8(0x82LL), MASK_S, INSTR_S, 3},
- { "ssm", OP8(0x80LL), MASK_S, INSTR_S, 3},
- { "su", OP8(0x7fLL), MASK_RX_E, INSTR_RX_E, 3},
- { "au", OP8(0x7eLL), MASK_RX_E, INSTR_RX_E, 3},
- { "de", OP8(0x7dLL), MASK_RX_E, INSTR_RX_E, 3},
- { "me", OP8(0x7cLL), MASK_RX_ED, INSTR_RX_ED, 3},
- { "se", OP8(0x7bLL), MASK_RX_E, INSTR_RX_E, 3},
- { "ae", OP8(0x7aLL), MASK_RX_E, INSTR_RX_E, 3},
- { "ce", OP8(0x79LL), MASK_RX_E, INSTR_RX_E, 3},
- { "le", OP8(0x78LL), MASK_RX_E, INSTR_RX_E, 3},
- { "ms", OP8(0x71LL), MASK_RX, INSTR_RX, 3},
- { "ste", OP8(0x70LL), MASK_RX_E, INSTR_RX_E, 3},
- { "sw", OP8(0x6fLL), MASK_RX_D, INSTR_RX_D, 3},
- { "aw", OP8(0x6eLL), MASK_RX_D, INSTR_RX_D, 3},
- { "dd", OP8(0x6dLL), MASK_RX_D, INSTR_RX_D, 3},
- { "md", OP8(0x6cLL), MASK_RX_D, INSTR_RX_D, 3},
- { "sd", OP8(0x6bLL), MASK_RX_D, INSTR_RX_D, 3},
- { "ad", OP8(0x6aLL), MASK_RX_D, INSTR_RX_D, 3},
- { "cd", OP8(0x69LL), MASK_RX_D, INSTR_RX_D, 3},
- { "ld", OP8(0x68LL), MASK_RX_D, INSTR_RX_D, 3},
- { "mxd", OP8(0x67LL), MASK_RX_DX, INSTR_RX_DX, 3},
- { "std", OP8(0x60LL), MASK_RX_D, INSTR_RX_D, 3},
- { "sl", OP8(0x5fLL), MASK_RX, INSTR_RX, 3},
- { "al", OP8(0x5eLL), MASK_RX, INSTR_RX, 3},
- { "d", OP8(0x5dLL), MASK_RX, INSTR_RX, 3},
- { "m", OP8(0x5cLL), MASK_RX, INSTR_RX, 3},
- { "s", OP8(0x5bLL), MASK_RX, INSTR_RX, 3},
- { "a", OP8(0x5aLL), MASK_RX, INSTR_RX, 3},
- { "c", OP8(0x59LL), MASK_RX, INSTR_RX, 3},
- { "l", OP8(0x58LL), MASK_RX, INSTR_RX, 3},
- { "x", OP8(0x57LL), MASK_RX, INSTR_RX, 3},
- { "o", OP8(0x56LL), MASK_RX, INSTR_RX, 3},
- { "cl", OP8(0x55LL), MASK_RX, INSTR_RX, 3},
- { "n", OP8(0x54LL), MASK_RX, INSTR_RX, 3},
- { "lae", OP8(0x51LL), MASK_RX, INSTR_RX, 3},
- { "st", OP8(0x50LL), MASK_RX, INSTR_RX, 3},
- { "cvb", OP8(0x4fLL), MASK_RX, INSTR_RX, 3},
- { "cvd", OP8(0x4eLL), MASK_RX, INSTR_RX, 3},
- { "bas", OP8(0x4dLL), MASK_RX, INSTR_RX, 3},
- { "mh", OP8(0x4cLL), MASK_RX, INSTR_RX, 3},
- { "sh", OP8(0x4bLL), MASK_RX, INSTR_RX, 3},
- { "ah", OP8(0x4aLL), MASK_RX, INSTR_RX, 3},
- { "ch", OP8(0x49LL), MASK_RX, INSTR_RX, 3},
- { "lh", OP8(0x48LL), MASK_RX, INSTR_RX, 3},
- { "b", OP16(0x47f0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bno", OP16(0x47e0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnh", OP16(0x47d0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnp", OP16(0x47d0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "ble", OP16(0x47c0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnl", OP16(0x47b0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnm", OP16(0x47b0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bhe", OP16(0x47a0LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnlh", OP16(0x4790LL), MASK_RX_B, INSTR_RX_B, 3},
- { "be", OP16(0x4780LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bz", OP16(0x4780LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bne", OP16(0x4770LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnz", OP16(0x4770LL), MASK_RX_B, INSTR_RX_B, 3},
- { "blh", OP16(0x4760LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnhe", OP16(0x4750LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bl", OP16(0x4740LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bm", OP16(0x4740LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bnle", OP16(0x4730LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bh", OP16(0x4720LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bp", OP16(0x4720LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bo", OP16(0x4710LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bc", OP8(0x47LL), MASK_RX_M, INSTR_RX_M, 3},
- { "nop", OP16(0x4700LL), MASK_RX_B, INSTR_RX_B, 3},
- { "bct", OP8(0x46LL), MASK_RX, INSTR_RX, 3},
- { "bal", OP8(0x45LL), MASK_RX, INSTR_RX, 3},
- { "ex", OP8(0x44LL), MASK_RX, INSTR_RX, 3},
- { "ic", OP8(0x43LL), MASK_RX, INSTR_RX, 3},
- { "stc", OP8(0x42LL), MASK_RX, INSTR_RX, 3},
- { "la", OP8(0x41LL), MASK_RX, INSTR_RX, 3},
- { "sth", OP8(0x40LL), MASK_RX, INSTR_RX, 3},
- { "sur", OP8(0x3fLL), MASK_RR_E, INSTR_RR_E, 3},
- { "aur", OP8(0x3eLL), MASK_RR_E, INSTR_RR_E, 3},
- { "der", OP8(0x3dLL), MASK_RR_E, INSTR_RR_E, 3},
- { "mer", OP8(0x3cLL), MASK_RR_ED, INSTR_RR_ED, 3},
- { "ser", OP8(0x3bLL), MASK_RR_E, INSTR_RR_E, 3},
- { "aer", OP8(0x3aLL), MASK_RR_E, INSTR_RR_E, 3},
- { "cer", OP8(0x39LL), MASK_RR_E, INSTR_RR_E, 3},
- { "ler", OP8(0x38LL), MASK_RR_E, INSTR_RR_E, 3},
- { "sxr", OP8(0x37LL), MASK_RR_X, INSTR_RR_X, 3},
- { "axr", OP8(0x36LL), MASK_RR, INSTR_RR, 3},
- { "lrer", OP8(0x35LL), MASK_RR_DE, INSTR_RR_DE, 3},
- { "her", OP8(0x34LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lcer", OP8(0x33LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lter", OP8(0x32LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lner", OP8(0x31LL), MASK_RR_E, INSTR_RR_E, 3},
- { "lper", OP8(0x30LL), MASK_RR_E, INSTR_RR_E, 3},
- { "swr", OP8(0x2fLL), MASK_RR_D, INSTR_RR_D, 3},
- { "awr", OP8(0x2eLL), MASK_RR_D, INSTR_RR_D, 3},
- { "ddr", OP8(0x2dLL), MASK_RR_D, INSTR_RR_D, 3},
- { "mdr", OP8(0x2cLL), MASK_RR_D, INSTR_RR_D, 3},
- { "sdr", OP8(0x2bLL), MASK_RR_D, INSTR_RR_D, 3},
- { "adr", OP8(0x2aLL), MASK_RR_D, INSTR_RR_D, 3},
- { "cdr", OP8(0x29LL), MASK_RR_D, INSTR_RR_D, 3},
- { "ldr", OP8(0x28LL), MASK_RR_D, INSTR_RR_D, 3},
- { "mxdr", OP8(0x27LL), MASK_RR_DX, INSTR_RR_DX, 3},
- { "mxr", OP8(0x26LL), MASK_RR_X, INSTR_RR_X, 3},
- { "lrdr", OP8(0x25LL), MASK_RR_XD, INSTR_RR_XD, 3},
- { "hdr", OP8(0x24LL), MASK_RR_D, INSTR_RR_D, 3},
- { "lcdr", OP8(0x23LL), MASK_RR_D, INSTR_RR_D, 3},
- { "ltdr", OP8(0x22LL), MASK_RR_D, INSTR_RR_D, 3},
- { "lndr", OP8(0x21LL), MASK_RR_D, INSTR_RR_D, 3},
- { "lpdr", OP8(0x20LL), MASK_RR_D, INSTR_RR_D, 3},
- { "slr", OP8(0x1fLL), MASK_RR, INSTR_RR, 3},
- { "alr", OP8(0x1eLL), MASK_RR, INSTR_RR, 3},
- { "dr", OP8(0x1dLL), MASK_RR, INSTR_RR, 3},
- { "mr", OP8(0x1cLL), MASK_RR, INSTR_RR, 3},
- { "sr", OP8(0x1bLL), MASK_RR, INSTR_RR, 3},
- { "ar", OP8(0x1aLL), MASK_RR, INSTR_RR, 3},
- { "cr", OP8(0x19LL), MASK_RR, INSTR_RR, 3},
- { "lr", OP8(0x18LL), MASK_RR, INSTR_RR, 3},
- { "xr", OP8(0x17LL), MASK_RR, INSTR_RR, 3},
- { "or", OP8(0x16LL), MASK_RR, INSTR_RR, 3},
- { "clr", OP8(0x15LL), MASK_RR, INSTR_RR, 3},
- { "nr", OP8(0x14LL), MASK_RR, INSTR_RR, 3},
- { "lcr", OP8(0x13LL), MASK_RR, INSTR_RR, 3},
- { "ltr", OP8(0x12LL), MASK_RR, INSTR_RR, 3},
- { "lnr", OP8(0x11LL), MASK_RR, INSTR_RR, 3},
- { "lpr", OP8(0x10LL), MASK_RR, INSTR_RR, 3},
- { "clcl", OP8(0x0fLL), MASK_RR, INSTR_RR, 3},
- { "mvcl", OP8(0x0eLL), MASK_RR, INSTR_RR, 3},
- { "basr", OP8(0x0dLL), MASK_RR, INSTR_RR, 3},
- { "bassm", OP8(0x0cLL), MASK_RR, INSTR_RR, 3},
- { "bsm", OP8(0x0bLL), MASK_RR, INSTR_RR, 3},
- { "svc", OP8(0x0aLL), MASK_RR_I, INSTR_RR_I, 3},
- { "br", OP16(0x07f0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnor", OP16(0x07e0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnhr", OP16(0x07d0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnpr", OP16(0x07d0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bler", OP16(0x07c0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnlr", OP16(0x07b0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnmr", OP16(0x07b0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bher", OP16(0x07a0LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnlhr", OP16(0x0790LL), MASK_RR_B, INSTR_RR_B, 3},
- { "ber", OP16(0x0780LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bzr", OP16(0x0780LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bner", OP16(0x0770LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnzr", OP16(0x0770LL), MASK_RR_B, INSTR_RR_B, 3},
- { "blhr", OP16(0x0760LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnher", OP16(0x0750LL), MASK_RR_B, INSTR_RR_B, 3},
- { "blr", OP16(0x0740LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bmr", OP16(0x0740LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bnler", OP16(0x0730LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bhr", OP16(0x0720LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bpr", OP16(0x0720LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bor", OP16(0x0710LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bcr", OP8(0x07LL), MASK_RR_M, INSTR_RR_M, 3},
- { "nopr", OP16(0x0700LL), MASK_RR_B, INSTR_RR_B, 3},
- { "bctr", OP8(0x06LL), MASK_RR, INSTR_RR, 3},
- { "balr", OP8(0x05LL), MASK_RR, INSTR_RR, 3},
- { "spm", OP8(0x04LL), MASK_RR_R, INSTR_RR_R, 3},
- { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3},
- { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2},
- { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 2},
- { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 2},
- { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 2},
- { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3},
- { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3},
- { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3}
-};
-
-const int s390_num_opcodes =
- sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);
+#include "s390-opc.tab"
diff -urN src/opcodes/s390-opc.txt src-s390/opcodes/s390-opc.txt
--- src/opcodes/s390-opc.txt Fri Sep 14 16:00:09 2001
+++ src-s390/opcodes/s390-opc.txt Fri Sep 14 18:23:52 2001
@@ -1,626 +1,626 @@
# S/390 opcodes list. Use s390-mkopc to convert it into the opcode table.
# Copyright 2000, 2001 Free Software Foundation, Inc.
# Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
-5a a RX "add" esa
-6a ad RX_D "add normalized (long)" esa
-2a adr RR_D "add normalized (long)" esa
-7a ae RX_E "add normalized (short)" esa
-3a aer RR_E "add normalized (short)" esa
-4a ah RX "add halfword" esa
-5e al RX "add logical" esa
-1e alr RR "add logical" esa
-fa ap SS_LL "add decimal" esa
-1a ar RR "add" esa
-7e au RX_E "add unnormalized (short)" esa
-3e aur RR_E "add unnormalized (short)" esa
-6e aw RX_D "add unnormalized (long)" esa
-2e awr RR_D "add unnormalized (long)" esa
-36 axr RR "add normalized" esa
-b240 bakr RRE "branch and stack" esa
-45 bal RX "branch and link" esa
-05 balr RR "branch and link" esa
-4d bas RX "branch and save" esa
-0d basr RR "branch and save" esa
-0c bassm RR "branch and save and set mode" esa
-47 bc RX_M "branch on condition" esa
-07 bcr RR_M "branch on condition" esa
-46 bct RX "branch on count" esa
-06 bctr RR "branch on count" esa
-b258 bsg RRE "branch in subspace group" esa
-0b bsm RR "branch and set mode" esa
-86 bxh RS "branch on index high" esa
-87 bxle RS "branch on index low or equal" esa
-59 c RX "compare" esa
-69 cd RX_D "compare (long)" esa
-29 cdr RR_D "compare (long)" esa
-bb cds RS "compare double and swap" esa
-79 ce RX_E "compare (short)" esa
-39 cer RR_E "compare (short)" esa
-b21a cfc S "compare and form codeword" esa
-49 ch RX "compare halfword" esa
-55 cl RX "compare logical" esa
-d5 clc SS_L "compare logical" esa
-0f clcl RR "compare logical long" esa
-95 cli SI "compare logical" esa
-bd clm RS_M "compare logical characters under mask" esa
-15 clr RR "compare logical" esa
-b25d clst RRE "compare logical string" esa
-b263 cmpsc RRE "compression call" esa
-f9 cp SS_LL "compare decimal" esa
-b24d cpya RRE_A "copy access" esa
-19 cr RR "compare" esa
-ba cs RS "compare and swap" esa
-b230 csch S_O "clear subchannel" esa
-b257 cuse RRE "compare until substring equal" esa
-b250 csp RRE "compare and swap and purge" esa
-4f cvb RX "convert to binary" esa
-4e cvd RX "convert to decimal" esa
-5d d RX "divide" esa
-6d dd RX_D "divide (long)" esa
-2d ddr RR_D "divide (long)" esa
-7d de RX_E "divide (short)" esa
-3d der RR_E "divide (short)" esa
-83 diag RS "diagnose" esa
-fd dp SS_LL "divide decimal" esa
-1d dr RR "divide" esa
-b22d dxr RRE_X "divide (ext.)" esa
+5a a RX_RRRD "add" esa
+6a ad RX_FRRD "add normalized (long)" esa
+2a adr RR_FF "add normalized (long)" esa
+7a ae RX_FRRD "add normalized (short)" esa
+3a aer RR_FF "add normalized (short)" esa
+4a ah RX_RRRD "add halfword" esa
+5e al RX_RRRD "add logical" esa
+1e alr RR_RR "add logical" esa
+fa ap SS_LLRDRD "add decimal" esa
+1a ar RR_RR "add" esa
+7e au RX_FRRD "add unnormalized (short)" esa
+3e aur RR_FF "add unnormalized (short)" esa
+6e aw RX_FRRD "add unnormalized (long)" esa
+2e awr RR_FF "add unnormalized (long)" esa
+36 axr RR_FF "add normalized" esa
+b240 bakr RRE_RR "branch and stack" esa
+45 bal RX_RRRD "branch and link" esa
+05 balr RR_RR "branch and link" esa
+4d bas RX_RRRD "branch and save" esa
+0d basr RR_RR "branch and save" esa
+0c bassm RR_RR "branch and save and set mode" esa
+47 bc RX_URRD "branch on condition" esa
+07 bcr RR_UR "branch on condition" esa
+46 bct RX_RRRD "branch on count" esa
+06 bctr RR_RR "branch on count" esa
+b258 bsg RRE_RR "branch in subspace group" esa
+0b bsm RR_RR "branch and set mode" esa
+86 bxh RS_RRRD "branch on index high" esa
+87 bxle RS_RRRD "branch on index low or equal" esa
+59 c RX_RRRD "compare" esa
+69 cd RX_FRRD "compare (long)" esa
+29 cdr RR_FF "compare (long)" esa
+bb cds RS_RRRD "compare double and swap" esa
+79 ce RX_FRRD "compare (short)" esa
+39 cer RR_FF "compare (short)" esa
+b21a cfc S_RD "compare and form codeword" esa
+49 ch RX_RRRD "compare halfword" esa
+55 cl RX_RRRD "compare logical" esa
+d5 clc SS_L0RDRD "compare logical" esa
+0f clcl RR_RR "compare logical long" esa
+95 cli SI_URD "compare logical" esa
+bd clm RS_RURD "compare logical characters under mask" esa
+15 clr RR_RR "compare logical" esa
+b25d clst RRE_RR "compare logical string" esa
+b263 cmpsc RRE_RR "compression call" esa
+f9 cp SS_LLRDRD "compare decimal" esa
+b24d cpya RRE_AA "copy access" esa
+19 cr RR_RR "compare" esa
+ba cs RS_RRRD "compare and swap" esa
+b230 csch S_00 "clear subchannel" esa
+b257 cuse RRE_RR "compare until substring equal" esa
+b250 csp RRE_RR "compare and swap and purge" esa
+4f cvb RX_RRRD "convert to binary" esa
+4e cvd RX_RRRD "convert to decimal" esa
+5d d RX_RRRD "divide" esa
+6d dd RX_FRRD "divide (long)" esa
+2d ddr RR_FF "divide (long)" esa
+7d de RX_FRRD "divide (short)" esa
+3d der RR_FF "divide (short)" esa
+83 diag RS_RRRD "diagnose" esa
+fd dp SS_LLRDRD "divide decimal" esa
+1d dr RR_RR "divide" esa
+b22d dxr RRE_F0 "divide (ext.)" esa
b24f ear RRE_RA "extract access" esa
-de ed SS_L "edit" esa
-df edmk SS_L "edit and mark" esa
-b226 epar RRE_R "extract primary ASN" esa
-b249 ereg RRE "extract stacked registers" esa
-b227 esar RRE_R "extract secondary ASN" esa
-b24a esta RRE "extract stacked state" esa
-44 ex RX "execute" esa
-24 hdr RR_D "halve (long)" esa
-34 her RR_E "halve (short)" esa
-b231 hsch S_O "halt subchannel" esa
-b224 iac RRE_R "insert address space control" esa
-43 ic RX "insert character" esa
-bf icm RS_M "insert characters under mask" esa
-b20b ipk S_O "insert PSW key" esa
-b222 ipm RRE_R "insert program mask" esa
-b221 ipte RRE "invalidate page table entry" esa
-b229 iske RRE "insert storage key extended" esa
-b223 ivsk RRE "insert virtual storage key" esa
-58 l RX "load" esa
-41 la RX "load address" esa
-51 lae RX "load address extended" esa
-9a lam RS_A "load access multiple" esa
-e500 lasp SSE "load address space parameters" esa
-23 lcdr RR_D "load complement (long)" esa
-33 lcer RR_E "load complement (short)" esa
-13 lcr RR "load complement" esa
-b7 lctl RS_C "load control" esa
-68 ld RX_D "load (long)" esa
-28 ldr RR_D "load (long)" esa
-78 le RX_E "load (short)" esa
-38 ler RR_E "load (short)" esa
-48 lh RX "load halfword" esa
-98 lm RS "load multiple" esa
-21 lndr RR_D "load negative (long)" esa
-31 lner RR_E "load negative (short)" esa
-11 lnr RR "load negative" esa
-20 lpdr RR_D "load positive (long)" esa
-30 lper RR_E "load positive (short)" esa
-10 lpr RR "load positive" esa
-82 lpsw S "load PSW" esa
-18 lr RR "load" esa
-b1 lra RX "load real address" esa
-25 lrdr RR_XD "load rounded (ext. to long)" esa
-35 lrer RR_DE "load rounded (long to short)" esa
-22 ltdr RR_D "load and test (long)" esa
-32 lter RR_E "load and test (short)" esa
-12 ltr RR "load and test" esa
-b24b lura RRE "load using real address" esa
-5c m RX "multiply" esa
-af mc SI "monitor call" esa
-6c md RX_D "multiply (long)" esa
-2c mdr RR_D "multiply (long)" esa
-7c me RX_ED "multiply (short to long)" esa
-3c mer RR_ED "multiply (short to long)" esa
-4c mh RX "multiply halfword" esa
-fc mp SS_LL "multiply decimal" esa
-1c mr RR "multiply" esa
-b232 msch S "modify subchannel" esa
-b247 msta RRE_R "modify stacked state" esa
-d2 mvc SS_L "move" esa
-e50f mvcdk SSE "move with destination key" esa
-e8 mvcin SS_L "move inverse" esa
-d9 mvck SS_RR "move with key" esa
-0e mvcl RR "move long" esa
-da mvcp SS_RR "move to primary" esa
-db mvcs SS_RR "move to secondary" esa
-e50e mvcsk SSE "move with source key" esa
-92 mvi SI "move" esa
-d1 mvn SS_L "move numerics" esa
-f1 mvo SS_LL "move with offset" esa
-b254 mvpg RRE "move page" esa
-b255 mvst RRE "move string" esa
-d3 mvz SS_L "move zones" esa
-67 mxd RX_DX "multiply (long to ext.)" esa
-27 mxdr RR_DX "multiply (long to ext.)" esa
-26 mxr RR_X "multiply (ext.)" esa
-54 n RX "AND" esa
-d4 nc SS_L "AND" esa
-94 ni SI "AND" esa
-14 nr RR "AND" esa
-56 o RX "OR" esa
-d6 oc SS_L "OR" esa
-96 oi SI "OR" esa
-16 or RR "OR" esa
-f2 pack SS_LL "pack" esa
-b248 palb RRE_O "purge ALB" esa
-b218 pc S "program call" esa
+de ed SS_L0RDRD "edit" esa
+df edmk SS_L0RDRD "edit and mark" esa
+b226 epar RRE_R0 "extract primary ASN" esa
+b249 ereg RRE_RR "extract stacked registers" esa
+b227 esar RRE_R0 "extract secondary ASN" esa
+b24a esta RRE_RR "extract stacked state" esa
+44 ex RX_RRRD "execute" esa
+24 hdr RR_FF "halve (long)" esa
+34 her RR_FF "halve (short)" esa
+b231 hsch S_00 "halt subchannel" esa
+b224 iac RRE_R0 "insert address space control" esa
+43 ic RX_RRRD "insert character" esa
+bf icm RS_RURD "insert characters under mask" esa
+b20b ipk S_00 "insert PSW key" esa
+b222 ipm RRE_R0 "insert program mask" esa
+b221 ipte RRE_RR "invalidate page table entry" esa
+b229 iske RRE_RR "insert storage key extended" esa
+b223 ivsk RRE_RR "insert virtual storage key" esa
+58 l RX_RRRD "load" esa
+41 la RX_RRRD "load address" esa
+51 lae RX_RRRD "load address extended" esa
+9a lam RS_AARD "load access multiple" esa
+e500 lasp SSE_RDRD "load address space parameters" esa
+23 lcdr RR_FF "load complement (long)" esa
+33 lcer RR_FF "load complement (short)" esa
+13 lcr RR_RR "load complement" esa
+b7 lctl RS_CCRD "load control" esa
+68 ld RX_FRRD "load (long)" esa
+28 ldr RR_FF "load (long)" esa
+78 le RX_FRRD "load (short)" esa
+38 ler RR_FF "load (short)" esa
+48 lh RX_RRRD "load halfword" esa
+98 lm RS_RRRD "load multiple" esa
+21 lndr RR_FF "load negative (long)" esa
+31 lner RR_FF "load negative (short)" esa
+11 lnr RR_RR "load negative" esa
+20 lpdr RR_FF "load positive (long)" esa
+30 lper RR_FF "load positive (short)" esa
+10 lpr RR_RR "load positive" esa
+82 lpsw S_RD "load PSW" esa
+18 lr RR_RR "load" esa
+b1 lra RX_RRRD "load real address" esa
+25 lrdr RR_FF "load rounded (ext. to long)" esa
+35 lrer RR_FF "load rounded (long to short)" esa
+22 ltdr RR_FF "load and test (long)" esa
+32 lter RR_FF "load and test (short)" esa
+12 ltr RR_RR "load and test" esa
+b24b lura RRE_RR "load using real address" esa
+5c m RX_RRRD "multiply" esa
+af mc SI_URD "monitor call" esa
+6c md RX_FRRD "multiply (long)" esa
+2c mdr RR_FF "multiply (long)" esa
+7c me RX_FRRD "multiply (short to long)" esa
+3c mer RR_FF "multiply (short to long)" esa
+4c mh RX_RRRD "multiply halfword" esa
+fc mp SS_LLRDRD "multiply decimal" esa
+1c mr RR_RR "multiply" esa
+b232 msch S_RD "modify subchannel" esa
+b247 msta RRE_R0 "modify stacked state" esa
+d2 mvc SS_L0RDRD "move" esa
+e50f mvcdk SSE_RDRD "move with destination key" esa
+e8 mvcin SS_L0RDRD "move inverse" esa
+d9 mvck SS_RRRDRD "move with key" esa
+0e mvcl RR_RR "move long" esa
+da mvcp SS_RRRDRD "move to primary" esa
+db mvcs SS_RRRDRD "move to secondary" esa
+e50e mvcsk SSE_RDRD "move with source key" esa
+92 mvi SI_URD "move" esa
+d1 mvn SS_L0RDRD "move numerics" esa
+f1 mvo SS_LLRDRD "move with offset" esa
+b254 mvpg RRE_RR "move page" esa
+b255 mvst RRE_RR "move string" esa
+d3 mvz SS_L0RDRD "move zones" esa
+67 mxd RX_FRRD "multiply (long to ext.)" esa
+27 mxdr RR_FF "multiply (long to ext.)" esa
+26 mxr RR_FF "multiply (ext.)" esa
+54 n RX_RRRD "AND" esa
+d4 nc SS_L0RDRD "AND" esa
+94 ni SI_URD "AND" esa
+14 nr RR_RR "AND" esa
+56 o RX_RRRD "OR" esa
+d6 oc SS_L0RDRD "OR" esa
+96 oi SI_URD "OR" esa
+16 or RR_RR "OR" esa
+f2 pack SS_LLRDRD "pack" esa
+b248 palb RRE_00 "purge ALB" esa
+b218 pc S_RD "program call" esa
0101 pr E "program return" esa
-b228 pt RRE "program transfer" esa
-b20d ptlb S_O "purge TLB" esa
-b23b rchp S_O "reset channel path" esa
-b22a rrbe RRE "reset reference bit extended" esa
-b238 rsch S_O "resume subchannel" esa
-5b s RX "subtract" esa
-b219 sac S "set address space control" esa
-b279 sacf S "set address space control fast" esa
-b237 sal S_O "set address limit" esa
+b228 pt RRE_RR "program transfer" esa
+b20d ptlb S_00 "purge TLB" esa
+b23b rchp S_00 "reset channel path" esa
+b22a rrbe RRE_RR "reset reference bit extended" esa
+b238 rsch S_00 "resume subchannel" esa
+5b s RX_RRRD "subtract" esa
+b219 sac S_RD "set address space control" esa
+b279 sacf S_RD "set address space control fast" esa
+b237 sal S_00 "set address limit" esa
b24e sar RRE_AR "set access" esa
-b23c schm S_O "set channel monitor" esa
-b204 sck S "set clock" esa
-b206 sckc S "set clock comparator" esa
-6b sd RX_D "subtract normalized (long)" esa
-2b sdr RR_D "subtract normalized (long)" esa
-7b se RX_E "subtract normalized (short)" esa
-3b ser RR_E "subtract normalized (short)" esa
-4b sh RX "subtract halfword" esa
-b214 sie S "start interpretive execution" esa
-ae sigp RS "signal processor" esa
-5f sl RX "subtract logical" esa
-8b sla RS_S "shift left single" esa
-8f slda RS_D "shift left double (long)" esa
-8d sldl RS_D "shift left double logical (long)" esa
-89 sll RS_S "shift left single logical" esa
-1f slr RR "subtract logical" esa
-fb sp SS_LL "subtract decimal" esa
-b20a spka S "set PSW key from address" esa
-04 spm RR_R "set program mask" esa
-b208 spt S "set CPU timer" esa
-b210 spx S "set prefix" esa
-b244 sqdr RRE_D "square root (long)" esa
-b245 sqer RRE_E "square root (short)" esa
-1b sr RR "subtract" esa
-8a sra RS_S "shift right single" esa
-8e srda RS_D "shift right double (long)" esa
-8c srdl RS_D "shift right double logical (long)" esa
-88 srl RS_S "shift right single logical" esa
-f0 srp SS_LI "shift and round decimal" esa
-b25e srst RRE "search string" esa
-b225 ssar RRE_R "set secondary ASN" esa
-b233 ssch S "start subchannel" esa
-b22b sske RRE "set storage key extended" esa
-80 ssm S "set system mask" esa
-50 st RX "store" esa
-9b stam RS_A "store access multiple" esa
-b212 stap S "store CPU address" esa
-42 stc RX "store character" esa
-b205 stck S "store clock" esa
-b207 stckc S "store clock comparator" esa
-be stcm RS_M "store characters under mask" esa
-b23a stcps S "store channel path status" esa
-b239 stcrw S "store channel report word" esa
-b6 stctl RS_C "store control" esa
-60 std RX_D "store (long)" esa
-70 ste RX_E "store (short)" esa
-40 sth RX "store halfword" esa
-b202 stidp S "store CPU id" esa
-90 stm RS "store multiple" esa
-ac stnsm SI "store then AND system mask" esa
-ad stosm SI "store then OR system mask" esa
-b209 stpt S "store CPU timer" esa
-b211 stpx S "store prefix" esa
-b234 stsch S "store subchannel" esa
-b246 stura RRE "store using real address" esa
-7f su RX_E "subtract unnormalized (short)" esa
-3f sur RR_E "subtract unnormalized (short)" esa
-0a svc RR_I "supervisor call" esa
-6f sw RX_D "subtract unnormalized (long)" esa
-2f swr RR_D "subtract unnormalized (long)" esa
-37 sxr RR_X "subtract normalized (ext.)" esa
+b23c schm S_00 "set channel monitor" esa
+b204 sck S_RD "set clock" esa
+b206 sckc S_RD "set clock comparator" esa
+6b sd RX_FRRD "subtract normalized (long)" esa
+2b sdr RR_FF "subtract normalized (long)" esa
+7b se RX_FRRD "subtract normalized (short)" esa
+3b ser RR_FF "subtract normalized (short)" esa
+4b sh RX_RRRD "subtract halfword" esa
+b214 sie S_RD "start interpretive execution" esa
+ae sigp RS_RRRD "signal processor" esa
+5f sl RX_RRRD "subtract logical" esa
+8b sla RS_R0RD "shift left single" esa
+8f slda RS_R0RD "shift left double (long)" esa
+8d sldl RS_R0RD "shift left double logical (long)" esa
+89 sll RS_R0RD "shift left single logical" esa
+1f slr RR_RR "subtract logical" esa
+fb sp SS_LLRDRD "subtract decimal" esa
+b20a spka S_RD "set PSW key from address" esa
+04 spm RR_R0 "set program mask" esa
+b208 spt S_RD "set CPU timer" esa
+b210 spx S_RD "set prefix" esa
+b244 sqdr RRE_F0 "square root (long)" esa
+b245 sqer RRE_F0 "square root (short)" esa
+1b sr RR_RR "subtract" esa
+8a sra RS_R0RD "shift right single" esa
+8e srda RS_R0RD "shift right double (long)" esa
+8c srdl RS_R0RD "shift right double logical (long)" esa
+88 srl RS_R0RD "shift right single logical" esa
+f0 srp SS_LIRDRD "shift and round decimal" esa
+b25e srst RRE_RR "search string" esa
+b225 ssar RRE_R0 "set secondary ASN" esa
+b233 ssch S_RD "start subchannel" esa
+b22b sske RRE_RR "set storage key extended" esa
+80 ssm S_RD "set system mask" esa
+50 st RX_RRRD "store" esa
+9b stam RS_AARD "store access multiple" esa
+b212 stap S_RD "store CPU address" esa
+42 stc RX_RRRD "store character" esa
+b205 stck S_RD "store clock" esa
+b207 stckc S_RD "store clock comparator" esa
+be stcm RS_RURD "store characters under mask" esa
+b23a stcps S_RD "store channel path status" esa
+b239 stcrw S_RD "store channel report word" esa
+b6 stctl RS_CCRD "store control" esa
+60 std RX_FRRD "store (long)" esa
+70 ste RX_FRRD "store (short)" esa
+40 sth RX_RRRD "store halfword" esa
+b202 stidp S_RD "store CPU id" esa
+90 stm RS_RRRD "store multiple" esa
+ac stnsm SI_URD "store then AND system mask" esa
+ad stosm SI_URD "store then OR system mask" esa
+b209 stpt S_RD "store CPU timer" esa
+b211 stpx S_RD "store prefix" esa
+b234 stsch S_RD "store subchannel" esa
+b246 stura RRE_RR "store using real address" esa
+7f su RX_FRRD "subtract unnormalized (short)" esa
+3f sur RR_FF "subtract unnormalized (short)" esa
+0a svc RR_U0 "supervisor call" esa
+6f sw RX_FRRD "subtract unnormalized (long)" esa
+2f swr RR_FF "subtract unnormalized (long)" esa
+37 sxr RR_FF "subtract normalized (ext.)" esa
b24c tar RRE_AR "test access" esa
-b22c tb RRE_R2 "test block" esa
-91 tm SI "test under mask" esa
-b236 tpi S "test pending interruption" esa
-e501 tprot SSE "test protection" esa
-dc tr SS_L "translate" esa
-99 trace RS "trace" esa
-dd trt SS_L "translate and test" esa
-93 ts S "test and set" esa
-b235 tsch S "test subchannel" esa
-f3 unpk SS_LL "unpack" esa
+b22c tb RRE_0R "test block" esa
+91 tm SI_URD "test under mask" esa
+b236 tpi S_RD "test pending interruption" esa
+e501 tprot SSE_RDRD "test protection" esa
+dc tr SS_L0RDRD "translate" esa
+99 trace RS_RRRD "trace" esa
+dd trt SS_L0RDRD "translate and test" esa
+93 ts S_RD "test and set" esa
+b235 tsch S_RD "test subchannel" esa
+f3 unpk SS_LLRDRD "unpack" esa
0102 upt E "update tree" esa
-57 x RX "exclusive OR" esa
-d7 xc SS_L "exclusive OR" esa
-97 xi SI "exclusive OR" esa
-17 xr RR "exclusive OR" esa
-f8 zap SS_LL "zero and add" esa
-a70a ahi RI "add halfword immediate" esa
-84 brxh RSI_A "branch relative on index high" esa
-85 brxle RSI_A "branch relative on index low or equal" esa
-a705 bras RI_A "branch relative and save" esa
-a704 brc RI_MA "branch relative on condition" esa
-a706 brct RI_A "branch relative on count" esa
-b241 cksm RRE "checksum" esa
-a70e chi RI "compare halfword immediate" esa
-a9 clcle RS "compare logical long extended" esa
-a708 lhi RI "load halfword immediate" esa
-a8 mvcle RS "move long extended" esa
-a70c mhi RI "multiply halfword immediate" esa
-b252 msr RRE "multiply single" esa
-71 ms RX "multiply single" esa
-a700 tmh RI_U "test under mask high" esa
-a701 tml RI_U "test under mask low" esa
-0700 nopr RR_B "no operation" esa
-0710 bor RR_B "branch on overflow / if ones" esa
-0720 bhr RR_B "branch on high" esa
-0720 bpr RR_B "branch on plus" esa
-0730 bnler RR_B "branch on not low or equal" esa
-0740 blr RR_B "branch on low" esa
-0740 bmr RR_B "branch on minus / if mixed" esa
-0750 bnher RR_B "branch on not high or equal" esa
-0760 blhr RR_B "branch on low or high" esa
-0770 bner RR_B "branch on not equal" esa
-0770 bnzr RR_B "branch on not zero / if not zeros" esa
-0780 ber RR_B "branch on equal" esa
-0780 bzr RR_B "branch on zero / if zeros" esa
-0790 bnlhr RR_B "branch on not low or high" esa
-07a0 bher RR_B "branch on high or equal" esa
-07b0 bnlr RR_B "branch on not low" esa
-07b0 bnmr RR_B "branch on not minus / if not mixed" esa
-07c0 bler RR_B "brach on low or equal" esa
-07d0 bnhr RR_B "branch on not high" esa
-07d0 bnpr RR_B "branch on not plus" esa
-07e0 bnor RR_B "branch on not overflow / if not ones" esa
-07f0 br RR_B "unconditional branch" esa
-4700 nop RX_B "no operation" esa
-4710 bo RX_B "branch on overflow / if ones" esa
-4720 bh RX_B "branch on high" esa
-4720 bp RX_B "branch on plus" esa
-4730 bnle RX_B "branch on not low or equal" esa
-4740 bl RX_B "branch on low" esa
-4740 bm RX_B "branch on minus / if mixed" esa
-4750 bnhe RX_B "branch on not high or equal" esa
-4760 blh RX_B "branch on low or high" esa
-4770 bne RX_B "branch on not equal" esa
-4770 bnz RX_B "branch on not zero / if not zeros" esa
-4780 be RX_B "branch on equal" esa
-4780 bz RX_B "branch on zero / if zeros" esa
-4790 bnlh RX_B "branch on not low or high" esa
-47a0 bhe RX_B "branch on high or equal" esa
-47b0 bnl RX_B "branch on not low" esa
-47b0 bnm RX_B "branch on not minus / if not mixed" esa
-47c0 ble RX_B "branch on low or equal" esa
-47d0 bnh RX_B "branch on not high" esa
-47d0 bnp RX_B "branch on not plus" esa
-47e0 bno RX_B "branch on not overflow / if not ones" esa
-47f0 b RX_B "unconditional branch" esa
-a714 jo RI_B "jump on overflow / if ones" esa
-a724 jh RI_B "jump on A high" esa
-a724 jp RI_B "jump on plus" esa
-a734 jnle RI_B "jump on not low or equal" esa
-a744 jl RI_B "jump on A low" esa
-a744 jm RI_B "jump on minus / if mixed" esa
-a754 jnhe RI_B "jump on not high or equal" esa
-a764 jlh RI_B "jump on low or high" esa
-a774 jne RI_B "jump on A not equal B" esa
-a774 jnz RI_B "jump on not zero / if not zeros" esa
-a784 je RI_B "jump on A equal B" esa
-a784 jz RI_B "jump on zero / if zeros" esa
-a794 jnlh RI_B "jump on not low or high" esa
-a7a4 jhe RI_B "jump on high or equal" esa
-a7b4 jnl RI_B "jump on A not low" esa
-a7b4 jnm RI_B "jump on not minus / if not mixed" esa
-a7c4 jle RI_B "jump on low or equal" esa
-a7d4 jnh RI_B "jump on A not high" esa
-a7d4 jnp RI_B "jump on not plus" esa
-a7e4 jno RI_B "jump on not overflow / if not ones" esa
-a7f4 j RI_B "jump" esa
-b34a axbr RRE_F "add extended bfp" esa
-b31a adbr RRE_F "add long bfp" esa
-ed000000001a adb RXE_F "add long bfp" esa
-b30a aebr RRE_F "add short bfp" esa
-ed000000000a aeb RXE_F "add short bfp" esa
-b349 cxbr RRE_F "compare extended bfp" esa
-b319 cdbr RRE_F "compare long bfp" esa
-ed0000000019 cdb RXE_F "compare long bfp" esa
-b309 cebr RRE_F "compare short bfp" esa
-ed0000000009 ceb RXE_F "compare short bfp" esa
-b348 kxbr RRE_F "compare and signal extended bfp" esa
-b318 kdbr RRE_F "compare and signal long bfp" esa
-ed0000000018 kdb RXE_F "compare and signal long bfp" esa
-b308 kebr RRE_F "compare and signal short bfp" esa
-ed0000000008 keb RXE_F "compare and signal short bfp" esa
-b396 cxfbr RRE_F "convert from fixed 32 to extended bfp" esa
-b395 cdfbr RRE_F "convert from fixed 32 to long bfp" esa
-b394 cefbr RRE_F "convert from fixed 32 to short bfp" esa
-b39a cfxbr RRF_M "convert to fixed extended bfp to 32" esa
-b399 cfdbr RRF_M "convert to fixed long bfp to 32" esa
-b398 cfebr RRF_M "convert to fixed short bfp to 32" esa
-b34d dxbr RRE_F "divide extended bfp" esa
-b31d ddbr RRE_F "divide long bfp" esa
-ed000000001d ddb RXE_F "divide long bfp" esa
-b30d debr RRE_F "divide short bfp" esa
-ed000000000d deb RXE_F "divide short bfp" esa
-b35b didbr RRF_RM "divide to integer long bfp" esa
-b353 diebr RRF_RM "divide to integer short bfp" esa
-b38c efpc RRE "extract fpc" esa
-b342 ltxbr RRE_F "load and test extended bfp" esa
-b312 ltdbr RRE_F "load and test long bfp" esa
-b302 ltebr RRE_F "load and test short bfp" esa
-b343 lcxbr RRE_F "load complement extended bfp" esa
-b313 lcdbr RRE_F "load complement long bfp" esa
-b303 lcebr RRE_F "load complement short bfp" esa
-b347 fixbr RRF_M "load fp integer extended bfp" esa
-b35f fidbr RRF_M "load fp integer long bfp" esa
-b357 fiebr RRF_M "load fp integer short bfp" esa
-b29d lfpc S "load fpc" esa
-b305 lxdbr RRE_F "load lengthened long to extended bfp" esa
-ed0000000005 lxdb RXE_F "load lengthened long to extended bfp" esa
-b306 lxebr RRE_F "load lengthened short to extended bfp" esa
-ed0000000006 lxeb RXE_F "load lengthened short to extended bfp" esa
-b304 ldebr RRE_F "load lengthened short to long bfp" esa
-ed0000000004 ldeb RXE_F "load lengthened short to long bfp" esa
-b341 lnxbr RRE_F "load negative extended bfp" esa
-b311 lndbr RRE_F "load negative long bfp" esa
-b301 lnebr RRE_F "load negative short bfp" esa
-b340 lpxbr RRE_F "load positive extended bfp" esa
-b310 lpdbr RRE_F "load positive long bfp" esa
-b300 lpebr RRE_F "load positive short bfp" esa
-b345 ldxbr RRE_F "load rounded extended to long bfp" esa
-b346 lexbr RRE_F "load rounded extended to short bfp" esa
-b344 ledbr RRE_F "load rounded long to short bfp" esa
-b34c mxbr RRE_F "multiply extended bfp" esa
-b31c mdbr RRE_F "multiply long bfp" esa
-ed000000001c mdb RXE_F "multiply long bfp" esa
-b307 mxdbr RRE_F "multiply long to extended bfp" esa
-ed0000000007 mxdb RXE_F "multiply long to extended bfp" esa
-b317 meebr RRE_F "multiply short bfp" esa
-ed0000000017 meeb RXE_F "multiply short bfp" esa
-b30c mdebr RRE_F "multiply short to long bfp" esa
-ed000000000c mdeb RXE_F "multiply short to long bfp" esa
-b31e madbr RRF_R "multiply and add long bfp" esa
-ed000000001e madb RXF "multiply and add long bfp" esa
-b30e maebr RRF_R "multiply and add short bfp" esa
-ed000000000e maeb RXF "multiply and add short bfp" esa
-b31f msdbr RRF_R "multiply and subtract long bfp" esa
-ed000000001f msdb RXF "multiply and subtract long bfp" esa
-b30f msebr RRF_R "multiply and subtract short bfp" esa
-ed000000000f mseb RXF "multiply and subtract short bfp" esa
-b384 sfpc RRE "set fpc" esa
-b299 srnm S "set rounding mode" esa
-b316 sqxbr RRE_F "square root extended bfp" esa
-b315 sqdbr RRE_F "square root long bfp" esa
-ed0000000015 sqdb RXE_F "square root long bfp" esa
-b314 sqebr RRE_F "square root short bfp" esa
-ed0000000014 sqeb RXE_F "square root short bfp" esa
-b29c stfpc S "store fpc" esa
-b34b sxbr RRE_F "subtract extended bfp" esa
-b31b sdbr RRE_F "subtract long bfp" esa
-ed000000001b sdb RXE_F "subtract long bfp" esa
-b30b sebr RRE_F "subtract short bfp" esa
-ed000000000b seb RXE_F "subtract short bfp" esa
-ed0000000012 tcxb RXE_F "test data class extended bfp" esa
-ed0000000011 tcdb RXE_F "test data class long bfp" esa
-ed0000000010 tceb RXE_F "test data class short bfp" esa
-b274 siga S "signal adapter" esa
+57 x RX_RRRD "exclusive OR" esa
+d7 xc SS_L0RDRD "exclusive OR" esa
+97 xi SI_URD "exclusive OR" esa
+17 xr RR_RR "exclusive OR" esa
+f8 zap SS_LLRDRD "zero and add" esa
+a70a ahi RI_RI "add halfword immediate" esa
+84 brxh RSI_RRP "branch relative on index high" esa
+85 brxle RSI_RRP "branch relative on index low or equal" esa
+a705 bras RI_RP "branch relative and save" esa
+a704 brc RI_UP "branch relative on condition" esa
+a706 brct RI_RP "branch relative on count" esa
+b241 cksm RRE_RR "checksum" esa
+a70e chi RI_RI "compare halfword immediate" esa
+a9 clcle RS_RRRD "compare logical long extended" esa
+a708 lhi RI_RI "load halfword immediate" esa
+a8 mvcle RS_RRRD "move long extended" esa
+a70c mhi RI_RI "multiply halfword immediate" esa
+b252 msr RRE_RR "multiply single" esa
+71 ms RX_RRRD "multiply single" esa
+a700 tmh RI_RU "test under mask high" esa
+a701 tml RI_RU "test under mask low" esa
+0700 nopr RR_0R "no operation" esa
+0710 bor RR_0R "branch on overflow / if ones" esa
+0720 bhr RR_0R "branch on high" esa
+0720 bpr RR_0R "branch on plus" esa
+0730 bnler RR_0R "branch on not low or equal" esa
+0740 blr RR_0R "branch on low" esa
+0740 bmr RR_0R "branch on minus / if mixed" esa
+0750 bnher RR_0R "branch on not high or equal" esa
+0760 blhr RR_0R "branch on low or high" esa
+0770 bner RR_0R "branch on not equal" esa
+0770 bnzr RR_0R "branch on not zero / if not zeros" esa
+0780 ber RR_0R "branch on equal" esa
+0780 bzr RR_0R "branch on zero / if zeros" esa
+0790 bnlhr RR_0R "branch on not low or high" esa
+07a0 bher RR_0R "branch on high or equal" esa
+07b0 bnlr RR_0R "branch on not low" esa
+07b0 bnmr RR_0R "branch on not minus / if not mixed" esa
+07c0 bler RR_0R "brach on low or equal" esa
+07d0 bnhr RR_0R "branch on not high" esa
+07d0 bnpr RR_0R "branch on not plus" esa
+07e0 bnor RR_0R "branch on not overflow / if not ones" esa
+07f0 br RR_0R "unconditional branch" esa
+4700 nop RX_0RRD "no operation" esa
+4710 bo RX_0RRD "branch on overflow / if ones" esa
+4720 bh RX_0RRD "branch on high" esa
+4720 bp RX_0RRD "branch on plus" esa
+4730 bnle RX_0RRD "branch on not low or equal" esa
+4740 bl RX_0RRD "branch on low" esa
+4740 bm RX_0RRD "branch on minus / if mixed" esa
+4750 bnhe RX_0RRD "branch on not high or equal" esa
+4760 blh RX_0RRD "branch on low or high" esa
+4770 bne RX_0RRD "branch on not equal" esa
+4770 bnz RX_0RRD "branch on not zero / if not zeros" esa
+4780 be RX_0RRD "branch on equal" esa
+4780 bz RX_0RRD "branch on zero / if zeros" esa
+4790 bnlh RX_0RRD "branch on not low or high" esa
+47a0 bhe RX_0RRD "branch on high or equal" esa
+47b0 bnl RX_0RRD "branch on not low" esa
+47b0 bnm RX_0RRD "branch on not minus / if not mixed" esa
+47c0 ble RX_0RRD "branch on low or equal" esa
+47d0 bnh RX_0RRD "branch on not high" esa
+47d0 bnp RX_0RRD "branch on not plus" esa
+47e0 bno RX_0RRD "branch on not overflow / if not ones" esa
+47f0 b RX_0RRD "unconditional branch" esa
+a714 jo RI_0P "jump on overflow / if ones" esa
+a724 jh RI_0P "jump on A high" esa
+a724 jp RI_0P "jump on plus" esa
+a734 jnle RI_0P "jump on not low or equal" esa
+a744 jl RI_0P "jump on A low" esa
+a744 jm RI_0P "jump on minus / if mixed" esa
+a754 jnhe RI_0P "jump on not high or equal" esa
+a764 jlh RI_0P "jump on low or high" esa
+a774 jne RI_0P "jump on A not equal B" esa
+a774 jnz RI_0P "jump on not zero / if not zeros" esa
+a784 je RI_0P "jump on A equal B" esa
+a784 jz RI_0P "jump on zero / if zeros" esa
+a794 jnlh RI_0P "jump on not low or high" esa
+a7a4 jhe RI_0P "jump on high or equal" esa
+a7b4 jnl RI_0P "jump on A not low" esa
+a7b4 jnm RI_0P "jump on not minus / if not mixed" esa
+a7c4 jle RI_0P "jump on low or equal" esa
+a7d4 jnh RI_0P "jump on A not high" esa
+a7d4 jnp RI_0P "jump on not plus" esa
+a7e4 jno RI_0P "jump on not overflow / if not ones" esa
+a7f4 j RI_0P "jump" esa
+b34a axbr RRE_FF "add extended bfp" esa
+b31a adbr RRE_FF "add long bfp" esa
+ed000000001a adb RXE_FRRD "add long bfp" esa
+b30a aebr RRE_FF "add short bfp" esa
+ed000000000a aeb RXE_FRRD "add short bfp" esa
+b349 cxbr RRE_FF "compare extended bfp" esa
+b319 cdbr RRE_FF "compare long bfp" esa
+ed0000000019 cdb RXE_FRRD "compare long bfp" esa
+b309 cebr RRE_FF "compare short bfp" esa
+ed0000000009 ceb RXE_FRRD "compare short bfp" esa
+b348 kxbr RRE_FF "compare and signal extended bfp" esa
+b318 kdbr RRE_FF "compare and signal long bfp" esa
+ed0000000018 kdb RXE_FRRD "compare and signal long bfp" esa
+b308 kebr RRE_FF "compare and signal short bfp" esa
+ed0000000008 keb RXE_FRRD "compare and signal short bfp" esa
+b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" esa
+b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" esa
+b394 cefbr RRE_RF "convert from fixed 32 to short bfp" esa
+b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" esa
+b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" esa
+b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" esa
+b34d dxbr RRE_FF "divide extended bfp" esa
+b31d ddbr RRE_FF "divide long bfp" esa
+ed000000001d ddb RXE_FRRD "divide long bfp" esa
+b30d debr RRE_FF "divide short bfp" esa
+ed000000000d deb RXE_FRRD "divide short bfp" esa
+b35b didbr RRF_FUFF "divide to integer long bfp" esa
+b353 diebr RRF_FUFF "divide to integer short bfp" esa
+b38c efpc RRE_RR "extract fpc" esa
+b342 ltxbr RRE_FF "load and test extended bfp" esa
+b312 ltdbr RRE_FF "load and test long bfp" esa
+b302 ltebr RRE_FF "load and test short bfp" esa
+b343 lcxbr RRE_FF "load complement extended bfp" esa
+b313 lcdbr RRE_FF "load complement long bfp" esa
+b303 lcebr RRE_FF "load complement short bfp" esa
+b347 fixbr RRF_U0FF "load fp integer extended bfp" esa
+b35f fidbr RRF_U0FF "load fp integer long bfp" esa
+b357 fiebr RRF_U0FF "load fp integer short bfp" esa
+b29d lfpc S_RD "load fpc" esa
+b305 lxdbr RRE_FF "load lengthened long to extended bfp" esa
+ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" esa
+b306 lxebr RRE_FF "load lengthened short to extended bfp" esa
+ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" esa
+b304 ldebr RRE_FF "load lengthened short to long bfp" esa
+ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" esa
+b341 lnxbr RRE_FF "load negative extended bfp" esa
+b311 lndbr RRE_FF "load negative long bfp" esa
+b301 lnebr RRE_FF "load negative short bfp" esa
+b340 lpxbr RRE_FF "load positive extended bfp" esa
+b310 lpdbr RRE_FF "load positive long bfp" esa
+b300 lpebr RRE_FF "load positive short bfp" esa
+b345 ldxbr RRE_FF "load rounded extended to long bfp" esa
+b346 lexbr RRE_FF "load rounded extended to short bfp" esa
+b344 ledbr RRE_FF "load rounded long to short bfp" esa
+b34c mxbr RRE_FF "multiply extended bfp" esa
+b31c mdbr RRE_FF "multiply long bfp" esa
+ed000000001c mdb RXE_FRRD "multiply long bfp" esa
+b307 mxdbr RRE_FF "multiply long to extended bfp" esa
+ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" esa
+b317 meebr RRE_FF "multiply short bfp" esa
+ed0000000017 meeb RXE_FRRD "multiply short bfp" esa
+b30c mdebr RRE_FF "multiply short to long bfp" esa
+ed000000000c mdeb RXE_FRRD "multiply short to long bfp" esa
+b31e madbr RRF_F0FF "multiply and add long bfp" esa
+ed000000001e madb RXF_FRRDF "multiply and add long bfp" esa
+b30e maebr RRF_F0FF "multiply and add short bfp" esa
+ed000000000e maeb RXF_FRRDF "multiply and add short bfp" esa
+b31f msdbr RRF_F0FF "multiply and subtract long bfp" esa
+ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" esa
+b30f msebr RRF_F0FF "multiply and subtract short bfp" esa
+ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" esa
+b384 sfpc RRE_RR "set fpc" esa
+b299 srnm S_RD "set rounding mode" esa
+b316 sqxbr RRE_FF "square root extended bfp" esa
+b315 sqdbr RRE_FF "square root long bfp" esa
+ed0000000015 sqdb RXE_FRRD "square root long bfp" esa
+b314 sqebr RRE_FF "square root short bfp" esa
+ed0000000014 sqeb RXE_FRRD "square root short bfp" esa
+b29c stfpc S_RD "store fpc" esa
+b34b sxbr RRE_FF "subtract extended bfp" esa
+b31b sdbr RRE_FF "subtract long bfp" esa
+ed000000001b sdb RXE_FRRD "subtract long bfp" esa
+b30b sebr RRE_FF "subtract short bfp" esa
+ed000000000b seb RXE_FRRD "subtract short bfp" esa
+ed0000000012 tcxb RXE_FRRD "test data class extended bfp" esa
+ed0000000011 tcdb RXE_FRRD "test data class long bfp" esa
+ed0000000010 tceb RXE_FRRD "test data class short bfp" esa
+b274 siga S_RD "signal adapter" esa
# are the following instructions confidential ??
-b2a6 cuutf RRE "convert unicode to utf-8" esa
-b2a7 cutfu RRE "convert utf-8 to unicode" esa
-ee plo SS_PLO "perform locked operation" esa
-b25a bsa RRE "branch and set authority" esa
-b277 rp S "resume program" esa
+b2a6 cuutf RRE_RR "convert unicode to utf-8" esa
+b2a7 cutfu RRE_RR "convert utf-8 to unicode" esa
+ee plo SS_RRRDRD2 "perform locked operation" esa
+b25a bsa RRE_RR "branch and set authority" esa
+b277 rp S_RD "resume program" esa
0107 sckpf E "set clock programmable field" esa
-b27d stsi S "store system information" esa
+b27d stsi S_RD "store system information" esa
01ff trap2 E "trap" esa
-b2ff trap4 S "trap4" esa
+b2ff trap4 S_RD "trap4" esa
# Here are the new esame instructions:
-b946 bctgr RRE "branch on count 64" esame
-b900 lpgr RRE "load positive 64" esame
-b910 lpgfr RRE "load positive 64<32" esame
-b901 lngr RRE "load negative 64" esame
-b911 lngfr RRE "load negative 64<32" esame
-b902 ltgr RRE "load and test 64" esame
-b912 ltgfr RRE "load and test 64<32" esame
-b903 lcgr RRE "load complement 64" esame
-b913 lcgfr RRE "load complement 64<32" esame
-b980 ngr RRE "and 64" esame
-b921 clgr RRE "compare logical 64" esame
-b931 clgfr RRE "compare logical 64<32" esame
-b981 ogr RRE "or 64" esame
-b982 xgr RRE "exclusive or 64" esame
-b904 lgr RRE "load 64" esame
-b914 lgfr RRE "load 64<32" esame
-b920 cgr RRE "compare 64" esame
-b930 cgfr RRE "compare 64<32" esame
-b908 agr RRE "add 64" esame
-b918 agfr RRE "add 64<32" esame
-b909 sgr RRE "subtract 64" esame
-b919 sgfr RRE "subtract 64<32" esame
-b90a algr RRE "add logical 64" esame
-b91a algfr RRE "add logical 64<32" esame
-b90b slgr RRE "subtract logical 64" esame
-b91b slgfr RRE "subtract logical 64<32" esame
-e30000000046 bctg RXE "branch on count 64" esame
-e3000000002e cvdg RXE "convert to decimal 64" esame
-e3000000000e cvbg RXE "convert to binary 64" esame
-e30000000024 stg RXE "store 64" esame
-e30000000080 ng RXE "and 64" esame
-e30000000021 clg RXE "compare logical 64" esame
-e30000000031 clgf RXE "comparee logical 64<32" esame
-e30000000081 og RXE "or 64" esame
-e30000000082 xg RXE "exclusive or 64" esame
-e30000000004 lg RXE "load 64" esame
-e30000000014 lgf RXE "load 64<32" esame
-e30000000015 lgh RXE "load halfword 64" esame
-e30000000020 cg RXE "compare 64" esame
-e30000000030 cgf RXE "compare 64<32" esame
-e30000000008 ag RXE "add 64" esame
-e30000000018 agf RXE "add 64<32" esame
-e30000000009 sg RXE "subtract 64" esame
-e30000000019 sgf RXE "subtract 64<32" esame
-e3000000000a alg RXE "add logical 64" esame
-e3000000001a algf RXE "add logical 64<32" esame
-e3000000000b slg RXE "subtract logical 64" esame
-e3000000001b slgf RXE "subtract logical 64<32" esame
-e3000000000c msg RXE "multiply single 64" esame
-e3000000001c msgf RXE "multiply single 64<32" esame
-ec0000000044 brxhg RIE_A "branch relative on index high 64" esame
-ec0000000045 brxlg RIE_A "branch relative on index low or equal 64" esame
-eb0000000044 bxhg RSE_R "branch on index high 64" esame
-eb0000000045 bxleg RSE_R "branch on index low or equal 64" esame
-eb000000000c srlg RSE_R "shift right single logical 64" esame
-eb000000000d sllg RSE_R "shift left single logical 64" esame
-eb000000000a srag RSE_R "shift right single 64" esame
-eb000000000b slag RSE_R "shift left single 64" esame
-eb0000000024 stmg RSE_R "store multiple 64" esame
-eb0000000026 stmh RSE_R "store multiple high" esame
-eb0000000004 lmg RSE_R "load multiple 64" esame
-eb0000000096 lmh RSE_R "load multiple high" esame
-ef lmd SS_LMD "load multiple disjoint" esame
-eb000000000f tracg RSE_R "trace 64" esame
-e30000000003 lrag RXE "load real address 64" esame
-e50000000002 strag SSE "store read address" esame
-eb0000000025 stctg RSE_R "store control 64" esame
-eb000000002f lctlg RSE_R "load control 64" esame
-eb0000000030 csg RSE_R "compare and swap 64" esame
-eb000000003e cdsg RSE_R "compare double and swap 64" esame
-eb0000000020 clmh RSE_M "compare logical characters under mask high" esame
-eb000000002c stcmh RSE_M "store characters under mask high" esame
-eb0000000080 icmh RSE_M "insert characters under mask high" esame
-a700 tmlh RI_U "test under mask low high" esame
-a702 tmhh RI_U "test under mask high high" esame
-a701 tmll RI_U "test under mask low low" esame
-a703 tmhl RI_U "test under mask high low" esame
-c004 brcl RIL_MA "branch relative on condition long" esame
-c014 jgo RIL_B "jump long on overflow / if ones" esame
-c024 jgh RIL_B "jump long on high" esame
-c024 jgp RIL_B "jump long on plus" esame
-c034 jgnle RIL_B "jump long on not low or equal" esame
-c044 jgl RIL_B "jump long on low" esame
-c044 jgm RIL_B "jump long on minus / if mixed" esame
-c054 jgnhe RIL_B "jump long on not high or equal" esame
-c064 jglh RIL_B "jump long on low or high" esame
-c074 jgne RIL_B "jump long on not equal" esame
-c074 jgnz RIL_B "jump long on not zero / if not zeros" esame
-c084 jge RIL_B "jump long on equal" esame
-c084 jgz RIL_B "jump long on zero / if zeros" esame
-c094 jgnlh RIL_B "jump long on not low or high" esame
-c0a4 jghe RIL_B "jump long on high or equal" esame
-c0b4 jgnl RIL_B "jump long on not low" esame
-c0b4 jgnm RIL_B "jump long on not minus / if not mixed" esame
-c0c4 jgle RIL_B "jump long on low or equal" esame
-c0d4 jgnh RIL_B "jump long on not high" esame
-c0d4 jgnp RIL_B "jump long on not plus" esame
-c0e4 jgno RIL_B "jump long on not overflow / if not ones" esame
-c0f4 jg RIL_B "jump long" esame
-c005 brasl RIL_A "branch relative and save long" esame
-a707 brctg RI_A "branch relative on count 64" esame
-a709 lghi RI "load halfword immediate 64" esame
-a70b aghi RI "add halfword immediate 64" esame
-a70d mghi RI "multiply halfword immediate 64" esame
-a70f cghi RI "compare halfword immediate 64" esame
-b925 sturg RRE "store using real address 64" esame
-b90e eregg RRE "extract stacked registers 64" esame
-b905 lurag RRE "load using real address 64" esame
-b90c msgr RRE "multiply single 64" esame
-b91c msgfr RRE "multiply single 64<32" esame
-b3a4 cegbr RRE "convert from fixed 64 to short bfp" esame
-b3a5 cdgbr RRE "convert from fixed 64 to long bfp" esame
-b3a6 cxgbr RRE "convert from fixed 64 to extended bfp" esame
-b3a8 cgebr RRF_M "convert to fixed short bfd to 64" esame
-b3a9 cgdbr RRF_M "convert to fixed long bfp to 64" esame
-b3aa cgxbr RRF_M "convert to fixed extended bfp to 64" esame
-b3c4 cegr RRE "convert from fixed 64 to short hfp" esame
-b3c5 cdgr RRE "convert from fixed 64 to long hfp" esame
-b3c6 cxgr RRE "convert from fixed 64 to extended hfp" esame
-b3c8 cger RRF_F "convert to fixed short hfp to 64" esame
-b3c9 cgdr RRF_F "convert to fixed long hfp to 64" esame
-b3ca cgxr RRF_F "convert to fixed extended hfp to 64" esame
+b946 bctgr RRE_RR "branch on count 64" esame
+b900 lpgr RRE_RR "load positive 64" esame
+b910 lpgfr RRE_RR "load positive 64<32" esame
+b901 lngr RRE_RR "load negative 64" esame
+b911 lngfr RRE_RR "load negative 64<32" esame
+b902 ltgr RRE_RR "load and test 64" esame
+b912 ltgfr RRE_RR "load and test 64<32" esame
+b903 lcgr RRE_RR "load complement 64" esame
+b913 lcgfr RRE_RR "load complement 64<32" esame
+b980 ngr RRE_RR "and 64" esame
+b921 clgr RRE_RR "compare logical 64" esame
+b931 clgfr RRE_RR "compare logical 64<32" esame
+b981 ogr RRE_RR "or 64" esame
+b982 xgr RRE_RR "exclusive or 64" esame
+b904 lgr RRE_RR "load 64" esame
+b914 lgfr RRE_RR "load 64<32" esame
+b920 cgr RRE_RR "compare 64" esame
+b930 cgfr RRE_RR "compare 64<32" esame
+b908 agr RRE_RR "add 64" esame
+b918 agfr RRE_RR "add 64<32" esame
+b909 sgr RRE_RR "subtract 64" esame
+b919 sgfr RRE_RR "subtract 64<32" esame
+b90a algr RRE_RR "add logical 64" esame
+b91a algfr RRE_RR "add logical 64<32" esame
+b90b slgr RRE_RR "subtract logical 64" esame
+b91b slgfr RRE_RR "subtract logical 64<32" esame
+e30000000046 bctg RXE_RRRD "branch on count 64" esame
+e3000000002e cvdg RXE_RRRD "convert to decimal 64" esame
+e3000000000e cvbg RXE_RRRD "convert to binary 64" esame
+e30000000024 stg RXE_RRRD "store 64" esame
+e30000000080 ng RXE_RRRD "and 64" esame
+e30000000021 clg RXE_RRRD "compare logical 64" esame
+e30000000031 clgf RXE_RRRD "comparee logical 64<32" esame
+e30000000081 og RXE_RRRD "or 64" esame
+e30000000082 xg RXE_RRRD "exclusive or 64" esame
+e30000000004 lg RXE_RRRD "load 64" esame
+e30000000014 lgf RXE_RRRD "load 64<32" esame
+e30000000015 lgh RXE_RRRD "load halfword 64" esame
+e30000000020 cg RXE_RRRD "compare 64" esame
+e30000000030 cgf RXE_RRRD "compare 64<32" esame
+e30000000008 ag RXE_RRRD "add 64" esame
+e30000000018 agf RXE_RRRD "add 64<32" esame
+e30000000009 sg RXE_RRRD "subtract 64" esame
+e30000000019 sgf RXE_RRRD "subtract 64<32" esame
+e3000000000a alg RXE_RRRD "add logical 64" esame
+e3000000001a algf RXE_RRRD "add logical 64<32" esame
+e3000000000b slg RXE_RRRD "subtract logical 64" esame
+e3000000001b slgf RXE_RRRD "subtract logical 64<32" esame
+e3000000000c msg RXE_RRRD "multiply single 64" esame
+e3000000001c msgf RXE_RRRD "multiply single 64<32" esame
+ec0000000044 brxhg RIE_RRP "branch relative on index high 64" esame
+ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" esame
+eb0000000044 bxhg RSE_RRRD "branch on index high 64" esame
+eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" esame
+eb000000000c srlg RSE_RRRD "shift right single logical 64" esame
+eb000000000d sllg RSE_RRRD "shift left single logical 64" esame
+eb000000000a srag RSE_RRRD "shift right single 64" esame
+eb000000000b slag RSE_RRRD "shift left single 64" esame
+eb0000000024 stmg RSE_RRRD "store multiple 64" esame
+eb0000000026 stmh RSE_RRRD "store multiple high" esame
+eb0000000004 lmg RSE_RRRD "load multiple 64" esame
+eb0000000096 lmh RSE_RRRD "load multiple high" esame
+ef lmd SS_RRRDRD3 "load multiple disjoint" esame
+eb000000000f tracg RSE_RRRD "trace 64" esame
+e30000000003 lrag RXE_RRRD "load real address 64" esame
+e50000000002 strag SSE_RDRD "store read address" esame
+eb0000000025 stctg RSE_RRRD "store control 64" esame
+eb000000002f lctlg RSE_RRRD "load control 64" esame
+eb0000000030 csg RSE_RRRD "compare and swap 64" esame
+eb000000003e cdsg RSE_RRRD "compare double and swap 64" esame
+eb0000000020 clmh RSE_RURD "compare logical characters under mask high" esame
+eb000000002c stcmh RSE_RURD "store characters under mask high" esame
+eb0000000080 icmh RSE_RURD "insert characters under mask high" esame
+a700 tmlh RI_RU "test under mask low high" esame
+a702 tmhh RI_RU "test under mask high high" esame
+a701 tmll RI_RU "test under mask low low" esame
+a703 tmhl RI_RU "test under mask high low" esame
+c004 brcl RIL_UP "branch relative on condition long" esame
+c014 jgo RIL_0P "jump long on overflow / if ones" esame
+c024 jgh RIL_0P "jump long on high" esame
+c024 jgp RIL_0P "jump long on plus" esame
+c034 jgnle RIL_0P "jump long on not low or equal" esame
+c044 jgl RIL_0P "jump long on low" esame
+c044 jgm RIL_0P "jump long on minus / if mixed" esame
+c054 jgnhe RIL_0P "jump long on not high or equal" esame
+c064 jglh RIL_0P "jump long on low or high" esame
+c074 jgne RIL_0P "jump long on not equal" esame
+c074 jgnz RIL_0P "jump long on not zero / if not zeros" esame
+c084 jge RIL_0P "jump long on equal" esame
+c084 jgz RIL_0P "jump long on zero / if zeros" esame
+c094 jgnlh RIL_0P "jump long on not low or high" esame
+c0a4 jghe RIL_0P "jump long on high or equal" esame
+c0b4 jgnl RIL_0P "jump long on not low" esame
+c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" esame
+c0c4 jgle RIL_0P "jump long on low or equal" esame
+c0d4 jgnh RIL_0P "jump long on not high" esame
+c0d4 jgnp RIL_0P "jump long on not plus" esame
+c0e4 jgno RIL_0P "jump long on not overflow / if not ones" esame
+c0f4 jg RIL_0P "jump long" esame
+c005 brasl RIL_RP "branch relative and save long" esame
+a707 brctg RI_RP "branch relative on count 64" esame
+a709 lghi RI_RI "load halfword immediate 64" esame
+a70b aghi RI_RI "add halfword immediate 64" esame
+a70d mghi RI_RI "multiply halfword immediate 64" esame
+a70f cghi RI_RI "compare halfword immediate 64" esame
+b925 sturg RRE_RR "store using real address 64" esame
+b90e eregg RRE_RR "extract stacked registers 64" esame
+b905 lurag RRE_RR "load using real address 64" esame
+b90c msgr RRE_RR "multiply single 64" esame
+b91c msgfr RRE_RR "multiply single 64<32" esame
+b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" esame
+b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" esame
+b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" esame
+b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" esame
+b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" esame
+b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" esame
+b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" esame
+b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" esame
+b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" esame
+b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" esame
+b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" esame
+b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" esame
010b tam E "test addressing mode" esame
010c sam24 E "set addressing mode 24" esame
010d sam31 E "set addressing mode 31" esame
010e sam64 E "set addressing mode 64" esame
-a500 iihh RI_U "insert immediate high high" esame
-a501 iihl RI_U "insert immediate high low" esame
-a502 iilh RI_U "insert immediate low high" esame
-a503 iill RI_U "insert immediate low low" esame
-a504 nihh RI_U "and immediate high high" esame
-a505 nihl RI_U "and immediate high low" esame
-a506 nilh RI_U "and immediate low high" esame
-a507 nill RI_U "and immediate low low" esame
-a508 oihh RI_U "or immediate high high" esame
-a509 oihl RI_U "or immediate high low" esame
-a50a oilh RI_U "or immediate low high" esame
-a50b oill RI_U "or immediate low low" esame
-a50c llihh RI_U "load logical immediate high high" esame
-a50d llihl RI_U "load logical immediate high low" esame
-a50e llilh RI_U "load logical immediate low high" esame
-a50f llill RI_U "load logical immediate low low" esame
-b2b1 stfl S "store facility list" esame
-b2b2 lpswe S "load psw extended" esame
-b90d dsgr RRE "divide single 64" esame
-b90f lrvgr RRE "load reversed 64" esame
-b916 llgfr RRE "load logical 64<32" esame
-b917 llgtr RRE "load logical thirty one bits" esame
-b91d dsgfr RRE "divide single 64<32" esame
-b91f lrvr RRE "load reversed 32" esame
-b986 mlgr RRE "multiply logical 64" esame
-b987 dlgr RRE "divide logical 64" esame
-b988 alcgr RRE "add logical with carry 64" esame
-b989 slbgr RRE "subtract logical with borrow 64" esame
-b98d epsw RRE "extract psw" esame
-b996 mlr RRE "multiply logical 32" esame
-b997 dlr RRE "divide logical 32" esame
-b998 alcr RRE "add logical with carry 32" esame
-b999 slbr RRE "subtract logical with borrow 32" esame
-b99d esea RRE_R "extract and set extended authority" esame
-c000 larl RIL_A "load address relative long" esame
-e3000000000d dsg RXE "divide single 64" esame
-e3000000000f lrvg RXE "load reversed 64" esame
-e30000000016 llgf RXE "load logical 64<32" esame
-e30000000017 llgt RXE "load logical thirty one bits" esame
-e3000000001d dsgf RXE "divide single 64<32" esame
-e3000000001e lrv RXE "load reversed 32" esame
-e3000000001f lrvh RXE "load reversed 16" esame
-e3000000002f strvg RXE "store reversed 64" esame
-e3000000003e strv RXE "store reversed 32" esame
-e3000000003f strvh RXE "store reversed 64" esame
-e30000000086 mlg RXE "multiply logical 64" esame
-e30000000087 dlg RXE "divide logical 64" esame
-e30000000088 alcg RXE "add logical with carry 64" esame
-e30000000089 slbg RXE "subtract logical with borrow 64" esame
-e3000000008e stpq RXE "store pair to quadword" esame
-e3000000008f lpq RXE "load pair from quadword" esame
-e30000000096 ml RXE "multiply logical 32" esame
-e30000000097 dl RXE "divide logical 32" esame
-e30000000098 alc RXE "add logical with carry 32" esame
-e30000000099 slb RXE "subtract logical with borrow 32" esame
-e30000000090 llgc RXE "load logical character" esame
-e30000000091 llgh RXE "load logical halfword" esame
-eb000000001c rllg RSE_R "rotate left single logical 64" esame
-eb000000001d rll RSE_R "rotate left single logical 32" esame
-b278 stcke S "store clock extended" esame
-b2a5 tre RRE "translate extended" esame
-eb000000008e mvclu RSE_R "move long unicode" esame
-e9 pka SS_L "pack ascii" esame
-e1 pku SS_L "pack unicode" esame
-b993 troo RRE "translate one to one" esame
-b992 trot RRE "translate one to two" esame
-b991 trto RRE "translate two to one" esame
-b990 trtt RRE "translate two to two" esame
-ea unpka SS_L "unpack ascii" esame
-e2 unpku SS_L "unpack unicode" esame
-b358 thder RRE "convert short bfp to long hfp" esame
-b359 thdr RRE "convert long bfp to long hfp" esame
-b350 tbedr RRF_M "convert long hfp to short bfp" esame
-b351 tbdr RRF_M "convert long hfp to long bfp" esame
-b374 lzer RRE_R "load short zero" esame
-b375 lzdr RRE_R "load long zero" esame
-b376 lzxr RRE_R "load extended zero" esame
+a500 iihh RI_RU "insert immediate high high" esame
+a501 iihl RI_RU "insert immediate high low" esame
+a502 iilh RI_RU "insert immediate low high" esame
+a503 iill RI_RU "insert immediate low low" esame
+a504 nihh RI_RU "and immediate high high" esame
+a505 nihl RI_RU "and immediate high low" esame
+a506 nilh RI_RU "and immediate low high" esame
+a507 nill RI_RU "and immediate low low" esame
+a508 oihh RI_RU "or immediate high high" esame
+a509 oihl RI_RU "or immediate high low" esame
+a50a oilh RI_RU "or immediate low high" esame
+a50b oill RI_RU "or immediate low low" esame
+a50c llihh RI_RU "load logical immediate high high" esame
+a50d llihl RI_RU "load logical immediate high low" esame
+a50e llilh RI_RU "load logical immediate low high" esame
+a50f llill RI_RU "load logical immediate low low" esame
+b2b1 stfl S_RD "store facility list" esame
+b2b2 lpswe S_RD "load psw extended" esame
+b90d dsgr RRE_RR "divide single 64" esame
+b90f lrvgr RRE_RR "load reversed 64" esame
+b916 llgfr RRE_RR "load logical 64<32" esame
+b917 llgtr RRE_RR "load logical thirty one bits" esame
+b91d dsgfr RRE_RR "divide single 64<32" esame
+b91f lrvr RRE_RR "load reversed 32" esame
+b986 mlgr RRE_RR "multiply logical 64" esame
+b987 dlgr RRE_RR "divide logical 64" esame
+b988 alcgr RRE_RR "add logical with carry 64" esame
+b989 slbgr RRE_RR "subtract logical with borrow 64" esame
+b98d epsw RRE_RR "extract psw" esame
+b996 mlr RRE_RR "multiply logical 32" esame
+b997 dlr RRE_RR "divide logical 32" esame
+b998 alcr RRE_RR "add logical with carry 32" esame
+b999 slbr RRE_RR "subtract logical with borrow 32" esame
+b99d esea RRE_R0 "extract and set extended authority" esame
+c000 larl RIL_RP "load address relative long" esame
+e3000000000d dsg RXE_RRRD "divide single 64" esame
+e3000000000f lrvg RXE_RRRD "load reversed 64" esame
+e30000000016 llgf RXE_RRRD "load logical 64<32" esame
+e30000000017 llgt RXE_RRRD "load logical thirty one bits" esame
+e3000000001d dsgf RXE_RRRD "divide single 64<32" esame
+e3000000001e lrv RXE_RRRD "load reversed 32" esame
+e3000000001f lrvh RXE_RRRD "load reversed 16" esame
+e3000000002f strvg RXE_RRRD "store reversed 64" esame
+e3000000003e strv RXE_RRRD "store reversed 32" esame
+e3000000003f strvh RXE_RRRD "store reversed 64" esame
+e30000000086 mlg RXE_RRRD "multiply logical 64" esame
+e30000000087 dlg RXE_RRRD "divide logical 64" esame
+e30000000088 alcg RXE_RRRD "add logical with carry 64" esame
+e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" esame
+e3000000008e stpq RXE_RRRD "store pair to quadword" esame
+e3000000008f lpq RXE_RRRD "load pair from quadword" esame
+e30000000096 ml RXE_RRRD "multiply logical 32" esame
+e30000000097 dl RXE_RRRD "divide logical 32" esame
+e30000000098 alc RXE_RRRD "add logical with carry 32" esame
+e30000000099 slb RXE_RRRD "subtract logical with borrow 32" esame
+e30000000090 llgc RXE_RRRD "load logical character" esame
+e30000000091 llgh RXE_RRRD "load logical halfword" esame
+eb000000001c rllg RSE_RRRD "rotate left single logical 64" esame
+eb000000001d rll RSE_RRRD "rotate left single logical 32" esame
+b278 stcke S_RD "store clock extended" esame
+b2a5 tre RRE_RR "translate extended" esame
+eb000000008e mvclu RSE_RRRD "move long unicode" esame
+e9 pka SS_L0RDRD "pack ascii" esame
+e1 pku SS_L0RDRD "pack unicode" esame
+b993 troo RRE_RR "translate one to one" esame
+b992 trot RRE_RR "translate one to two" esame
+b991 trto RRE_RR "translate two to one" esame
+b990 trtt RRE_RR "translate two to two" esame
+ea unpka SS_L0RDRD "unpack ascii" esame
+e2 unpku SS_L0RDRD "unpack unicode" esame
+b358 thder RRE_RR "convert short bfp to long hfp" esame
+b359 thdr RRE_RR "convert long bfp to long hfp" esame
+b350 tbedr RRF_U0FF "convert long hfp to short bfp" esame
+b351 tbdr RRF_U0FF "convert long hfp to long bfp" esame
+b374 lzer RRE_R0 "load short zero" esame
+b375 lzdr RRE_R0 "load long zero" esame
+b376 lzxr RRE_R0 "load extended zero" esame
[-- Attachment #3: binutils-test390.diff --]
[-- Type: text/x-diff, Size: 46124 bytes --]
diff -urN src/gas/testsuite/gas/s390/opcode.d src-s390/gas/testsuite/gas/s390/opcode.d
--- src/gas/testsuite/gas/s390/opcode.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,425 @@
+#name: s390 opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: 5a 65 af ff [ ]*a %r6,4095\(%r5,%r10\)
+ 4: 6a 65 af ff [ ]*ad %f6,4095\(%r5,%r10\)
+ 8: ed 65 af ff 00 1a [ ]*adb %f6,4095\(%r5,%r10\)
+ e: b3 1a 00 69 [ ]*adbr %f6,%f9
+ 12: 2a 69 [ ]*adr %f6,%f9
+ 14: 7a 65 af ff [ ]*ae %f6,4095\(%r5,%r10\)
+ 18: ed 65 af ff 00 0a [ ]*aeb %f6,4095\(%r5,%r10\)
+ 1e: b3 0a 00 69 [ ]*aebr %f6,%f9
+ 22: 3a 69 [ ]*aer %f6,%f9
+ 24: 4a 65 af ff [ ]*ah %r6,4095\(%r5,%r10\)
+ 28: a7 6a 80 01 [ ]*ahi %r6,-32767
+ 2c: 5e 65 af ff [ ]*al %r6,4095\(%r5,%r10\)
+ 30: 1e 69 [ ]*alr %r6,%r9
+ 32: fa 58 5f ff af ff [ ]*ap 4095\(6,%r5\),4095\(9,%r10\)
+ 38: 1a 69 [ ]*ar %r6,%r9
+ 3a: 7e 65 af ff [ ]*au %f6,4095\(%r5,%r10\)
+ 3e: 3e 69 [ ]*aur %f6,%f9
+ 40: 6e 65 af ff [ ]*aw %f6,4095\(%r5,%r10\)
+ 44: 2e 69 [ ]*awr %f6,%f9
+ 46: b3 4a 00 69 [ ]*axbr %f6,%f9
+ 4a: 36 69 [ ]*axr %f6,%f9
+ 4c: 47 f5 af ff [ ]*b 4095\(%r5,%r10\)
+ 50: b2 40 00 69 [ ]*bakr %r6,%r9
+ 54: 45 65 af ff [ ]*bal %r6,4095\(%r5,%r10\)
+ 58: 05 69 [ ]*balr %r6,%r9
+ 5a: 4d 65 af ff [ ]*bas %r6,4095\(%r5,%r10\)
+ 5e: 0d 69 [ ]*basr %r6,%r9
+ 60: 0c 69 [ ]*bassm %r6,%r9
+ 62: 47 65 af ff [ ]*blh 4095\(%r5,%r10\)
+ 66: 07 69 [ ]*blhr %r9
+ 68: 46 65 af ff [ ]*bct %r6,4095\(%r5,%r10\)
+ 6c: 06 69 [ ]*bctr %r6,%r9
+ 6e: 47 85 af ff [ ]*be 4095\(%r5,%r10\)
+ 72: 07 89 [ ]*ber %r9
+ 74: 47 25 af ff [ ]*bh 4095\(%r5,%r10\)
+ 78: 47 a5 af ff [ ]*bhe 4095\(%r5,%r10\)
+ 7c: 07 a9 [ ]*bher %r9
+ 7e: 07 29 [ ]*bhr %r9
+ 80: 47 45 af ff [ ]*bl 4095\(%r5,%r10\)
+ 84: 47 c5 af ff [ ]*ble 4095\(%r5,%r10\)
+ 88: 07 c9 [ ]*bler %r9
+ 8a: 47 65 af ff [ ]*blh 4095\(%r5,%r10\)
+ 8e: 07 69 [ ]*blhr %r9
+ 90: 07 49 [ ]*blr %r9
+ 92: 47 45 af ff [ ]*bl 4095\(%r5,%r10\)
+ 96: 07 49 [ ]*blr %r9
+ 98: 47 75 af ff [ ]*bne 4095\(%r5,%r10\)
+ 9c: 07 79 [ ]*bner %r9
+ 9e: 47 d5 af ff [ ]*bnh 4095\(%r5,%r10\)
+ a2: 47 55 af ff [ ]*bnhe 4095\(%r5,%r10\)
+ a6: 07 59 [ ]*bnher %r9
+ a8: 07 d9 [ ]*bnhr %r9
+ aa: 47 b5 af ff [ ]*bnl 4095\(%r5,%r10\)
+ ae: 47 35 af ff [ ]*bnle 4095\(%r5,%r10\)
+ b2: 07 39 [ ]*bnler %r9
+ b4: 47 95 af ff [ ]*bnlh 4095\(%r5,%r10\)
+ b8: 07 99 [ ]*bnlhr %r9
+ ba: 07 b9 [ ]*bnlr %r9
+ bc: 47 b5 af ff [ ]*bnl 4095\(%r5,%r10\)
+ c0: 07 b9 [ ]*bnlr %r9
+ c2: 47 e5 af ff [ ]*bno 4095\(%r5,%r10\)
+ c6: 07 e9 [ ]*bnor %r9
+ c8: 47 d5 af ff [ ]*bnh 4095\(%r5,%r10\)
+ cc: 07 d9 [ ]*bnhr %r9
+ ce: 47 75 af ff [ ]*bne 4095\(%r5,%r10\)
+ d2: 07 79 [ ]*bner %r9
+ d4: 47 15 af ff [ ]*bo 4095\(%r5,%r10\)
+ d8: 07 19 [ ]*bor %r9
+ da: 47 25 af ff [ ]*bh 4095\(%r5,%r10\)
+ de: 07 29 [ ]*bhr %r9
+ e0: 07 f9 [ ]*br %r9
+ e2: a7 95 00 00 [ ]*bras %r9,e2 <foo\+0xe2>
+ e6: a7 64 00 00 [ ]*jlh e6 <foo\+0xe6>
+ ea: a7 66 00 00 [ ]*brct %r6,ea <foo\+0xea>
+ ee: 84 69 00 00 [ ]*brxh %r6,%r9,ee <foo\+0xee>
+ f2: 85 69 00 00 [ ]*brxle %r6,%r9,f2 <foo\+0xf2>
+ f6: b2 5a 00 69 [ ]*bsa %r6,%r9
+ fa: b2 58 00 69 [ ]*bsg %r6,%r9
+ fe: 0b 69 [ ]*bsm %r6,%r9
+ 100: 86 69 5f ff [ ]*bxh %r6,%r9,4095\(%r5\)
+ 104: 87 69 5f ff [ ]*bxle %r6,%r9,4095\(%r5\)
+ 108: 47 85 af ff [ ]*be 4095\(%r5,%r10\)
+ 10c: 07 89 [ ]*ber %r9
+ 10e: 59 65 af ff [ ]*c %r6,4095\(%r5,%r10\)
+ 112: 69 65 af ff [ ]*cd %f6,4095\(%r5,%r10\)
+ 116: ed 65 af ff 00 19 [ ]*cdb %f6,4095\(%r5,%r10\)
+ 11c: b3 19 00 69 [ ]*cdbr %f6,%f9
+ 120: b3 95 00 69 [ ]*cdfbr %r6,%f9
+ 124: 29 69 [ ]*cdr %f6,%f9
+ 126: bb 69 5f ff [ ]*cds %r6,%r9,4095\(%r5\)
+ 12a: 79 65 af ff [ ]*ce %f6,4095\(%r5,%r10\)
+ 12e: ed 65 af ff 00 09 [ ]*ceb %f6,4095\(%r5,%r10\)
+ 134: b3 09 00 69 [ ]*cebr %f6,%f9
+ 138: b3 94 00 69 [ ]*cefbr %r6,%f9
+ 13c: 39 69 [ ]*cer %f6,%f9
+ 13e: b2 1a 5f ff [ ]*cfc 4095\(%r5\)
+ 142: b3 99 50 69 [ ]*cfdbr %f6,5,%r9
+ 146: b3 98 50 69 [ ]*cfebr %f6,5,%r9
+ 14a: b3 9a 50 69 [ ]*cfxbr %f6,5,%r9
+ 14e: 49 65 af ff [ ]*ch %r6,4095\(%r5,%r10\)
+ 152: a7 6e 80 01 [ ]*chi %r6,-32767
+ 156: b2 41 00 69 [ ]*cksm %r6,%r9
+ 15a: 55 65 af ff [ ]*cl %r6,4095\(%r5,%r10\)
+ 15e: d5 ff 5f ff af ff [ ]*clc 4095\(256,%r5\),4095\(%r10\)
+ 164: 0f 69 [ ]*clcl %r6,%r9
+ 166: a9 69 00 0a [ ]*clcle %r6,%r9,10
+ 16a: 95 ff 5f ff [ ]*cli 4095\(%r5\),255
+ 16e: bd 6a 5f ff [ ]*clm %r6,10,4095\(%r5\)
+ 172: 15 69 [ ]*clr %r6,%r9
+ 174: b2 5d 00 69 [ ]*clst %r6,%r9
+ 178: b2 63 00 69 [ ]*cmpsc %r6,%r9
+ 17c: f9 58 5f ff af ff [ ]*cp 4095\(6,%r5\),4095\(9,%r10\)
+ 182: b2 4d 00 69 [ ]*cpya %a6,%a9
+ 186: 19 69 [ ]*cr %r6,%r9
+ 188: ba 69 5f ff [ ]*cs %r6,%r9,4095\(%r5\)
+ 18c: b2 30 00 00 [ ]*csch
+ 190: b2 50 00 69 [ ]*csp %r6,%r9
+ 194: b2 57 00 69 [ ]*cuse %r6,%r9
+ 198: b2 a7 00 69 [ ]*cutfu %r6,%r9
+ 19c: b2 a6 00 69 [ ]*cuutf %r6,%r9
+ 1a0: 4f 65 af ff [ ]*cvb %r6,4095\(%r5,%r10\)
+ 1a4: 4e 65 af ff [ ]*cvd %r6,4095\(%r5,%r10\)
+ 1a8: b3 49 00 69 [ ]*cxbr %f6,%f9
+ 1ac: b3 96 00 69 [ ]*cxfbr %r6,%f9
+ 1b0: 5d 65 af ff [ ]*d %r6,4095\(%r5,%r10\)
+ 1b4: 6d 65 af ff [ ]*dd %f6,4095\(%r5,%r10\)
+ 1b8: ed 65 af ff 00 1d [ ]*ddb %f6,4095\(%r5,%r10\)
+ 1be: b3 1d 00 69 [ ]*ddbr %f6,%f9
+ 1c2: 2d 69 [ ]*ddr %f6,%f9
+ 1c4: 7d 65 af ff [ ]*de %f6,4095\(%r5,%r10\)
+ 1c8: ed 65 af ff 00 0d [ ]*deb %f6,4095\(%r5,%r10\)
+ 1ce: b3 0d 00 69 [ ]*debr %f6,%f9
+ 1d2: 3d 69 [ ]*der %f6,%f9
+ 1d4: 83 69 5f ff [ ]*diag %r6,%r9,4095\(%r5\)
+ 1d8: b3 5b 9a 65 [ ]*didbr %f6,%f9,%f5,10
+ 1dc: b3 53 9a 65 [ ]*diebr %f6,%f9,%f5,10
+ 1e0: fd 58 5f ff af ff [ ]*dp 4095\(6,%r5\),4095\(9,%r10\)
+ 1e6: 1d 69 [ ]*dr %r6,%r9
+ 1e8: b3 4d 00 69 [ ]*dxbr %f6,%f9
+ 1ec: b2 2d 00 60 [ ]*dxr %f6
+ 1f0: b2 4f 00 69 [ ]*ear %r6,%a9
+ 1f4: de ff 5f ff af ff [ ]*ed 4095\(256,%r5\),4095\(%r10\)
+ 1fa: df ff 5f ff af ff [ ]*edmk 4095\(256,%r5\),4095\(%r10\)
+ 200: b3 8c 00 69 [ ]*efpc %r6,%r9
+ 204: b2 26 00 60 [ ]*epar %r6
+ 208: b2 49 00 69 [ ]*ereg %r6,%r9
+ 20c: b2 27 00 60 [ ]*esar %r6
+ 210: b2 4a 00 69 [ ]*esta %r6,%r9
+ 214: 44 60 5f ff [ ]*ex %r6,4095\(%r5\)
+ 218: b3 5f 50 69 [ ]*fidbr %f6,5,%f9
+ 21c: b3 57 50 69 [ ]*fiebr %f6,5,%f9
+ 220: b3 47 50 69 [ ]*fixbr %f6,5,%f9
+ 224: 24 69 [ ]*hdr %f6,%f9
+ 226: 34 69 [ ]*her %f6,%f9
+ 228: b2 31 00 00 [ ]*hsch
+ 22c: b2 24 00 60 [ ]*iac %r6
+ 230: 43 65 af ff [ ]*ic %r6,4095\(%r5,%r10\)
+ 234: bf 6a 5f ff [ ]*icm %r6,10,4095\(%r5\)
+ 238: b2 0b 00 00 [ ]*ipk
+ 23c: b2 22 00 60 [ ]*ipm %r6
+ 240: b2 21 00 69 [ ]*ipte %r6,%r9
+ 244: b2 29 00 69 [ ]*iske %r6,%r9
+ 248: b2 23 00 69 [ ]*ivsk %r6,%r9
+ 24c: a7 f4 00 00 [ ]*j 24c <foo\+0x24c>
+ 250: a7 84 00 00 [ ]*je 250 <foo\+0x250>
+ 254: a7 24 00 00 [ ]*jh 254 <foo\+0x254>
+ 258: a7 a4 00 00 [ ]*jhe 258 <foo\+0x258>
+ 25c: a7 44 00 00 [ ]*jl 25c <foo\+0x25c>
+ 260: a7 c4 00 00 [ ]*jle 260 <foo\+0x260>
+ 264: a7 64 00 00 [ ]*jlh 264 <foo\+0x264>
+ 268: a7 44 00 00 [ ]*jl 268 <foo\+0x268>
+ 26c: a7 74 00 00 [ ]*jne 26c <foo\+0x26c>
+ 270: a7 54 00 00 [ ]*jnhe 270 <foo\+0x270>
+ 274: a7 b4 00 00 [ ]*jnl 274 <foo\+0x274>
+ 278: a7 34 00 00 [ ]*jnle 278 <foo\+0x278>
+ 27c: a7 94 00 00 [ ]*jnlh 27c <foo\+0x27c>
+ 280: a7 b4 00 00 [ ]*jnl 280 <foo\+0x280>
+ 284: a7 e4 00 00 [ ]*jno 284 <foo\+0x284>
+ 288: a7 d4 00 00 [ ]*jnh 288 <foo\+0x288>
+ 28c: a7 74 00 00 [ ]*jne 28c <foo\+0x28c>
+ 290: a7 14 00 00 [ ]*jo 290 <foo\+0x290>
+ 294: a7 24 00 00 [ ]*jh 294 <foo\+0x294>
+ 298: a7 84 00 00 [ ]*je 298 <foo\+0x298>
+ 29c: ed 65 af ff 00 18 [ ]*kdb %f6,4095\(%r5,%r10\)
+ 2a2: b3 18 00 69 [ ]*kdbr %f6,%f9
+ 2a6: ed 65 af ff 00 08 [ ]*keb %f6,4095\(%r5,%r10\)
+ 2ac: b3 08 00 69 [ ]*kebr %f6,%f9
+ 2b0: b3 48 00 69 [ ]*kxbr %f6,%f9
+ 2b4: 58 65 af ff [ ]*l %r6,4095\(%r5,%r10\)
+ 2b8: 41 65 af ff [ ]*la %r6,4095\(%r5,%r10\)
+ 2bc: 51 65 af ff [ ]*lae %r6,4095\(%r5,%r10\)
+ 2c0: 9a 69 5f ff [ ]*lam %a6,%a9,4095\(%r5\)
+ 2c4: e5 00 5f ff af ff [ ]*lasp 4095\(%r5\),4095\(%r10\)
+ 2ca: b3 13 00 69 [ ]*lcdbr %f6,%f9
+ 2ce: 23 69 [ ]*lcdr %f6,%f9
+ 2d0: b3 03 00 69 [ ]*lcebr %f6,%f9
+ 2d4: 33 69 [ ]*lcer %f6,%f9
+ 2d6: 13 69 [ ]*lcr %r6,%r9
+ 2d8: b7 69 5f ff [ ]*lctl %c6,%c9,4095\(%r5\)
+ 2dc: b3 43 00 69 [ ]*lcxbr %f6,%f9
+ 2e0: 68 60 5f ff [ ]*ld %f6,4095\(%r5\)
+ 2e4: ed 60 5f ff 00 04 [ ]*ldeb %f6,4095\(%r5\)
+ 2ea: b3 04 00 69 [ ]*ldebr %f6,%f9
+ 2ee: 28 69 [ ]*ldr %f6,%f9
+ 2f0: b3 45 00 69 [ ]*ldxbr %f6,%f9
+ 2f4: 78 60 5f ff [ ]*le %f6,4095\(%r5\)
+ 2f8: b3 44 00 69 [ ]*ledbr %f6,%f9
+ 2fc: 38 69 [ ]*ler %f6,%f9
+ 2fe: b3 46 00 69 [ ]*lexbr %f6,%f9
+ 302: b2 9d 5f ff [ ]*lfpc 4095\(%r5\)
+ 306: 48 60 5f ff [ ]*lh %r6,4095\(%r5\)
+ 30a: a7 68 80 01 [ ]*lhi %r6,-32767
+ 30e: 98 69 5f ff [ ]*lm %r6,%r9,4095\(%r5\)
+ 312: b3 11 00 69 [ ]*lndbr %f6,%f9
+ 316: 21 69 [ ]*lndr %f6,%f9
+ 318: b3 01 00 69 [ ]*lnebr %f6,%f9
+ 31c: 31 69 [ ]*lner %f6,%f9
+ 31e: 11 69 [ ]*lnr %r6,%r9
+ 320: b3 41 00 69 [ ]*lnxbr %f6,%f9
+ 324: b3 10 00 69 [ ]*lpdbr %f6,%f9
+ 328: 20 69 [ ]*lpdr %f6,%f9
+ 32a: b3 00 00 69 [ ]*lpebr %f6,%f9
+ 32e: 30 69 [ ]*lper %f6,%f9
+ 330: 10 69 [ ]*lpr %r6,%r9
+ 332: 82 00 5f ff [ ]*lpsw 4095\(%r5\)
+ 336: b3 40 00 69 [ ]*lpxbr %f6,%f9
+ 33a: 18 69 [ ]*lr %r6,%r9
+ 33c: b1 65 af ff [ ]*lra %r6,4095\(%r5,%r10\)
+ 340: 25 69 [ ]*lrdr %f6,%f9
+ 342: 35 69 [ ]*lrer %f6,%f9
+ 344: b3 12 00 69 [ ]*ltdbr %f6,%f9
+ 348: 22 69 [ ]*ltdr %f6,%f9
+ 34a: b3 02 00 69 [ ]*ltebr %f6,%f9
+ 34e: 32 69 [ ]*lter %f6,%f9
+ 350: 12 69 [ ]*ltr %r6,%r9
+ 352: b3 42 00 69 [ ]*ltxbr %f6,%f9
+ 356: b2 4b 00 69 [ ]*lura %r6,%r9
+ 35a: ed 65 af ff 00 05 [ ]*lxdb %f6,4095\(%r5,%r10\)
+ 360: b3 05 00 69 [ ]*lxdbr %f6,%f9
+ 364: ed 65 af ff 00 06 [ ]*lxeb %f6,4095\(%r5,%r10\)
+ 36a: b3 06 00 69 [ ]*lxebr %f6,%f9
+ 36e: 5c 65 af ff [ ]*m %r6,4095\(%r5,%r10\)
+ 372: ed 95 af ff 60 1e [ ]*madb %f6,%f9,4095\(%r5,%r10\)
+ 378: b3 1e 60 95 [ ]*madbr %f6,%f9,%f5
+ 37c: ed 95 af ff 60 0e [ ]*maeb %f6,%f9,4095\(%r5,%r10\)
+ 382: b3 0e 60 95 [ ]*maebr %f6,%f9,%f5
+ 386: af 06 5f ff [ ]*mc 4095\(%r5\),6
+ 38a: 6c 65 af ff [ ]*md %f6,4095\(%r5,%r10\)
+ 38e: ed 65 af ff 00 1c [ ]*mdb %f6,4095\(%r5,%r10\)
+ 394: b3 1c 00 69 [ ]*mdbr %f6,%f9
+ 398: ed 65 af ff 00 0c [ ]*mdeb %f6,4095\(%r5,%r10\)
+ 39e: b3 0c 00 69 [ ]*mdebr %f6,%f9
+ 3a2: 2c 69 [ ]*mdr %f6,%f9
+ 3a4: 7c 65 af ff [ ]*me %f6,4095\(%r5,%r10\)
+ 3a8: ed 65 af ff 00 17 [ ]*meeb %f6,4095\(%r5,%r10\)
+ 3ae: b3 17 00 69 [ ]*meebr %f6,%f9
+ 3b2: 3c 69 [ ]*mer %f6,%f9
+ 3b4: 4c 65 af ff [ ]*mh %r6,4095\(%r5,%r10\)
+ 3b8: a7 6c 80 01 [ ]*mhi %r6,-32767
+ 3bc: fc ff 5f ff af ff [ ]*mp 4095\(16,%r5\),4095\(16,%r10\)
+ 3c2: 1c 69 [ ]*mr %r6,%r9
+ 3c4: 71 65 af ff [ ]*ms %r6,4095\(%r5,%r10\)
+ 3c8: b2 32 5f ff [ ]*msch 4095\(%r5\)
+ 3cc: ed 95 af ff 60 1f [ ]*msdb %f6,%f9,4095\(%r5,%r10\)
+ 3d2: b3 1f 60 95 [ ]*msdbr %f6,%f9,%f5
+ 3d6: ed 95 af ff 60 0f [ ]*mseb %f6,%f9,4095\(%r5,%r10\)
+ 3dc: b3 0f 60 95 [ ]*msebr %f6,%f9,%f5
+ 3e0: b2 52 00 69 [ ]*msr %r6,%r9
+ 3e4: b2 47 00 60 [ ]*msta %r6
+ 3e8: d2 ff 5f ff af ff [ ]*mvc 4095\(256,%r5\),4095\(%r10\)
+ 3ee: e5 0f 5f ff af ff [ ]*mvcdk 4095\(%r5\),4095\(%r10\)
+ 3f4: e8 ff 5f ff af ff [ ]*mvcin 4095\(256,%r5\),4095\(%r10\)
+ 3fa: d9 69 5f ff af ff [ ]*mvck 4095\(%r6,%r5\),4095\(%r10\),%r9
+ 400: 0e 69 [ ]*mvcl %r6,%r9
+ 402: a8 69 00 0a [ ]*mvcle %r6,%r9,10
+ 406: da 69 5f ff af ff [ ]*mvcp 4095\(%r6,%r5\),4095\(%r10\),%r9
+ 40c: db 69 5f ff af ff [ ]*mvcs 4095\(%r6,%r5\),4095\(%r10\),%r9
+ 412: e5 0e 5f ff af ff [ ]*mvcsk 4095\(%r5\),4095\(%r10\)
+ 418: 92 ff 5f ff [ ]*mvi 4095\(%r5\),255
+ 41c: d1 ff 5f ff af ff [ ]*mvn 4095\(256,%r5\),4095\(%r10\)
+ 422: f1 ff 5f ff af ff [ ]*mvo 4095\(16,%r5\),4095\(16,%r10\)
+ 428: b2 54 00 69 [ ]*mvpg %r6,%r9
+ 42c: b2 55 00 69 [ ]*mvst %r6,%r9
+ 430: d3 ff 5f ff af ff [ ]*mvz 4095\(256,%r5\),4095\(%r10\)
+ 436: b3 4c 00 69 [ ]*mxbr %f6,%f9
+ 43a: 67 65 af ff [ ]*mxd %f6,4095\(%r5,%r10\)
+ 43e: ed 65 af ff 00 07 [ ]*mxdb %f6,4095\(%r5,%r10\)
+ 444: b3 07 00 69 [ ]*mxdbr %f6,%f9
+ 448: 27 69 [ ]*mxdr %f6,%f9
+ 44a: 26 69 [ ]*mxr %f6,%f9
+ 44c: 54 65 af ff [ ]*n %r6,4095\(%r5,%r10\)
+ 450: d4 ff 5f ff af ff [ ]*nc 4095\(256,%r5\),4095\(%r10\)
+ 456: 94 ff 5f ff [ ]*ni 4095\(%r5\),255
+ 45a: 47 05 af ff [ ]*bc 0,4095\(%r5,%r10\)
+ 45e: 07 06 [ ]*bcr 0,%r6
+ 460: 14 69 [ ]*nr %r6,%r9
+ 462: 56 65 af ff [ ]*o %r6,4095\(%r5,%r10\)
+ 466: d6 ff 5f ff af ff [ ]*oc 4095\(256,%r5\),4095\(%r10\)
+ 46c: 96 ff 5f ff [ ]*oi 4095\(%r5\),255
+ 470: 16 69 [ ]*or %r6,%r9
+ 472: f2 ff 5f ff af ff [ ]*pack 4095\(16,%r5\),4095\(16,%r10\)
+ 478: b2 48 00 00 [ ]*palb
+ 47c: b2 18 5f ff [ ]*pc 4095\(%r5\)
+ 480: ee 69 5f ff af ff [ ]*plo %r6,4095\(%r5\),%r9,4095\(%r10\)
+ 486: 01 01 [ ]*pr
+ 488: b2 28 00 69 [ ]*pt %r6,%r9
+ 48c: b2 0d 00 00 [ ]*ptlb
+ 490: b2 3b 00 00 [ ]*rchp
+ 494: b2 77 5f ff [ ]*rp 4095\(%r5\)
+ 498: b2 2a 00 69 [ ]*rrbe %r6,%r9
+ 49c: b2 38 00 00 [ ]*rsch
+ 4a0: 5b 65 af ff [ ]*s %r6,4095\(%r5,%r10\)
+ 4a4: b2 19 5f ff [ ]*sac 4095\(%r5\)
+ 4a8: b2 79 5f ff [ ]*sacf 4095\(%r5\)
+ 4ac: b2 37 00 00 [ ]*sal
+ 4b0: b2 4e 00 69 [ ]*sar %a6,%r9
+ 4b4: b2 3c 00 00 [ ]*schm
+ 4b8: b2 04 5f ff [ ]*sck 4095\(%r5\)
+ 4bc: b2 06 5f ff [ ]*sckc 4095\(%r5\)
+ 4c0: 01 07 [ ]*sckpf
+ 4c2: 6b 65 af ff [ ]*sd %f6,4095\(%r5,%r10\)
+ 4c6: ed 65 af ff 00 1b [ ]*sdb %f6,4095\(%r5,%r10\)
+ 4cc: b3 1b 00 69 [ ]*sdbr %f6,%f9
+ 4d0: 2b 69 [ ]*sdr %f6,%f9
+ 4d2: 7b 65 af ff [ ]*se %f6,4095\(%r5,%r10\)
+ 4d6: ed 65 af ff 00 0b [ ]*seb %f6,4095\(%r5,%r10\)
+ 4dc: b3 0b 00 69 [ ]*sebr %f6,%f9
+ 4e0: 3b 69 [ ]*ser %f6,%f9
+ 4e2: b3 84 00 69 [ ]*sfpc %r6,%r9
+ 4e6: 4b 65 af ff [ ]*sh %r6,4095\(%r5,%r10\)
+ 4ea: b2 14 5f ff [ ]*sie 4095\(%r5\)
+ 4ee: b2 74 5f ff [ ]*siga 4095\(%r5\)
+ 4f2: ae 69 5f ff [ ]*sigp %r6,%r9,4095\(%r5\)
+ 4f6: 5f 65 af ff [ ]*sl %r6,4095\(%r5,%r10\)
+ 4fa: 8b 60 5f ff [ ]*sla %r6,4095\(%r5\)
+ 4fe: 8f 60 5f ff [ ]*slda %r6,4095\(%r5\)
+ 502: 8d 60 5f ff [ ]*sldl %r6,4095\(%r5\)
+ 506: 89 60 5f ff [ ]*sll %r6,4095\(%r5\)
+ 50a: 1f 69 [ ]*slr %r6,%r9
+ 50c: fb ff 5f ff af ff [ ]*sp 4095\(16,%r5\),4095\(16,%r10\)
+ 512: b2 0a 5f ff [ ]*spka 4095\(%r5\)
+ 516: 04 60 [ ]*spm %r6
+ 518: b2 08 5f ff [ ]*spt 4095\(%r5\)
+ 51c: b2 10 5f ff [ ]*spx 4095\(%r5\)
+ 520: ed 65 af ff 00 15 [ ]*sqdb %f6,4095\(%r5,%r10\)
+ 526: b3 15 00 69 [ ]*sqdbr %f6,%f9
+ 52a: b2 44 00 60 [ ]*sqdr %f6
+ 52e: ed 65 af ff 00 14 [ ]*sqeb %f6,4095\(%r5,%r10\)
+ 534: b3 14 00 69 [ ]*sqebr %f6,%f9
+ 538: b2 45 00 60 [ ]*sqer %f6
+ 53c: b3 16 00 69 [ ]*sqxbr %f6,%f9
+ 540: 1b 69 [ ]*sr %r6,%r9
+ 542: 8a 60 5f ff [ ]*sra %r6,4095\(%r5\)
+ 546: 8e 60 5f ff [ ]*srda %r6,4095\(%r5\)
+ 54a: 8c 60 5f ff [ ]*srdl %r6,4095\(%r5\)
+ 54e: 88 60 5f ff [ ]*srl %r6,4095\(%r5\)
+ 552: b2 99 5f ff [ ]*srnm 4095\(%r5\)
+ 556: f0 fa 5f ff af ff [ ]*srp 4095\(16,%r5\),4095\(%r10\),10
+ 55c: b2 5e 00 69 [ ]*srst %r6,%r9
+ 560: b2 25 00 60 [ ]*ssar %r6
+ 564: b2 33 5f ff [ ]*ssch 4095\(%r5\)
+ 568: b2 2b 00 69 [ ]*sske %r6,%r9
+ 56c: 80 00 5f ff [ ]*ssm 4095\(%r5\)
+ 570: 50 65 af ff [ ]*st %r6,4095\(%r5,%r10\)
+ 574: 9b 69 5f ff [ ]*stam %a6,%a9,4095\(%r5\)
+ 578: b2 12 5f ff [ ]*stap 4095\(%r5\)
+ 57c: 42 65 af ff [ ]*stc %r6,4095\(%r5,%r10\)
+ 580: b2 05 5f ff [ ]*stck 4095\(%r5\)
+ 584: b2 07 5f ff [ ]*stckc 4095\(%r5\)
+ 588: be 6f 5f ff [ ]*stcm %r6,15,4095\(%r5\)
+ 58c: b2 3a 5f ff [ ]*stcps 4095\(%r5\)
+ 590: b2 39 5f ff [ ]*stcrw 4095\(%r5\)
+ 594: b6 69 5f ff [ ]*stctl %c6,%c9,4095\(%r5\)
+ 598: 60 65 af ff [ ]*std %f6,4095\(%r5,%r10\)
+ 59c: 70 65 af ff [ ]*ste %f6,4095\(%r5,%r10\)
+ 5a0: b2 9c 5f ff [ ]*stfpc 4095\(%r5\)
+ 5a4: 40 65 af ff [ ]*sth %r6,4095\(%r5,%r10\)
+ 5a8: b2 02 5f ff [ ]*stidp 4095\(%r5\)
+ 5ac: 90 69 5f ff [ ]*stm %r6,%r9,4095\(%r5\)
+ 5b0: ac ff 5f ff [ ]*stnsm 4095\(%r5\),255
+ 5b4: ad ff 5f ff [ ]*stosm 4095\(%r5\),255
+ 5b8: b2 09 5f ff [ ]*stpt 4095\(%r5\)
+ 5bc: b2 11 5f ff [ ]*stpx 4095\(%r5\)
+ 5c0: b2 34 5f ff [ ]*stsch 4095\(%r5\)
+ 5c4: b2 7d 5f ff [ ]*stsi 4095\(%r5\)
+ 5c8: b2 46 00 69 [ ]*stura %r6,%r9
+ 5cc: 7f 65 af ff [ ]*su %f6,4095\(%r5,%r10\)
+ 5d0: 3f 69 [ ]*sur %f6,%f9
+ 5d2: 0a ff [ ]*svc 255
+ 5d4: 6f 65 af ff [ ]*sw %f6,4095\(%r5,%r10\)
+ 5d8: 2f 69 [ ]*swr %f6,%f9
+ 5da: b3 4b 00 69 [ ]*sxbr %f6,%f9
+ 5de: 37 69 [ ]*sxr %f6,%f9
+ 5e0: b2 4c 00 69 [ ]*tar %a6,%r9
+ 5e4: b2 2c 00 06 [ ]*tb %r6
+ 5e8: ed 65 af ff 00 11 [ ]*tcdb %f6,4095\(%r5,%r10\)
+ 5ee: ed 65 af ff 00 10 [ ]*tceb %f6,4095\(%r5,%r10\)
+ 5f4: ed 65 af ff 00 12 [ ]*tcxb %f6,4095\(%r5,%r10\)
+ 5fa: 91 ff 5f ff [ ]*tm 4095\(%r5\),255
+ 5fe: a7 60 ff ff [ ]*tmh %r6,65535
+ 602: a7 61 ff ff [ ]*tml %r6,65535
+ 606: b2 36 5f ff [ ]*tpi 4095\(%r5\)
+ 60a: e5 01 5f ff af ff [ ]*tprot 4095\(%r5\),4095\(%r10\)
+ 610: dc ff 5f ff af ff [ ]*tr 4095\(256,%r5\),4095\(%r10\)
+ 616: 99 69 5f ff [ ]*trace %r6,%r9,4095\(%r5\)
+ 61a: 01 ff [ ]*trap2
+ 61c: b2 ff 5f ff [ ]*trap4 4095\(%r5\)
+ 620: dd ff 5f ff af ff [ ]*trt 4095\(256,%r5\),4095\(%r10\)
+ 626: 93 00 5f ff [ ]*ts 4095\(%r5\)
+ 62a: b2 35 5f ff [ ]*tsch 4095\(%r5\)
+ 62e: f3 ff 5f ff af ff [ ]*unpk 4095\(16,%r5\),4095\(16,%r10\)
+ 634: 01 02 [ ]*upt
+ 636: 57 65 af ff [ ]*x %r6,4095\(%r5,%r10\)
+ 63a: d7 ff 5f ff af ff [ ]*xc 4095\(256,%r5\),4095\(%r10\)
+ 640: 97 ff 5f ff [ ]*xi 4095\(%r5\),255
+ 644: 17 69 [ ]*xr %r6,%r9
+ 646: f8 ff 5f ff af ff [ ]*zap 4095\(16,%r5\),4095\(16,%r10\)
diff -urN src/gas/testsuite/gas/s390/opcode.s src-s390/gas/testsuite/gas/s390/opcode.s
--- src/gas/testsuite/gas/s390/opcode.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,419 @@
+.text
+foo:
+ a %r6,4095(%r5,%r10)
+ ad %f6,4095(%r5,%r10)
+ adb %f6,4095(%r5,%r10)
+ adbr %f6,%f9
+ adr %f6,%f9
+ ae %f6,4095(%r5,%r10)
+ aeb %f6,4095(%r5,%r10)
+ aebr %f6,%f9
+ aer %f6,%f9
+ ah %r6,4095(%r5,%r10)
+ ahi %r6,-32767
+ al %r6,4095(%r5,%r10)
+ alr %r6,%r9
+ ap 4095(6,%r5),4095(9,%r10)
+ ar %r6,%r9
+ au %f6,4095(%r5,%r10)
+ aur %f6,%f9
+ aw %f6,4095(%r5,%r10)
+ awr %f6,%f9
+ axbr %f6,%f9
+ axr %f6,%f9
+ b 4095(%r5,%r10)
+ bakr %r6,%r9
+ bal %r6,4095(%r5,%r10)
+ balr %r6,%r9
+ bas %r6,4095(%r5,%r10)
+ basr %r6,%r9
+ bassm %r6,%r9
+ bc 6,4095(%r5,%r10)
+ bcr 6,%r9
+ bct %r6,4095(%r5,%r10)
+ bctr %r6,%r9
+ be 4095(%r5,%r10)
+ ber %r9
+ bh 4095(%r5,%r10)
+ bhe 4095(%r5,%r10)
+ bher %r9
+ bhr %r9
+ bl 4095(%r5,%r10)
+ ble 4095(%r5,%r10)
+ bler %r9
+ blh 4095(%r5,%r10)
+ blhr %r9
+ blr %r9
+ bm 4095(%r5,%r10)
+ bmr %r9
+ bne 4095(%r5,%r10)
+ bner %r9
+ bnh 4095(%r5,%r10)
+ bnhe 4095(%r5,%r10)
+ bnher %r9
+ bnhr %r9
+ bnl 4095(%r5,%r10)
+ bnle 4095(%r5,%r10)
+ bnler %r9
+ bnlh 4095(%r5,%r10)
+ bnlhr %r9
+ bnlr %r9
+ bnm 4095(%r5,%r10)
+ bnmr %r9
+ bno 4095(%r5,%r10)
+ bnor %r9
+ bnp 4095(%r5,%r10)
+ bnpr %r9
+ bnz 4095(%r5,%r10)
+ bnzr %r9
+ bo 4095(%r5,%r10)
+ bor %r9
+ bp 4095(%r5,%r10)
+ bpr %r9
+ br %r9
+ bras %r9,.
+ brc 6,.
+ brct 6,.
+ brxh %r6,%r9,.
+ brxle %r6,%r9,.
+ bsa %r6,%r9
+ bsg %r6,%r9
+ bsm %r6,%r9
+ bxh %r6,%r9,4095(%r5)
+ bxle %r6,%r9,4095(%r5)
+ bz 4095(%r5,%r10)
+ bzr %r9
+ c %r6,4095(%r5,%r10)
+ cd %f6,4095(%r5,%r10)
+ cdb %f6,4095(%r5,%r10)
+ cdbr %f6,%f9
+ cdfbr %r6,%f9
+ cdr %f6,%f9
+ cds %r6,%r9,4095(%r5)
+ ce %f6,4095(%r5,%r10)
+ ceb %f6,4095(%r5,%r10)
+ cebr %f6,%f9
+ cefbr %r6,%f9
+ cer %f6,%f9
+ cfc 4095(%r5)
+ cfdbr %f6,5,%r9
+ cfebr %f6,5,%r9
+ cfxbr %f6,5,%r9
+ ch %r6,4095(%r5,%r10)
+ chi %r6,-32767
+ cksm %r6,%r9
+ cl %r6,4095(%r5,%r10)
+ clc 4095(256,%r5),4095(%r10)
+ clcl %r6,%r9
+ clcle %r6,%r9,10
+ cli 4095(%r5),255
+ clm %r6,10,4095(%r5)
+ clr %r6,%r9
+ clst %r6,%r9
+ cmpsc %r6,%r9
+ cp 4095(6,%r5),4095(9,%r10)
+ cpya %a6,%a9
+ cr %r6,%r9
+ cs %r6,%r9,4095(%r5)
+ csch
+ csp %r6,%r9
+ cuse %r6,%r9
+ cutfu %r6,%r9
+ cuutf %r6,%r9
+ cvb %r6,4095(%r5,%r10)
+ cvd %r6,4095(%r5,%r10)
+ cxbr %f6,%f9
+ cxfbr %r6,%f9
+ d %r6,4095(%r5,%r10)
+ dd %f6,4095(%r5,%r10)
+ ddb %f6,4095(%r5,%r10)
+ ddbr %f6,%f9
+ ddr %f6,%f9
+ de %f6,4095(%r5,%r10)
+ deb %f6,4095(%r5,%r10)
+ debr %f6,%f9
+ der %f6,%f9
+ diag %r6,%r9,4095(%r5)
+ didbr %f6,%r9,%r5,10
+ diebr %f6,%r9,%r5,10
+ dp 4095(6,%r5),4095(9,%r10)
+ dr %r6,%r9
+ dxbr %f6,%f9
+ dxr %f6
+ ear %r6,%a9
+ ed 4095(256,%r5),4095(%r10)
+ edmk 4095(256,%r5),4095(%r10)
+ efpc %r6,%r9
+ epar %r6
+ ereg %r6,%r9
+ esar %r6
+ esta %r6,%r9
+ ex %r6,4095(%r5)
+ fidbr %r6,5,%r9
+ fiebr %r6,5,%r9
+ fixbr %r6,5,%r9
+ hdr %f6,%f9
+ her %f6,%f9
+ hsch
+ iac %r6
+ ic %r6,4095(%r5,%r10)
+ icm %r6,10,4095(%r5)
+ ipk
+ ipm %r6
+ ipte %r6,%r9
+ iske %r6,%r9
+ ivsk %r6,%r9
+ j .
+ je .
+ jh .
+ jhe .
+ jl .
+ jle .
+ jlh .
+ jm .
+ jne .
+ jnhe .
+ jnl .
+ jnle .
+ jnlh .
+ jnm .
+ jno .
+ jnp .
+ jnz .
+ jo .
+ jp .
+ jz .
+ kdb %f6,4095(%r5,%r10)
+ kdbr %f6,%f9
+ keb %f6,4095(%r5,%r10)
+ kebr %f6,%f9
+ kxbr %f6,%f9
+ l %r6,4095(%r5,%r10)
+ la %r6,4095(%r5,%r10)
+ lae %r6,4095(%r5,%r10)
+ lam %a6,%a9,4095(%r5)
+ lasp 4095(%r5),4095(%r10)
+ lcdbr %f6,%f9
+ lcdr %f6,%f9
+ lcebr %f6,%f9
+ lcer %f6,%f9
+ lcr %r6,%r9
+ lctl %c6,%c9,4095(%r5)
+ lcxbr %f6,%f9
+ ld %f6,4095(%r5)
+ ldeb %f6,4095(%r5)
+ ldebr %f6,%f9
+ ldr %f6,%f9
+ ldxbr %f6,%f9
+ le %f6,4095(%r5)
+ ledbr %f6,%f9
+ ler %f6,%f9
+ lexbr %f6,%f9
+ lfpc 4095(%r5)
+ lh %r6,4095(%r5)
+ lhi %r6,-32767
+ lm %r6,%r9,4095(%r5)
+ lndbr %f6,%f9
+ lndr %f6,%f9
+ lnebr %f6,%f9
+ lner %f6,%f9
+ lnr %r6,%r9
+ lnxbr %f6,%f9
+ lpdbr %f6,%f9
+ lpdr %f6,%f9
+ lpebr %f6,%f9
+ lper %f6,%f9
+ lpr %r6,%r9
+ lpsw 4095(%r5)
+ lpxbr %f6,%f9
+ lr %r6,%r9
+ lra %r6,4095(%r5,%r10)
+ lrdr %f6,%f9
+ lrer %f6,%f9
+ ltdbr %f6,%f9
+ ltdr %f6,%f9
+ ltebr %f6,%f9
+ lter %f6,%f9
+ ltr %r6,%r9
+ ltxbr %f6,%f9
+ lura %r6,%r9
+ lxdb %f6,4095(%r5,%r10)
+ lxdbr %f6,%f9
+ lxeb %f6,4095(%r5,%r10)
+ lxebr %f6,%f9
+ m %r6,4095(%r5,%r10)
+ madb %f6,%f9,4095(%r5,%r10)
+ madbr %f6,%f9,%f5
+ maeb %f6,%f9,4095(%r5,%r10)
+ maebr %f6,%f9,%f5
+ mc 4095(%r5),6
+ md %f6,4095(%r5,%r10)
+ mdb %f6,4095(%f5,%f10)
+ mdbr %f6,%f9
+ mdeb %f6,4095(%f5,%f10)
+ mdebr %f6,%f9
+ mdr %f6,%f9
+ me %f6,4095(%r5,%r10)
+ meeb %f6,4095(%r5,%r10)
+ meebr %f6,%f9
+ mer %f6,%f9
+ mh %r6,4095(%r5,%r10)
+ mhi %r6,-32767
+ mp 4095(16,%r5),4095(16,%r10)
+ mr %r6,%r9
+ ms %r6,4095(%r5,%r10)
+ msch 4095(%r5)
+ msdb %f6,%f9,4095(%r5,%r10)
+ msdbr %f6,%f9,%f5
+ mseb %f6,%f9,4095(%r5,%r10)
+ msebr %f6,%f9,%f5
+ msr %r6,%r9
+ msta %r6
+ mvc 4095(256,%r5),4095(%r10)
+ mvcdk 4095(%r5),4095(%r10)
+ mvcin 4095(256,%r5),4095(%r10)
+ mvck 4095(%r6,%r5),4095(%r10),%r9
+ mvcl %r6,%r9
+ mvcle %r6,%r9,10
+ mvcp 4095(%r6,%r5),4095(%r10),%r9
+ mvcs 4095(%r6,%r5),4095(%r10),%r9
+ mvcsk 4095(%r5),4095(%r10)
+ mvi 4095(%r5),255
+ mvn 4095(256,%r5),4095(%r10)
+ mvo 4095(16,%r5),4095(16,%r10)
+ mvpg %r6,%r9
+ mvst %r6,%r9
+ mvz 4095(256,%r5),4095(%r10)
+ mxbr %f6,%f9
+ mxd %f6,4095(%r5,%r10)
+ mxdb %f6,4095(%r5,%r10)
+ mxdbr %f6,%f9
+ mxdr %r6,%r9
+ mxr %r6,%r9
+ n %r6,4095(%r5,%r10)
+ nc 4095(256,%r5),4095(%r10)
+ ni 4095(%r5),255
+ nop 4095(%r5,%r10)
+ nopr %r6
+ nr %r6,%r9
+ o %r6,4095(%r5,%r10)
+ oc 4095(256,%r5),4095(%r10)
+ oi 4095(%r5),255
+ or %r6,%r9
+ pack 4095(16,%r5),4095(16,%r10)
+ palb
+ pc 4095(%r5)
+ plo %r6,4095(%r5),%r9,4095(%r10)
+ pr
+ pt %r6,%r9
+ ptlb
+ rchp
+ rp 4095(%r5)
+ rrbe %r6,%r9
+ rsch
+ s %r6,4095(%r5,%r10)
+ sac 4095(%r5)
+ sacf 4095(%r5)
+ sal
+ sar %a6,%r9
+ schm
+ sck 4095(%r5)
+ sckc 4095(%r5)
+ sckpf
+ sd %f6,4095(%r5,%r10)
+ sdb %f6,4095(%r5,%r10)
+ sdbr %f6,%f9
+ sdr %f6,%f9
+ se %f6,4095(%r5,%r10)
+ seb %f6,4095(%r5,%r10)
+ sebr %f6,%f9
+ ser %r6,%r9
+ sfpc %r6,%r9
+ sh %r6,4095(%r5,%r10)
+ sie 4095(%r5)
+ siga 4095(%r5)
+ sigp %r6,%r9,4095(%r5)
+ sl %r6,4095(%r5,%r10)
+ sla %r6,4095(%r5)
+ slda %r6,4095(%r5)
+ sldl %r6,4095(%r5)
+ sll %r6,4095(%r5)
+ slr %r6,%r9
+ sp 4095(16,%r5),4095(16,%r10)
+ spka 4095(%r5)
+ spm %r6
+ spt 4095(%r5)
+ spx 4095(%r5)
+ sqdb %f6,4095(%r5,%r10)
+ sqdbr %f6,%f9
+ sqdr %f6
+ sqeb %f6,4095(%r5,%r10)
+ sqebr %f6,%f9
+ sqer %f6
+ sqxbr %f6,%f9
+ sr %r6,%r9
+ sra %r6,4095(%r5)
+ srda %r6,4095(%r5)
+ srdl %r6,4095(%r5)
+ srl %r6,4095(%r5)
+ srnm 4095(%r5)
+ srp 4095(16,%r5),4095(%r10),10
+ srst %r6,%r9
+ ssar %r6
+ ssch 4095(%r5)
+ sske %r6,%r9
+ ssm 4095(%r5)
+ st %r6,4095(%r5,%r10)
+ stam %a6,%a9,4095(%r5)
+ stap 4095(%r5)
+ stc %r6,4095(%r5,%r10)
+ stck 4095(%r5)
+ stckc 4095(%r5)
+ stcm %r6,15,4095(%r5)
+ stcps 4095(%r5)
+ stcrw 4095(%r5)
+ stctl %c6,%c9,4095(%r5)
+ std %f6,4095(%r5,%r10)
+ ste %f6,4095(%r5,%r10)
+ stfpc 4095(%r5)
+ sth %r6,4095(%r5,%r10)
+ stidp 4095(%r5)
+ stm %r6,%r9,4095(%r5)
+ stnsm 4095(%r5),255
+ stosm 4095(%r5),255
+ stpt 4095(%r5)
+ stpx 4095(%r5)
+ stsch 4095(%r5)
+ stsi 4095(%r5)
+ stura %r6,%r9
+ su %f6,4095(%r5,%r10)
+ sur %r6,%r9
+ svc 255
+ sw %f6,4095(%r5,%r10)
+ swr %f6,%f9
+ sxbr %f6,%f9
+ sxr %r6,%r9
+ tar %a6,%r9
+ tb %r6
+ tcdb %f6,4095(%r5,%r10)
+ tceb %f6,4095(%r5,%r10)
+ tcxb %f6,4095(%r5,%r10)
+ tm 4095(%r5),255
+ tmh %r6,65535
+ tml %r6,65535
+ tpi 4095(%r5)
+ tprot 4095(%r5),4095(%r10)
+ tr 4095(256,%r5),4095(%r10)
+ trace %r6,%r9,4095(%r5)
+ trap2
+ trap4 4095(%r5)
+ trt 4095(256,%r5),4095(%r10)
+ ts 4095(%r5)
+ tsch 4095(%r5)
+ unpk 4095(16,%r5),4095(16,%r10)
+ upt
+ x %r6,4095(%r5,%r10)
+ xc 4095(256,%r5),4095(%r10)
+ xi 4095(%r5),255
+ xr %r6,%r9
+ zap 4095(16,%r5),4095(16,%r10)
diff -urN src/gas/testsuite/gas/s390/opcode64.d src-s390/gas/testsuite/gas/s390/opcode64.d
--- src/gas/testsuite/gas/s390/opcode64.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode64.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,211 @@
+#name: s390x opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: e3 95 af ff 00 08 [ ]*ag %r9,4095\(%r5,%r10\)
+ 6: e3 95 af ff 00 18 [ ]*agf %r9,4095\(%r5,%r10\)
+ c: b9 18 00 96 [ ]*agfr %r9,%r6
+ 10: a7 9b 80 01 [ ]*aghi %r9,-32767
+ 14: b9 08 00 96 [ ]*agr %r9,%r6
+ 18: e3 95 af ff 00 98 [ ]*alc %r9,4095\(%r5,%r10\)
+ 1e: e3 95 af ff 00 88 [ ]*alcg %r9,4095\(%r5,%r10\)
+ 24: b9 88 00 96 [ ]*alcgr %r9,%r6
+ 28: b9 98 00 96 [ ]*alcr %r9,%r6
+ 2c: e3 95 af ff 00 0a [ ]*alg %r9,4095\(%r5,%r10\)
+ 32: e3 95 af ff 00 1a [ ]*algf %r9,4095\(%r5,%r10\)
+ 38: b9 1a 00 96 [ ]*algfr %r9,%r6
+ 3c: b9 0a 00 96 [ ]*algr %r9,%r6
+ 40: e3 65 af ff 00 46 [ ]*bctg %r6,4095\(%r5,%r10\)
+ 46: b9 46 00 69 [ ]*bctgr %r6,%r9
+ 4a: c0 65 00 00 00 00 [ ]*brasl %r6,4a <foo\+0x4a>
+ 50: c0 f4 00 00 00 00 [ ]*jg 50 <foo\+0x50>
+ 56: a7 67 00 00 [ ]*brctg %r6,56 <foo\+0x56>
+ 5a: ec 69 00 00 00 44 [ ]*brxhg %r6,%r9,5a <foo\+0x5a>
+ 60: ec 69 00 00 00 45 [ ]*brxlg %r6,%r9,60 <foo\+0x60>
+ 66: eb 69 5f ff 00 44 [ ]*bxhg %r6,%r9,4095\(%r5\)
+ 6c: eb 69 5f ff 00 45 [ ]*bxleg %r6,%r9,4095\(%r5\)
+ 72: b3 a5 00 69 [ ]*cdgbr %r6,%r9
+ 76: b3 c5 00 69 [ ]*cdgr %r6,%r9
+ 7a: eb 69 5f ff 00 3e [ ]*cdsg %r6,%r9,4095\(%r5\)
+ 80: b3 a4 00 69 [ ]*cegbr %r6,%r9
+ 84: b3 c4 00 69 [ ]*cegr %r6,%r9
+ 88: e3 65 af ff 00 20 [ ]*cg %r6,4095\(%r5,%r10\)
+ 8e: b3 a9 f0 69 [ ]*cgdbr %f6,15,%r9
+ 92: b3 c9 90 65 [ ]*cgdr %f6,9,%r5
+ 96: b3 a8 f0 69 [ ]*cgebr %f6,15,%r9
+ 9a: b3 c8 90 65 [ ]*cger %f6,9,%r5
+ 9e: e3 65 af ff 00 30 [ ]*cgf %r6,4095\(%r5,%r10\)
+ a4: b9 30 00 69 [ ]*cgfr %r6,%r9
+ a8: a7 6f 80 01 [ ]*cghi %r6,-32767
+ ac: b9 20 00 69 [ ]*cgr %r6,%r9
+ b0: b3 aa f0 69 [ ]*cgxbr %f6,15,%r9
+ b4: b3 ca 90 65 [ ]*cgxr %f6,9,%r5
+ b8: e3 65 af ff 00 21 [ ]*clg %r6,4095\(%r5,%r10\)
+ be: e3 65 af ff 00 31 [ ]*clgf %r6,4095\(%r5,%r10\)
+ c4: b9 31 00 69 [ ]*clgfr %r6,%r9
+ c8: b9 21 00 69 [ ]*clgr %r6,%r9
+ cc: eb 6a 5f ff 00 20 [ ]*clmh %r6,10,4095\(%r5\)
+ d2: eb 69 5f ff 00 30 [ ]*csg %r6,%r9,4095\(%r5\)
+ d8: e3 65 af ff 00 0e [ ]*cvbg %r6,4095\(%r5,%r10\)
+ de: e3 65 af ff 00 2e [ ]*cvdg %r6,4095\(%r5,%r10\)
+ e4: b3 a6 00 69 [ ]*cxgbr %r6,%r9
+ e8: b3 c6 00 69 [ ]*cxgr %r6,%r9
+ ec: e3 65 af ff 00 97 [ ]*dl %r6,4095\(%r5,%r10\)
+ f2: e3 65 af ff 00 87 [ ]*dlg %r6,4095\(%r5,%r10\)
+ f8: b9 87 00 69 [ ]*dlgr %r6,%r9
+ fc: b9 97 00 69 [ ]*dlr %r6,%r9
+ 100: e3 65 af ff 00 0d [ ]*dsg %r6,4095\(%r5,%r10\)
+ 106: e3 65 af ff 00 1d [ ]*dsgf %r6,4095\(%r5,%r10\)
+ 10c: b9 1d 00 69 [ ]*dsgfr %r6,%r9
+ 110: b9 0d 00 69 [ ]*dsgr %r6,%r9
+ 114: b9 8d 00 69 [ ]*epsw %r6,%r9
+ 118: b9 0e 00 69 [ ]*eregg %r6,%r9
+ 11c: b9 9d 00 60 [ ]*esea %r6
+ 120: eb 6a 5f ff 00 80 [ ]*icmh %r6,10,4095\(%r5\)
+ 126: a5 60 ff ff [ ]*iihh %r6,65535
+ 12a: a5 61 ff ff [ ]*iihl %r6,65535
+ 12e: a5 62 ff ff [ ]*iilh %r6,65535
+ 132: a5 63 ff ff [ ]*iill %r6,65535
+ 136: c0 f4 00 00 00 00 [ ]*jg 136 <foo\+0x136>
+ 13c: c0 84 00 00 00 00 [ ]*jge 13c <foo\+0x13c>
+ 142: c0 24 00 00 00 00 [ ]*jgh 142 <foo\+0x142>
+ 148: c0 a4 00 00 00 00 [ ]*jghe 148 <foo\+0x148>
+ 14e: c0 44 00 00 00 00 [ ]*jgl 14e <foo\+0x14e>
+ 154: c0 c4 00 00 00 00 [ ]*jgle 154 <foo\+0x154>
+ 15a: c0 64 00 00 00 00 [ ]*jglh 15a <foo\+0x15a>
+ 160: c0 44 00 00 00 00 [ ]*jgl 160 <foo\+0x160>
+ 166: c0 74 00 00 00 00 [ ]*jgne 166 <foo\+0x166>
+ 16c: c0 d4 00 00 00 00 [ ]*jgnh 16c <foo\+0x16c>
+ 172: c0 54 00 00 00 00 [ ]*jgnhe 172 <foo\+0x172>
+ 178: c0 b4 00 00 00 00 [ ]*jgnl 178 <foo\+0x178>
+ 17e: c0 34 00 00 00 00 [ ]*jgnle 17e <foo\+0x17e>
+ 184: c0 94 00 00 00 00 [ ]*jgnlh 184 <foo\+0x184>
+ 18a: c0 b4 00 00 00 00 [ ]*jgnl 18a <foo\+0x18a>
+ 190: c0 e4 00 00 00 00 [ ]*jgno 190 <foo\+0x190>
+ 196: c0 d4 00 00 00 00 [ ]*jgnh 196 <foo\+0x196>
+ 19c: c0 74 00 00 00 00 [ ]*jgne 19c <foo\+0x19c>
+ 1a2: c0 14 00 00 00 00 [ ]*jgo 1a2 <foo\+0x1a2>
+ 1a8: c0 24 00 00 00 00 [ ]*jgh 1a8 <foo\+0x1a8>
+ 1ae: c0 84 00 00 00 00 [ ]*jge 1ae <foo\+0x1ae>
+ 1b4: c0 60 00 00 00 00 [ ]*larl %r6,1b4 <foo\+0x1b4>
+ 1ba: b9 13 00 69 [ ]*lcgfr %r6,%r9
+ 1be: b9 03 00 69 [ ]*lcgr %r6,%r9
+ 1c2: eb 69 5f ff 00 2f [ ]*lctlg %r6,%r9,4095\(%r5\)
+ 1c8: e3 65 af ff 00 04 [ ]*lg %r6,4095\(%r5,%r10\)
+ 1ce: e3 65 af ff 00 14 [ ]*lgf %r6,4095\(%r5,%r10\)
+ 1d4: b9 14 00 69 [ ]*lgfr %r6,%r9
+ 1d8: e3 65 af ff 00 15 [ ]*lgh %r6,4095\(%r5,%r10\)
+ 1de: a7 69 80 01 [ ]*lghi %r6,-32767
+ 1e2: b9 04 00 69 [ ]*lgr %r6,%r9
+ 1e6: e3 65 af ff 00 90 [ ]*llgc %r6,4095\(%r5,%r10\)
+ 1ec: e3 65 af ff 00 16 [ ]*llgf %r6,4095\(%r5,%r10\)
+ 1f2: b9 16 00 69 [ ]*llgfr %r6,%r9
+ 1f6: e3 65 af ff 00 91 [ ]*llgh %r6,4095\(%r5,%r10\)
+ 1fc: e3 65 af ff 00 17 [ ]*llgt %r6,4095\(%r5,%r10\)
+ 202: b9 17 00 69 [ ]*llgtr %r6,%r9
+ 206: a5 6c ff ff [ ]*llihh %r6,65535
+ 20a: a5 6d ff ff [ ]*llihl %r6,65535
+ 20e: a5 6e ff ff [ ]*llilh %r6,65535
+ 212: a5 6f ff ff [ ]*llill %r6,65535
+ 216: ef 69 5f ff af ff [ ]*lmd %r6,%r9,4095\(%r5\),4095\(%r10\)
+ 21c: eb 69 5f ff 00 04 [ ]*lmg %r6,%r9,4095\(%r5\)
+ 222: eb 69 5f ff 00 96 [ ]*lmh %r6,%r9,4095\(%r5\)
+ 228: b9 11 00 69 [ ]*lngfr %r6,%r9
+ 22c: b9 01 00 69 [ ]*lngr %r6,%r9
+ 230: b9 10 00 69 [ ]*lpgfr %r6,%r9
+ 234: b9 00 00 69 [ ]*lpgr %r6,%r9
+ 238: e3 65 af ff 00 8f [ ]*lpq %r6,4095\(%r5,%r10\)
+ 23e: b2 b2 5f ff [ ]*lpswe 4095\(%r5\)
+ 242: e3 65 af ff 00 03 [ ]*lrag %r6,4095\(%r5,%r10\)
+ 248: e3 65 af ff 00 1e [ ]*lrv %r6,4095\(%r5,%r10\)
+ 24e: e3 65 af ff 00 0f [ ]*lrvg %r6,4095\(%r5,%r10\)
+ 254: b9 0f 00 69 [ ]*lrvgr %r6,%r9
+ 258: e3 65 af ff 00 1f [ ]*lrvh %r6,4095\(%r5,%r10\)
+ 25e: b9 1f 00 69 [ ]*lrvr %r6,%r9
+ 262: b9 12 00 69 [ ]*ltgfr %r6,%r9
+ 266: b9 02 00 69 [ ]*ltgr %r6,%r9
+ 26a: b9 05 00 69 [ ]*lurag %r6,%r9
+ 26e: b3 75 00 60 [ ]*lzdr %r6
+ 272: b3 74 00 60 [ ]*lzer %r6
+ 276: b3 76 00 60 [ ]*lzxr %r6
+ 27a: a7 6d 80 01 [ ]*mghi %r6,-32767
+ 27e: e3 65 af ff 00 96 [ ]*ml %r6,4095\(%r5,%r10\)
+ 284: e3 65 af ff 00 86 [ ]*mlg %r6,4095\(%r5,%r10\)
+ 28a: b9 86 00 69 [ ]*mlgr %r6,%r9
+ 28e: b9 96 00 69 [ ]*mlr %r6,%r9
+ 292: e3 65 af ff 00 0c [ ]*msg %r6,4095\(%r5,%r10\)
+ 298: e3 65 af ff 00 1c [ ]*msgf %r6,4095\(%r5,%r10\)
+ 29e: b9 1c 00 69 [ ]*msgfr %r6,%r9
+ 2a2: b9 0c 00 69 [ ]*msgr %r6,%r9
+ 2a6: eb 69 5f ff 00 8e [ ]*mvclu %r6,%r9,4095\(%r5\)
+ 2ac: e3 65 af ff 00 80 [ ]*ng %r6,4095\(%r5,%r10\)
+ 2b2: b9 80 00 69 [ ]*ngr %r6,%r9
+ 2b6: a5 64 ff ff [ ]*nihh %r6,65535
+ 2ba: a5 65 ff ff [ ]*nihl %r6,65535
+ 2be: a5 66 ff ff [ ]*nilh %r6,65535
+ 2c2: a5 67 ff ff [ ]*nill %r6,65535
+ 2c6: e3 65 af ff 00 81 [ ]*og %r6,4095\(%r5,%r10\)
+ 2cc: b9 81 00 69 [ ]*ogr %r6,%r9
+ 2d0: a5 68 ff ff [ ]*oihh %r6,65535
+ 2d4: a5 69 ff ff [ ]*oihl %r6,65535
+ 2d8: a5 6a ff ff [ ]*oilh %r6,65535
+ 2dc: a5 6b ff ff [ ]*oill %r6,65535
+ 2e0: e9 ff 5f ff af ff [ ]*pka 4095\(256,%r5\),4095\(%r10\)
+ 2e6: e1 ff 5f ff af ff [ ]*pku 4095\(256,%r5\),4095\(%r10\)
+ 2ec: eb 69 5f ff 00 1d [ ]*rll %r6,%r9,4095\(%r5\)
+ 2f2: eb 69 5f ff 00 1c [ ]*rllg %r6,%r9,4095\(%r5\)
+ 2f8: 01 0c [ ]*sam24
+ 2fa: 01 0d [ ]*sam31
+ 2fc: 01 0e [ ]*sam64
+ 2fe: e3 65 af ff 00 09 [ ]*sg %r6,4095\(%r5,%r10\)
+ 304: e3 65 af ff 00 19 [ ]*sgf %r6,4095\(%r5,%r10\)
+ 30a: b9 19 00 69 [ ]*sgfr %r6,%r9
+ 30e: b9 09 00 69 [ ]*sgr %r6,%r9
+ 312: eb 69 5f ff 00 0b [ ]*slag %r6,%r9,4095\(%r5\)
+ 318: e3 65 af ff 00 99 [ ]*slb %r6,4095\(%r5,%r10\)
+ 31e: e3 65 af ff 00 89 [ ]*slbg %r6,4095\(%r5,%r10\)
+ 324: b9 89 00 69 [ ]*slbgr %r6,%r9
+ 328: b9 99 00 69 [ ]*slbr %r6,%r9
+ 32c: e3 65 af ff 00 0b [ ]*slg %r6,4095\(%r5,%r10\)
+ 332: e3 65 af ff 00 1b [ ]*slgf %r6,4095\(%r5,%r10\)
+ 338: b9 1b 00 69 [ ]*slgfr %r6,%r9
+ 33c: b9 0b 00 69 [ ]*slgr %r6,%r9
+ 340: eb 69 5f ff 00 0d [ ]*sllg %r6,%r9,4095\(%r5\)
+ 346: eb 69 5f ff 00 0a [ ]*srag %r6,%r9,4095\(%r5\)
+ 34c: eb 69 5f ff 00 0c [ ]*srlg %r6,%r9,4095\(%r5\)
+ 352: b2 78 5f ff [ ]*stcke 4095\(%r5\)
+ 356: eb 6a 5f ff 00 2c [ ]*stcmh %r6,10,4095\(%r5\)
+ 35c: eb 69 5f ff 00 25 [ ]*stctg %r6,%r9,4095\(%r5\)
+ 362: b2 b1 5f ff [ ]*stfl 4095\(%r5\)
+ 366: e3 65 af ff 00 24 [ ]*stg %r6,4095\(%r5,%r10\)
+ 36c: eb 69 5f ff 00 24 [ ]*stmg %r6,%r9,4095\(%r5\)
+ 372: eb 69 5f ff 00 26 [ ]*stmh %r6,%r9,4095\(%r5\)
+ 378: e3 65 af ff 00 8e [ ]*stpq %r6,4095\(%r5,%r10\)
+ 37e: e5 00 5f ff 9f ff [ ]*lasp 4095\(%r5\),4095\(%r9\)
+ 384: e3 65 af ff 00 3e [ ]*strv %r6,4095\(%r5,%r10\)
+ 38a: e3 65 af ff 00 2f [ ]*strvg %r6,4095\(%r5,%r10\)
+ 390: e3 65 af ff 00 3f [ ]*strvh %r6,4095\(%r5,%r10\)
+ 396: b9 25 00 69 [ ]*sturg %r6,%r9
+ 39a: 01 0b [ ]*tam
+ 39c: b3 51 f0 69 [ ]*tbdr %f6,15,%f9
+ 3a0: b3 50 f0 69 [ ]*tbedr %f6,15,%f9
+ 3a4: b3 58 00 69 [ ]*thder %r6,%r9
+ 3a8: b3 59 00 69 [ ]*thdr %r6,%r9
+ 3ac: a7 62 ff ff [ ]*tmhh %r6,65535
+ 3b0: a7 63 ff ff [ ]*tmhl %r6,65535
+ 3b4: a7 60 ff ff [ ]*tmh %r6,65535
+ 3b8: a7 61 ff ff [ ]*tml %r6,65535
+ 3bc: eb 69 5f ff 00 0f [ ]*tracg %r6,%r9,4095\(%r5\)
+ 3c2: b2 a5 00 69 [ ]*tre %r6,%r9
+ 3c6: b9 93 00 69 [ ]*troo %r6,%r9
+ 3ca: b9 92 00 69 [ ]*trot %r6,%r9
+ 3ce: b9 91 00 69 [ ]*trto %r6,%r9
+ 3d2: b9 90 00 69 [ ]*trtt %r6,%r9
+ 3d6: ea ff 5f ff af ff [ ]*unpka 4095\(256,%r5\),4095\(%r10\)
+ 3dc: e2 ff 5f ff af ff [ ]*unpku 4095\(256,%r5\),4095\(%r10\)
+ 3e2: e3 65 af ff 00 82 [ ]*xg %r6,4095\(%r5,%r10\)
+ 3e8: b9 82 00 69 [ ]*xgr %r6,%r9
diff -urN src/gas/testsuite/gas/s390/opcode64.s src-s390/gas/testsuite/gas/s390/opcode64.s
--- src/gas/testsuite/gas/s390/opcode64.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/opcode64.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,205 @@
+.text
+foo:
+ ag %r9,4095(%r5,%r10)
+ agf %r9,4095(%r5,%r10)
+ agfr %r9,%r6
+ aghi %r9,-32767
+ agr %r9,%r6
+ alc %r9,4095(%r5,%r10)
+ alcg %r9,4095(%r5,%r10)
+ alcgr %r9,%r6
+ alcr %r9,%r6
+ alg %r9,4095(%r5,%r10)
+ algf %r9,4095(%r5,%r10)
+ algfr %r9,%r6
+ algr %r9,%r6
+ bctg %r6,4095(%r5,%r10)
+ bctgr %r6,%r9
+ brasl %r6,.
+ brcl 15,.
+ brctg %r6,.
+ brxhg %r6,%r9,.
+ brxlg %r6,%r9,.
+ bxhg %r6,%r9,4095(%r5)
+ bxleg %r6,%r9,4095(%r5)
+ cdgbr %r6,%r9
+ cdgr %r6,%r9
+ cdsg %r6,%r9,4095(%r5)
+ cegbr %r6,%r9
+ cegr %r6,%r9
+ cg %r6,4095(%r5,%r10)
+ cgdbr %r6,15,%r9
+ cgdr %f6,9,%r5
+ cgebr %r6,15,%r9
+ cger %f6,9,%r5
+ cgf %r6,4095(%r5,%r10)
+ cgfr %r6,%r9
+ cghi %r6,-32767
+ cgr %r6,%r9
+ cgxbr %r6,15,%r9
+ cgxr %f6,9,%r5
+ clg %r6,4095(%r5,%r10)
+ clgf %r6,4095(%r5,%r10)
+ clgfr %r6,%r9
+ clgr %r6,%r9
+ clmh %r6,10,4095(%r5)
+ csg %r6,%r9,4095(%r5)
+ cvbg %r6,4095(%r5,%r10)
+ cvdg %r6,4095(%r5,%r10)
+ cxgbr %r6,%r9
+ cxgr %r6,%r9
+ dl %r6,4095(%r5,%r10)
+ dlg %r6,4095(%r5,%r10)
+ dlgr %r6,%r9
+ dlr %r6,%r9
+ dsg %r6,4095(%r5,%r10)
+ dsgf %r6,4095(%r5,%r10)
+ dsgfr %r6,%r9
+ dsgr %r6,%r9
+ epsw %r6,%r9
+ eregg %r6,%r9
+ esea %r6
+ icmh %r6,10,4095(%r5)
+ iihh %r6,65535
+ iihl %r6,65535
+ iilh %r6,65535
+ iill %r6,65535
+ jg .
+ jge .
+ jgh .
+ jghe .
+ jgl .
+ jgle .
+ jglh .
+ jgm .
+ jgne .
+ jgnh .
+ jgnhe .
+ jgnl .
+ jgnle .
+ jgnlh .
+ jgnm .
+ jgno .
+ jgnp .
+ jgnz .
+ jgo .
+ jgp .
+ jgz .
+ larl %r6,.
+ lcgfr %r6,%r9
+ lcgr %r6,%r9
+ lctlg %r6,%r9,4095(%r5)
+ lg %r6,4095(%r5,%r10)
+ lgf %r6,4095(%r5,%r10)
+ lgfr %r6,%r9
+ lgh %r6,4095(%r5,%r10)
+ lghi %r6,-32767
+ lgr %r6,%r9
+ llgc %r6,4095(%r5,%r10)
+ llgf %r6,4095(%r5,%r10)
+ llgfr %r6,%r9
+ llgh %r6,4095(%r5,%r10)
+ llgt %r6,4095(%r5,%r10)
+ llgtr %r6,%r9
+ llihh %r6,65535
+ llihl %r6,65535
+ llilh %r6,65535
+ llill %r6,65535
+ lmd %r6,%r9,4095(%r5),4095(%r10)
+ lmg %r6,%r9,4095(%r5)
+ lmh %r6,%r9,4095(%r5)
+ lngfr %r6,%r9
+ lngr %r6,%r9
+ lpgfr %r6,%r9
+ lpgr %r6,%r9
+ lpq %r6,4095(%r5,%r10)
+ lpswe 4095(%r5)
+ lrag %r6,4095(%r5,%r10)
+ lrv %r6,4095(%r5,%r10)
+ lrvg %r6,4095(%r5,%r10)
+ lrvgr %r6,%r9
+ lrvh %r6,4095(%r5,%r10)
+ lrvr %r6,%r9
+ ltgfr %r6,%r9
+ ltgr %r6,%r9
+ lurag %r6,%r9
+ lzdr %r6
+ lzer %r6
+ lzxr %r6
+ mghi %r6,-32767
+ ml %r6,4095(%r5,%r10)
+ mlg %r6,4095(%r5,%r10)
+ mlgr %r6,%r9
+ mlr %r6,%r9
+ msg %r6,4095(%r5,%r10)
+ msgf %r6,4095(%r5,%r10)
+ msgfr %r6,%r9
+ msgr %r6,%r9
+ mvclu %r6,%r9,4095(%r5)
+ ng %r6,4095(%r5,%r10)
+ ngr %r6,%r9
+ nihh %r6,65535
+ nihl %r6,65535
+ nilh %r6,65535
+ nill %r6,65535
+ og %r6,4095(%r5,%r10)
+ ogr %r6,%r9
+ oihh %r6,65535
+ oihl %r6,65535
+ oilh %r6,65535
+ oill %r6,65535
+ pka 4095(256,%r5),4095(%r10)
+ pku 4095(256,%r5),4095(%r10)
+ rll %r6,%r9,4095(%r5)
+ rllg %r6,%r9,4095(%r5)
+ sam24
+ sam31
+ sam64
+ sg %r6,4095(%r5,%r10)
+ sgf %r6,4095(%r5,%r10)
+ sgfr %r6,%r9
+ sgr %r6,%r9
+ slag %r6,%r9,4095(%r5)
+ slb %r6,4095(%r5,%r10)
+ slbg %r6,4095(%r5,%r10)
+ slbgr %r6,%r9
+ slbr %r6,%r9
+ slg %r6,4095(%r5,%r10)
+ slgf %r6,4095(%r5,%r10)
+ slgfr %r6,%r9
+ slgr %r6,%r9
+ sllg %r6,%r9,4095(%r5)
+ srag %r6,%r9,4095(%r5)
+ srlg %r6,%r9,4095(%r5)
+ stcke 4095(%r5)
+ stcmh %r6,10,4095(%r5)
+ stctg %r6,%r9,4095(%r5)
+ stfl 4095(%r5)
+ stg %r6,4095(%r5,%r10)
+ stmg %r6,%r9,4095(%r5)
+ stmh %r6,%r9,4095(%r5)
+ stpq %r6,4095(%r5,%r10)
+ strag 4095(%r5),4095(%r9)
+ strv %r6,4095(%r5,%r10)
+ strvg %r6,4095(%r5,%r10)
+ strvh %r6,4095(%r5,%r10)
+ sturg %r6,%r9
+ tam
+ tbdr %r6,15,%r9
+ tbedr %r6,15,%r9
+ thder %r6,%r9
+ thdr %r6,%r9
+ tmhh %r6,65535
+ tmhl %r6,65535
+ tmlh %r6,65535
+ tmll %r6,65535
+ tracg %r6,%r9,4095(%r5)
+ tre %r6,%r9
+ troo %r6,%r9
+ trot %r6,%r9
+ trto %r6,%r9
+ trtt %r6,%r9
+ unpka 4095(256,%r5),4095(%r10)
+ unpku 4095(256,%r5),4095(%r10)
+ xg %r6,4095(%r5,%r10)
+ xgr %r6,%r9
diff -urN src/gas/testsuite/gas/s390/operands.d src-s390/gas/testsuite/gas/s390/operands.d
--- src/gas/testsuite/gas/s390/operands.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,23 @@
+#name: s390 operands
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: 01 01 [ ]*pr
+ 2: a7 1a 80 01 [ ]*ahi %r1,-32767
+ 6: 18 12 [ ]*lr %r1,%r2
+ 8: b2 5e 00 12 [ ]*srst %r1,%r2
+ c: b3 5b 93 12 [ ]*didbr %f1,%f9,%f2,3
+ 10: ba 12 40 03 [ ]*cs %r1,%r2,3\(%r4\)
+ 14: 84 12 00 00 [ ]*brxh %r1,%r2,14 <foo\+0x14>
+[ ]*16: R_390_PC16DBL test_rsi\+0x2
+ 18: 58 13 40 02 [ ]*l %r1,2\(%r3,%r4\)
+ 1c: ed 10 30 02 00 1a [ ]*adb %f1,2\(%r3\)
+ 22: ed 24 50 03 10 1e [ ]*madb %f1,%f2,3\(%r4,%r5\)
+ 28: b2 33 20 01 [ ]*ssch 1\(%r2\)
+ 2c: 92 03 20 01 [ ]*mvi 1\(%r2\),3
+ 30: d2 26 30 01 50 04 [ ]*mvc 1\(39,%r3\),4\(%r5\)
+ 36: e5 01 20 01 40 03 [ ]*tprot 1\(%r2\),3\(%r4\)
diff -urN src/gas/testsuite/gas/s390/operands.s src-s390/gas/testsuite/gas/s390/operands.s
--- src/gas/testsuite/gas/s390/operands.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,16 @@
+.text
+foo:
+ .insn e,0x0101
+ .insn ri,0xa70a0000,%r1,-32767
+ .insn rr,0x1800,%r1,%r2
+ .insn rre,0xb25e0000,%r1,%r2
+ .insn rrf,0xb35b0000,%f1,%f2,9,%f3
+ .insn rs,0xba000000,%r1,%r2,3(%r4)
+ .insn rsi,0x84000000,%r1,%r2,test_rsi
+ .insn rx,0x58000000,%r1,2(%r3,%r4)
+ .insn rxe,0xed000000001a,%f1,2(%r3)
+ .insn rxf,0xed000000001e,%f1,%f2,3(%r4,%r5)
+ .insn s,0xb2330000,1(%r2)
+ .insn si,0x92000000,1(%r2),3
+ .insn ss,0xd20000000000,1(2,%r3),4(%r5),6
+ .insn sse,0xe50100000000,1(%r2),3(%r4)
diff -urN src/gas/testsuite/gas/s390/operands64.d src-s390/gas/testsuite/gas/s390/operands64.d
--- src/gas/testsuite/gas/s390/operands64.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands64.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,14 @@
+#name: s390x operands
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: ec 12 00 00 00 45 [ ]*brxlg %r1,%r2,0 <foo>
+[ ]*2: R_390_PC16DBL test_rie\+0x2
+ 6: c0 e5 00 00 00 00 [ ]*brasl %r14,6 <foo\+0x6>
+[ ]*8: R_390_PC32DBL test_ril\+0x2
+ c: eb 12 40 03 00 0d [ ]*sllg %r1,%r2,3\(%r4\)
+ 12: 07 07 [ ]*bcr 0,%r7
diff -urN src/gas/testsuite/gas/s390/operands64.s src-s390/gas/testsuite/gas/s390/operands64.s
--- src/gas/testsuite/gas/s390/operands64.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/operands64.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,6 @@
+.text
+foo:
+ .insn rie,0xec0000000045,%r1,%r2,test_rie
+ .insn ril,0xc00500000000,%r14,test_ril
+ .insn rse,0xeb000000000d,%r1,%r2,3(%r4)
+
diff -urN src/gas/testsuite/gas/s390/reloc.d src-s390/gas/testsuite/gas/s390/reloc.d
--- src/gas/testsuite/gas/s390/reloc.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,31 @@
+#name: s390 reloc
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: d2 00 10 00 20 00 [ ]*mvc 0\(1,%r1\),0\(%r2\)
+[ ]*1: R_390_8 test_R_390_8
+ 6: 58 01 20 00 [ ]*l %r0,0\(%r1,%r2\)
+[ ]*8: R_390_12 test_R_390_12
+ a: a7 08 00 00 [ ]*lhi %r0,0
+[ ]*c: R_390_16 test_R_390_16
+[ ]*...
+[ ]*e: R_390_32 test_R_390_32
+[ ]*12: R_390_PC32 test_R_390_PC32\+0x12
+ 16: 58 01 20 00 [ ]*l %r0,0\(%r1,%r2\)
+[ ]*18: R_390_GOT12 test_R_390_GOT12
+[ ]*...
+[ ]*1a: R_390_GOT32 test_R_390_GOT32
+[ ]*1e: R_390_PLT32 test_R_390_PLT32
+ 22: a7 08 00 00 [ ]*lhi %r0,0
+[ ]*24: R_390_GOT16 test_R_390_GOT16
+ 26: a7 08 00 00 [ ]*lhi %r0,0
+[ ]*28: R_390_16 test_R_390_PC16\+0x26
+ 2a: a7 e5 00 00 [ ]*bras %r14,2a <foo\+0x2a>
+[ ]*2c: R_390_PC16DBL test_R_390_PC16DBL\+0x2
+ 2e: a7 e5 00 00 [ ]*bras %r14,2e <foo\+0x2e>
+[ ]*30: R_390_PC16DBL test_R_390_PLT16DBL\+0x2
+ 32: 07 07 [ ]*bcr 0,%r7
diff -urN src/gas/testsuite/gas/s390/reloc.s src-s390/gas/testsuite/gas/s390/reloc.s
--- src/gas/testsuite/gas/s390/reloc.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,14 @@
+.text
+foo:
+ mvc 0(test_R_390_8,%r1),0(%r2)
+ l %r0,test_R_390_12(%r1,%r2)
+ lhi %r0,test_R_390_16
+ .long test_R_390_32
+ .long test_R_390_PC32-foo
+ l %r0,test_R_390_GOT12@GOT(%r1,%r2)
+ .long test_R_390_GOT32@GOT
+ .long test_R_390_PLT32@PLT
+ lhi %r0,test_R_390_GOT16@GOT
+ lhi %r0,test_R_390_PC16-foo
+ bras %r14,test_R_390_PC16DBL
+ bras %r14,test_R_390_PLT16DBL
diff -urN src/gas/testsuite/gas/s390/reloc64.d src-s390/gas/testsuite/gas/s390/reloc64.d
--- src/gas/testsuite/gas/s390/reloc64.d Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc64.d Fri Sep 14 18:47:22 2001
@@ -0,0 +1,20 @@
+#name: s390x reloc
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+ 0: c0 e5 00 00 00 00 [ ]*brasl %r14,0 <foo>
+[ ]*2: R_390_PC32DBL test_R_390_PC32DBL\+0x2
+ 6: c0 e5 00 00 00 00 [ ]*brasl %r14,6 <foo\+0x6>
+[ ]*8: R_390_PC32DBL test_R_390_PLT32DBL\+0x2
+[ ]*...
+[ ]*c: R_390_64 test_R_390_64
+[ ]*14: R_390_PC64 test_R_390_PC64\+0x14
+[ ]*1c: R_390_GOT64 test_R_390_GOT64
+[ ]*24: R_390_PLT64 test_R_390_PLT64
+ 2c: c0 10 00 00 00 00 [ ]*larl %r1,2c <foo\+0x2c>
+[ ]*2e: R_390_GOTENT test_R_390_GOTENT\+0x2
+ 32: 07 07 [ ]*bcr 0,%r7
diff -urN src/gas/testsuite/gas/s390/reloc64.s src-s390/gas/testsuite/gas/s390/reloc64.s
--- src/gas/testsuite/gas/s390/reloc64.s Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/reloc64.s Fri Sep 14 18:47:22 2001
@@ -0,0 +1,9 @@
+.text
+foo:
+ brasl %r14,test_R_390_PC32DBL
+ brasl %r14,test_R_390_PLT32DBL
+ .quad test_R_390_64
+ .quad test_R_390_PC64-foo
+ .quad test_R_390_GOT64@GOT
+ .quad test_R_390_PLT64@PLT
+ larl %r1,test_R_390_GOTENT@GOT
diff -urN src/gas/testsuite/gas/s390/s390.exp src-s390/gas/testsuite/gas/s390/s390.exp
--- src/gas/testsuite/gas/s390/s390.exp Thu Jan 1 01:00:00 1970
+++ src-s390/gas/testsuite/gas/s390/s390.exp Fri Sep 14 18:47:22 2001
@@ -0,0 +1,35 @@
+#
+# s390/s390x tests
+#
+proc run_list_test { name opts } {
+ global srcdir subdir
+ set testname "s390 $name"
+ set file $srcdir/$subdir/$name
+ gas_run ${name}.s $opts ">&dump.out"
+ if { [regexp_diff "dump.out" "${file}.l"] } then {
+ fail $testname
+ verbose "output is [file_contents "dump.out"]" 2
+ exit
+ return
+ }
+ pass $testname
+}
+
+if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then {
+
+ run_dump_test "opcode"
+ run_dump_test "reloc"
+ run_dump_test "operands"
+
+# # PIC is only supported on ELF targets.
+# if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"] ) } then {
+# run_dump_test "s390pic"
+# }
+}
+
+if [istarget "s390x-*-*"] then {
+
+ run_dump_test "opcode64"
+ run_dump_test "reloc64"
+ run_dump_test "operands64"
+}
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2001-09-18 8:55 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2001-09-17 5:33 Automatic opcode table generation and gas test cases for s/390 Martin Schwidefsky
-- strict thread matches above, loose matches on Subject: below --
2001-09-14 15:21 Martin Schwidefsky
2001-09-14 15:38 ` DJ Delorie
2001-09-18 8:55 ` Nick Clifton
2001-09-14 13:10 Martin Schwidefsky
2001-09-14 13:18 ` DJ Delorie
2001-09-14 12:46 Martin Schwidefsky
2001-09-14 12:50 ` DJ Delorie
2001-09-14 12:31 Martin Schwidefsky
2001-09-14 12:34 ` DJ Delorie
2001-09-14 12:24 Martin Schwidefsky
2001-09-14 12:27 ` DJ Delorie
2001-09-14 12:06 Martin Schwidefsky
2001-09-14 12:14 ` DJ Delorie
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