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From: "Cui, Lili" <lili.cui@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
	"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 1/3] x86: Split REX/REX2 old registers judgment.
Date: Wed, 22 May 2024 06:11:32 +0000	[thread overview]
Message-ID: <PH0PR11MB5593A8858D8DBBCAFC272E479EEB2@PH0PR11MB5593.namprd11.prod.outlook.com> (raw)
In-Reply-To: <21daf000-afb4-4b25-a711-8a302140429e@suse.com>

> On 22.05.2024 03:33, Cui, Lili wrote:
> >
> >> On 20.05.2024 08:22, Cui, Lili wrote:
> >>> --- a/gas/config/tc-i386.c
> >>> +++ b/gas/config/tc-i386.c
> >>> @@ -4303,22 +4303,20 @@ static void establish_rex (void)
> >>>    /* Respect a user-specified REX prefix.  */
> >>>    i.rex |= i.prefix[REX_PREFIX] & REX_OPCODE;
> >>>
> >>> -  /* For 8 bit registers we need an empty rex prefix.  Also if the
> >>> -     instruction already has a prefix, we need to convert old
> >>> -     registers to new ones.  */
> >>> -
> >>> -  if ((i.types[first].bitfield.class == Reg && i.types[first].bitfield.byte
> >>> -       && ((i.op[first].regs->reg_flags & RegRex64) != 0 || i.rex != 0
> >>> -	   || i.rex2 != 0))
> >>> -      || (i.types[last].bitfield.class == Reg && i.types[last].bitfield.byte
> >>> -	  && ((i.op[last].regs->reg_flags & RegRex64) != 0 || i.rex != 0
> >>> -	      || i.rex2 != 0)))
> >>> -    {
> >>> -      unsigned int x;
> >>> -
> >>> -      if (!is_apx_rex2_encoding () && !is_any_vex_encoding(&i.tm))
> >>> -	i.rex |= REX_OPCODE;
> >>> -      for (x = first; x <= last; x++)
> >>> +  /* For 8 bit registers without a prefix, we need an empty rex
> >>> + prefix.  */
> >>
> >> As you're touching this comment, can you please also correct it? It's
> >> not all 8- bit registers which are affected here (as expressed by the
> >> RegRex64 checks).
> >>
> > Done.
> >
> >>> +  if (((i.types[first].bitfield.class == Reg && i.types[first].bitfield.byte
> >>> +	&& ((i.op[first].regs->reg_flags & RegRex64) != 0 ))
> >>
> >> Nit: Please parenthesize this line and ...
> >>
> >>> +       || (i.types[last].bitfield.class == Reg && i.types[last].bitfield.byte
> >>> +	   && (i.op[last].regs->reg_flags & RegRex64) != 0 ))
> >>
> >> ... this one the same way, preferably like the latter. Also please
> >> omit the blanks before the closing parentheses.
> >>
> > Done.
> >
> >>> +      && !is_apx_rex2_encoding () && !is_any_vex_encoding (&i.tm)
> >>> + &&
> >>> + !i.rex)
> >>
> >> Is the !i.rex part needed? It wasn't there before. If it's needed, it
> >> would imo better come ahead of the APX/VEX checks.
> >>
> > Yes, I added it because there is already i.rex and we don't need to overwrite
> it. And I will put it ahead of the APX/VEX checks.
> 
> I don't think conditionals should be added in such cases. Resulting code will do
> better without the extra conditional branch, when the update is really benign
> in the case where (here) i.rex is already set. See, btw, your own response to a
> pretty similar question of mine:
> https://sourceware.org/pipermail/binutils/2024-May/134157.html
> 
Yes, they are the similar issues. Since I just pushed it to the trunk, I'll create a patch to remove it.

Lili.

  reply	other threads:[~2024-05-22  6:11 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-20  6:21 [PATCH 0/3] Support APX zero-upper Cui, Lili
2024-05-20  6:22 ` [PATCH 1/3] x86: Split REX/REX2 old registers judgment Cui, Lili
2024-05-21 12:18   ` Jan Beulich
2024-05-22  1:33     ` Cui, Lili
2024-05-22  5:49       ` Jan Beulich
2024-05-22  6:11         ` Cui, Lili [this message]
2024-05-22  6:22           ` Jan Beulich
2024-05-20  6:22 ` [PATCH 2/3] Add check for 8-bit old registers in EVEX format Cui, Lili
2024-05-21 12:24   ` Jan Beulich
2024-05-22  2:20     ` Cui, Lili
2024-05-20  6:22 ` [PATCH 3/3] Support APX zero-upper Cui, Lili
2024-05-22  6:21   ` Jan Beulich
2024-05-22  8:05     ` Cui, Lili

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