C6x patch: Fix SPKERNEL assembly/disassembly

C6x patch: Fix SPKERNEL assembly/disassembly

[Bernd Schmidt]

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We don't handle the encoding of the SPKERNEL instruction correctly.  The
fstg field grows from the high bits, i.e. it is bit-reversed.  The
following patch corrects it in gas and objdump.

I've verified the two new tests against the TI assembler/disassembler.
Interestingly all the existing ones pass before and after the patch.


Bernd


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gas/
	* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field
	in SPKERNEL instructions.

opcodes/
	* tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
	in SPKERNEL instructions.

gas/testsuite/
	* gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests.
	* gas/tic6x/insns-c674x-sploop.s: Likewise.

	
	
Index: gas/testsuite/gas/tic6x/insns-c674x-sploop.d
===================================================================
--- gas/testsuite/gas/tic6x/insns-c674x-sploop.d	(revision 301803)
+++ gas/testsuite/gas/tic6x/insns-c674x-sploop.d	(working copy)
@@ -77,4 +77,10 @@ Disassembly of section \.text:
 [0-9a-f]+[048c] <[^>]*> 06838000[ \t]+sploop 14
 [0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
 [0-9a-f]+[048c] <[^>]*> 0f434000[ \t]+spkernel 3,13
+[0-9a-f]+[048c] <[^>]*> 00038000[ \t]+sploop 1
+[0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 01034000[ \t]+spkernel 8,0
+[0-9a-f]+[048c] <[^>]*> 00838000[ \t]+sploop 2
 [0-9a-f]+[048c] <[^>]*> 00000000[ \t]+nop 1
+[0-9a-f]+[048c] <[^>]*> 06034000[ \t]+spkernel 6,0
+[ \t]*\.\.\.
Index: gas/testsuite/gas/tic6x/insns-c674x-sploop.s
===================================================================
--- gas/testsuite/gas/tic6x/insns-c674x-sploop.s	(revision 301803)
+++ gas/testsuite/gas/tic6x/insns-c674x-sploop.s	(working copy)
@@ -77,3 +77,9 @@ f:
 	sploop 14
 	nop
 	spkernel 3,13
+	sploop 1
+	nop
+	spkernel 8,0
+	sploop 2
+	nop
+	spkernel 6,0
Index: gas/config/tc-tic6x.c
===================================================================
--- gas/config/tc-tic6x.c	(revision 301803)
+++ gas/config/tc-tic6x.c	(working copy)
@@ -2503,6 +2503,7 @@ tic6x_try_encode (tic6x_opcode_id id, ti
 
 	  if (opct->variable_fields[fld].coding_method == tic6x_coding_fstg)
 	    {
+	      int i, t;
 	      if (operands[opno].value.exp.X_add_number < 0
 		  || (operands[opno].value.exp.X_add_number
 		      >= (1 << (fldd->width - fcyc_bits))))
@@ -2513,7 +2514,13 @@ tic6x_try_encode (tic6x_opcode_id id, ti
 		  *ok = FALSE;
 		  return 0;
 		}
-	      value = operands[opno].value.exp.X_add_number << fcyc_bits;
+	      value = operands[opno].value.exp.X_add_number;
+	      for (t = 0, i = fcyc_bits; i < fldd->width; i++)
+		{
+		  t = (t << 1) | (value & 1);
+		  value >>= 1;
+		}
+	      value = t << fcyc_bits;
 	    }
 	  else
 	    {
Index: opcodes/tic6x-dis.c
===================================================================
--- opcodes/tic6x-dis.c	(revision 301803)
+++ opcodes/tic6x-dis.c	(working copy)
@@ -882,9 +882,11 @@ print_insn_tic6x (bfd_vma addr, struct d
 		    abort ();
 		  if (enc->coding_method == tic6x_coding_fstg)
 		    {
+		      int i, t;
+		      for (t = 0, i = fcyc_bits; i < 6; i++)
+			t = (t << 1) | ((fld_val >> i) & 1);
 		      operands_text[op_num] = TRUE;
-		      snprintf (operands[op_num], 24, "%u",
-				fld_val >> fcyc_bits);
+		      snprintf (operands[op_num], 24, "%u", t);
 		    }
 		  else
 		    {

Re: C6x patch: Fix SPKERNEL assembly/disassembly

[Joseph S. Myers]

On Wed, 6 Oct 2010, Bernd Schmidt wrote:

> We don't handle the encoding of the SPKERNEL instruction correctly.  The
> fstg field grows from the high bits, i.e. it is bit-reversed.  The
> following patch corrects it in gas and objdump.
> 
> I've verified the two new tests against the TI assembler/disassembler.
> Interestingly all the existing ones pass before and after the patch.

This is OK.  The reason that the existing tests pass (I did verify 
diassembly of all the positive tests with the TI disassembler when doing 
the original port, as a sanity check for mistakes in the encodings listed 
in the ISA manuals) is that what I was thinking of testing was the 
boundary cases of largest/smallest field values accepted, meaning that all 
those tests are of values with all fstg bits set, i.e. unaffected by the 
reversal (and I didn't notice the table in the manual showing the 
reversal).

-- 
Joseph S. Myers
joseph@codesourcery.com