* [PATCH 0/3] x86/APX: ZU support follow-up
@ 2024-05-29 8:06 Jan Beulich
2024-05-29 8:07 ` [PATCH 1/3] x86/APX: support extended SETcc form Jan Beulich
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Jan Beulich @ 2024-05-29 8:06 UTC (permalink / raw)
To: Binutils; +Cc: Lili Cui, H.J. Lu
1: support extended SETcc form
2: disassembler macro for condition code
3: convert ZU to operand constraint
Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/3] x86/APX: support extended SETcc form
2024-05-29 8:06 [PATCH 0/3] x86/APX: ZU support follow-up Jan Beulich
@ 2024-05-29 8:07 ` Jan Beulich
2024-05-30 8:18 ` Cui, Lili
2024-05-29 8:08 ` [PATCH 2/3] x86: disassembler macro for condition code Jan Beulich
2024-05-29 8:09 ` [PATCH 3/3] x86/APX: convert ZU to operand constraint Jan Beulich
2 siblings, 1 reply; 13+ messages in thread
From: Jan Beulich @ 2024-05-29 8:07 UTC (permalink / raw)
To: Binutils; +Cc: Lili Cui, H.J. Lu
As indicated during review, spelling/readability-wise
setz %eax
is easier than
setzuz %al
_and_ properly specifies the full register that's being modified. Permit
that form to be used, even if the spec writers are unwilling to formally
mention it.
While there also correct the non-ZU EVEX form: That ought to also permit
memory operands.
---
In principle SETZUcc ought to also permit for memory operands, for (as
per the spec) EVEX.ZU simply being ignored in that case. However, such
forms are rather meaningless, so I'm not convinced we really want to
permit that.
--- a/gas/testsuite/gas/i386/x86-64-apx-zu-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-zu-intel.d
@@ -42,6 +42,9 @@ Disassembly of section .text:
\s*[a-f0-9]+:\s*62 dc 7f 18 4f c1[ ]+setzug r25b
\s*[a-f0-9]+:\s*d5 91 9f c1[ ]+setg r25b
\s*[a-f0-9]+:\s*62 f4 7f 08 4f c0[ ]+\{evex\} setg al
+\s*[a-f0-9]+:\s*62 f4 7f 08 4f 00[ ]+\{evex\} setg (BYTE PTR )?\[rax\]
+\s*[a-f0-9]+:\s*62 f4 7f 18 4a c0[ ]+setzup al
+\s*[a-f0-9]+:\s*62 f4 ff 18 4b c0[ ]+setzunp al
\s*[a-f0-9]+:\s*62 f4 7d 18 6b c3 0a[ ]+imulzu ax,bx,0xa
\s*[a-f0-9]+:\s*67 62 f4 7d 18 6b 00 0a[ ]+imulzu ax,WORD PTR \[eax\],0xa
\s*[a-f0-9]+:\s*62 ec 7d 18 6b c1 0a[ ]+imulzu r16w,r17w,0xa
--- a/gas/testsuite/gas/i386/x86-64-apx-zu.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-zu.d
@@ -42,6 +42,9 @@ Disassembly of section .text:
\s*[a-f0-9]+:\s*62 dc 7f 18 4f c1[ ]+setzug %r25b
\s*[a-f0-9]+:\s*d5 91 9f c1[ ]+setg %r25b
\s*[a-f0-9]+:\s*62 f4 7f 08 4f c0[ ]+\{evex\} setg %al
+\s*[a-f0-9]+:\s*62 f4 7f 08 4f 00[ ]+\{evex\} setg \(%rax\)
+\s*[a-f0-9]+:\s*62 f4 7f 18 4a c0[ ]+setzup %al
+\s*[a-f0-9]+:\s*62 f4 ff 18 4b c0[ ]+setzunp %al
\s*[a-f0-9]+:\s*62 f4 7d 18 6b c3 0a[ ]+imulzu \$0xa,%bx,%ax
\s*[a-f0-9]+:\s*67 62 f4 7d 18 6b 00 0a[ ]+imulzu \$0xa,\(%eax\),%ax
\s*[a-f0-9]+:\s*62 ec 7d 18 6b c1 0a[ ]+imulzu \$0xa,%r17w,%r16w
--- a/gas/testsuite/gas/i386/x86-64-apx-zu.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-zu.s
@@ -36,6 +36,9 @@ _start:
setzug %r25b
setg %r25b
{evex} setg %al
+ {evex} setg (%rax)
+ setpe %eax
+ setpo %rax
.intel_syntax noprefix
imulzu ax,bx, 10
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -533,8 +533,11 @@ loopne, 0xe0, x64, JumpByte|No_bSuf|No_w
// Set byte on flag instructions.
set<cc>, 0xf9<cc:opc>/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Unspecified|BaseIndex }
-set<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4, { Reg8 }
+set<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4, { Reg8|Unspecified|BaseIndex }
setzu<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4|ZU, { Reg8 }
+// As an extension, allow SETcc without the ZU infix, instead taking the full
+// register as operand.
+set<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|ZU, { Reg32|Reg64 }
// String manipulation.
cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/3] x86: disassembler macro for condition code
2024-05-29 8:06 [PATCH 0/3] x86/APX: ZU support follow-up Jan Beulich
2024-05-29 8:07 ` [PATCH 1/3] x86/APX: support extended SETcc form Jan Beulich
@ 2024-05-29 8:08 ` Jan Beulich
2024-05-30 5:52 ` Jiang, Haochen
2024-05-29 8:09 ` [PATCH 3/3] x86/APX: convert ZU to operand constraint Jan Beulich
2 siblings, 1 reply; 13+ messages in thread
From: Jan Beulich @ 2024-05-29 8:08 UTC (permalink / raw)
To: Binutils; +Cc: Lili Cui, H.J. Lu
Both CMPccXADD and APX'es {,CF}CMOVcc have almost identical entries
replicated 16 times each. Fold those to just one each by introducing a
%CC macro. (Note that the recording of ->condition_code in print_insn()
is merely for completeness for now; it's not used as long as only
VEX/EVEX encodings would consume it.)
This then also renders condition codes printed consistent across all
respective insns; CMPxxXADD had a number of outliers so far.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -160,6 +160,7 @@ struct instr_info
unsigned char rex2_payload;
bool need_modrm;
+ unsigned char condition_code;
unsigned char need_vex;
bool has_sib;
@@ -1199,22 +1200,7 @@ enum
PREFIX_EVEX_0F3A67,
PREFIX_EVEX_0F3AC2,
- PREFIX_EVEX_MAP4_40,
- PREFIX_EVEX_MAP4_41,
- PREFIX_EVEX_MAP4_42,
- PREFIX_EVEX_MAP4_43,
- PREFIX_EVEX_MAP4_44,
- PREFIX_EVEX_MAP4_45,
- PREFIX_EVEX_MAP4_46,
- PREFIX_EVEX_MAP4_47,
- PREFIX_EVEX_MAP4_48,
- PREFIX_EVEX_MAP4_49,
- PREFIX_EVEX_MAP4_4A,
- PREFIX_EVEX_MAP4_4B,
- PREFIX_EVEX_MAP4_4C,
- PREFIX_EVEX_MAP4_4D,
- PREFIX_EVEX_MAP4_4E,
- PREFIX_EVEX_MAP4_4F,
+ PREFIX_EVEX_MAP4_4x,
PREFIX_EVEX_MAP4_F0,
PREFIX_EVEX_MAP4_F1,
PREFIX_EVEX_MAP4_F2,
@@ -1315,22 +1301,7 @@ enum
X86_64_VEX_0F385C,
X86_64_VEX_0F385E,
X86_64_VEX_0F386C,
- X86_64_VEX_0F38E0,
- X86_64_VEX_0F38E1,
- X86_64_VEX_0F38E2,
- X86_64_VEX_0F38E3,
- X86_64_VEX_0F38E4,
- X86_64_VEX_0F38E5,
- X86_64_VEX_0F38E6,
- X86_64_VEX_0F38E7,
- X86_64_VEX_0F38E8,
- X86_64_VEX_0F38E9,
- X86_64_VEX_0F38EA,
- X86_64_VEX_0F38EB,
- X86_64_VEX_0F38EC,
- X86_64_VEX_0F38ED,
- X86_64_VEX_0F38EE,
- X86_64_VEX_0F38EF,
+ X86_64_VEX_0F38Ex,
X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
};
@@ -1816,6 +1787,7 @@ struct dis386 {
nothing otherwise; behave as 'P' in all other cases
2 upper case letter macros:
+ "CC" => print condition code
"XY" => print 'x' or 'y' if suffix_always is true or no register
operands and no broadcast.
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
@@ -4512,100 +4484,10 @@ static const struct dis386 x86_64_table[
{ VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
},
- /* X86_64_VEX_0F38E0 */
+ /* X86_64_VEX_0F38Ex */
{
{ Bad_Opcode },
- { "%XEcmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E1 */
- {
- { Bad_Opcode },
- { "%XEcmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E2 */
- {
- { Bad_Opcode },
- { "%XEcmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E3 */
- {
- { Bad_Opcode },
- { "%XEcmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E4 */
- {
- { Bad_Opcode },
- { "%XEcmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E5 */
- {
- { Bad_Opcode },
- { "%XEcmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E6 */
- {
- { Bad_Opcode },
- { "%XEcmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E7 */
- {
- { Bad_Opcode },
- { "%XEcmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E8 */
- {
- { Bad_Opcode },
- { "%XEcmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38E9 */
- {
- { Bad_Opcode },
- { "%XEcmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38EA */
- {
- { Bad_Opcode },
- { "%XEcmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38EB */
- {
- { Bad_Opcode },
- { "%XEcmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38EC */
- {
- { Bad_Opcode },
- { "%XEcmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38ED */
- {
- { Bad_Opcode },
- { "%XEcmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38EE */
- {
- { Bad_Opcode },
- { "%XEcmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
- },
-
- /* X86_64_VEX_0F38EF */
- {
- { Bad_Opcode },
- { "%XEcmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+ { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
},
/* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
@@ -6624,23 +6506,23 @@ static const struct dis386 vex_table[][2
{ "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
{ "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
/* e0 */
- { X86_64_TABLE (X86_64_VEX_0F38E0) },
- { X86_64_TABLE (X86_64_VEX_0F38E1) },
- { X86_64_TABLE (X86_64_VEX_0F38E2) },
- { X86_64_TABLE (X86_64_VEX_0F38E3) },
- { X86_64_TABLE (X86_64_VEX_0F38E4) },
- { X86_64_TABLE (X86_64_VEX_0F38E5) },
- { X86_64_TABLE (X86_64_VEX_0F38E6) },
- { X86_64_TABLE (X86_64_VEX_0F38E7) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
/* e8 */
- { X86_64_TABLE (X86_64_VEX_0F38E8) },
- { X86_64_TABLE (X86_64_VEX_0F38E9) },
- { X86_64_TABLE (X86_64_VEX_0F38EA) },
- { X86_64_TABLE (X86_64_VEX_0F38EB) },
- { X86_64_TABLE (X86_64_VEX_0F38EC) },
- { X86_64_TABLE (X86_64_VEX_0F38ED) },
- { X86_64_TABLE (X86_64_VEX_0F38EE) },
- { X86_64_TABLE (X86_64_VEX_0F38EF) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_TABLE (X86_64_VEX_0F38Ex) },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -9031,6 +8913,7 @@ get_valid_dis386 (const struct dis386 *d
ins->need_vex = 3;
ins->codep++;
vindex = *ins->codep++;
+ ins->condition_code = vindex & 0xf;
if (vex_table_index != VEX_MAP7)
dp = &vex_table[vex_table_index][vindex];
else if (vindex == 0xf8)
@@ -9199,6 +9082,7 @@ get_valid_dis386 (const struct dis386 *d
ins->codep++;
vindex = *ins->codep++;
+ ins->condition_code = vindex & 0xf;
if (vex_table_index != EVEX_MAP7)
dp = &evex_table[vex_table_index][vindex];
else if (vindex == 0xf8)
@@ -9591,6 +9475,7 @@ print_insn (bfd_vma pc, disassemble_info
dp = &dis386[*ins.codep];
ins.need_modrm = onebyte_has_modrm[*ins.codep];
}
+ ins.condition_code = *ins.codep & 0xf;
ins.codep++;
/* Save sizeflag for printing the extra ins.prefixes later before updating
@@ -10505,6 +10390,16 @@ putop (instr_info *ins, const char *in_t
abort ();
break;
case 'C':
+ if (l == 1 && last[0] == 'C')
+ {
+ /* Condition code (taken from the map-0 Jcc entries). */
+ for (const char *q = dis386[0x70 | ins->condition_code].name + 1;
+ ISLOWER(*q); ++q)
+ *ins->obufp++ = *q;
+ break;
+ }
+ if (l)
+ abort ();
if (ins->intel_syntax && !alt)
break;
if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -545,23 +545,23 @@ static const struct dis386 evex_table[][
{ "%XEvaesdecY", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvaesdeclastY", { XM, Vex, EXx }, PREFIX_DATA },
/* E0 */
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E0) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E1) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E2) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E3) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E4) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E5) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E6) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E7) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
/* E8 */
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E8) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E9) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EA) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EB) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EC) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38ED) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EE) },
- { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EF) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
+ { X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38Ex) },
/* F0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -947,23 +947,23 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_40) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_41) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_42) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_43) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_44) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_45) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_46) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_47) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
/* 48 */
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_48) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_49) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_4A) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_4B) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_4C) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_4D) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_4E) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP4_4F) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP4_4x) },
/* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -338,117 +338,12 @@
{ "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 },
{ "vcmps%XH", { MaskG, VexScalar, EXw, EXxEVexS, CMP }, 0 },
},
- /* PREFIX_EVEX_MAP4_40 */
+ /* PREFIX_EVEX_MAP4_4x */
{
- { "%CFcmovoS", { VexGv, Gv, Ev }, 0 },
+ { "%CFcmov%CCS", { VexGv, Gv, Ev }, 0 },
{ Bad_Opcode },
- { "%CFcmovoS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUo", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_41 */
- {
- { "%CFcmovnoS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovnoS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUno", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_42 */
- {
- { "%CFcmovbS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovbS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUb", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_43 */
- {
- { "%CFcmovaeS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovaeS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUae", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_44 */
- {
- { "%CFcmoveS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmoveS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUe", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_45 */
- {
- { "%CFcmovneS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovneS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUne", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_46 */
- {
- { "%CFcmovbeS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovbeS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUbe", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_47 */
- {
- { "%CFcmovaS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovaS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUa", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_48 */
- {
- { "%CFcmovsS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovsS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUs", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_49 */
- {
- { "%CFcmovnsS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovnsS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUns", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_4A */
- {
- { "%CFcmovpS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovpS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUp", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_4B */
- {
- { "%CFcmovnpS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovnpS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUnp", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_4C */
- {
- { "%CFcmovlS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovlS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUl", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_4D */
- {
- { "%CFcmovgeS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovgeS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUge", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_4E */
- {
- { "%CFcmovleS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovleS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUle", { Eb }, 0 },
- },
- /* PREFIX_EVEX_MAP4_4F */
- {
- { "%CFcmovgS", { VexGv, Gv, Ev }, 0 },
- { Bad_Opcode },
- { "%CFcmovgS", { VexGv, Gv, Ev }, 0 },
- { "set%ZUg", { Eb }, 0 },
+ { "%CFcmov%CCS", { VexGv, Gv, Ev }, 0 },
+ { "set%ZU%CC", { Eb }, 0 },
},
/* PREFIX_EVEX_MAP4_F0 */
{
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d
@@ -42,30 +42,30 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e2 bc 87 23 01 00 00[ ]+cmpbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ec 94 87 23 01 00 00[ ]+cmplxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ec bc 87 23 01 00 00[ ]+cmplxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpaxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpaxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpaexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpaexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpgxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpgxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpgexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpgexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e1 94 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e1 bc 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 eb 94 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 eb bc 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e9 94 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e9 bc 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e0 94 87 23 01 00 00[ ]+cmpoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e0 bc 87 23 01 00 00[ ]+cmpoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ea 94 87 23 01 00 00[ ]+cmppxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ea bc 87 23 01 00 00[ ]+cmppxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e8 94 87 23 01 00 00[ ]+cmpsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e8 bc 87 23 01 00 00[ ]+cmpsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 f7[ ]+crc32 %r31,%r22
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 37[ ]+crc32q \(%r31\),%r22
[ ]*[a-f0-9]+:[ ]*62 ec fc 08 f0 cb[ ]+crc32 %r19b,%r17
@@ -186,30 +186,30 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e2 bc 87 23 01 00 00[ ]+cmpbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ec 94 87 23 01 00 00[ ]+cmplxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ec bc 87 23 01 00 00[ ]+cmplxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpaxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpaxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpaexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpaexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpgxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpgxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpgexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpgexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e1 94 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e1 bc 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 eb 94 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 eb bc 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e9 94 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e9 bc 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e0 94 87 23 01 00 00[ ]+cmpoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e0 bc 87 23 01 00 00[ ]+cmpoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ea 94 87 23 01 00 00[ ]+cmppxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ea bc 87 23 01 00 00[ ]+cmppxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e8 94 87 23 01 00 00[ ]+cmpsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e8 bc 87 23 01 00 00[ ]+cmpsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 f7[ ]+crc32 %r31,%r22
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 37[ ]+crc32q \(%r31\),%r22
[ ]*[a-f0-9]+:[ ]*62 ec fc 08 f0 cb[ ]+crc32 %r19b,%r17
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d
@@ -42,30 +42,30 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e2 bc 87 23 01 00 00[ ]+cmpbxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ec 94 87 23 01 00 00[ ]+cmplxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ec bc 87 23 01 00 00[ ]+cmplxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpnbexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpnbexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpnbxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpnbxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpnlexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpnlexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpnlxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpnlxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpaxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpaxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpaexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpaexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpgxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpgxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpgexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpgexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e1 94 87 23 01 00 00[ ]+cmpnoxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e1 bc 87 23 01 00 00[ ]+cmpnoxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 eb 94 87 23 01 00 00[ ]+cmpnpxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 eb bc 87 23 01 00 00[ ]+cmpnpxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e9 94 87 23 01 00 00[ ]+cmpnsxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e9 bc 87 23 01 00 00[ ]+cmpnsxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnzxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnzxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e0 94 87 23 01 00 00[ ]+cmpoxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e0 bc 87 23 01 00 00[ ]+cmpoxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ea 94 87 23 01 00 00[ ]+cmppxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ea bc 87 23 01 00 00[ ]+cmppxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e8 94 87 23 01 00 00[ ]+cmpsxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e8 bc 87 23 01 00 00[ ]+cmpsxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpzxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpzxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 f7[ ]+crc32[ ]+r22,r31
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 37[ ]+crc32[ ]+r22,QWORD PTR \[r31\]
[ ]*[a-f0-9]+:[ ]*62 ec fc 08 f0 cb[ ]+crc32[ ]+r17,r19b
@@ -186,30 +186,30 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e2 bc 87 23 01 00 00[ ]+cmpbxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ec 94 87 23 01 00 00[ ]+cmplxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ec bc 87 23 01 00 00[ ]+cmplxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpnbexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpnbexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpnbxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpnbxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpnlexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpnlexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpnlxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpnlxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpaxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpaxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpaexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpaexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpgxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpgxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpgexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpgexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e1 94 87 23 01 00 00[ ]+cmpnoxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e1 bc 87 23 01 00 00[ ]+cmpnoxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 eb 94 87 23 01 00 00[ ]+cmpnpxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 eb bc 87 23 01 00 00[ ]+cmpnpxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e9 94 87 23 01 00 00[ ]+cmpnsxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e9 bc 87 23 01 00 00[ ]+cmpnsxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnzxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnzxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e0 94 87 23 01 00 00[ ]+cmpoxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e0 bc 87 23 01 00 00[ ]+cmpoxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ea 94 87 23 01 00 00[ ]+cmppxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ea bc 87 23 01 00 00[ ]+cmppxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e8 94 87 23 01 00 00[ ]+cmpsxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e8 bc 87 23 01 00 00[ ]+cmpsxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpzxadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpzxadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpexadd[ ]+DWORD PTR \[r31\+rax\*4\+0x123\],edx,r25d
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpexadd[ ]+QWORD PTR \[r31\+rax\*4\+0x123\],r15,r31
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 f7[ ]+crc32[ ]+r22,r31
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 37[ ]+crc32[ ]+r22,QWORD PTR \[r31\]
[ ]*[a-f0-9]+:[ ]*62 ec fc 08 f0 cb[ ]+crc32[ ]+r17,r19b
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d
@@ -42,30 +42,30 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e2 bc 87 23 01 00 00[ ]+cmpbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ec 94 87 23 01 00 00[ ]+cmplxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ec bc 87 23 01 00 00[ ]+cmplxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpaxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpaxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpaexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpaexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpgxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpgxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpgexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpgexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e1 94 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e1 bc 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 eb 94 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 eb bc 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e9 94 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e9 bc 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e0 94 87 23 01 00 00[ ]+cmpoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e0 bc 87 23 01 00 00[ ]+cmpoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ea 94 87 23 01 00 00[ ]+cmppxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ea bc 87 23 01 00 00[ ]+cmppxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e8 94 87 23 01 00 00[ ]+cmpsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e8 bc 87 23 01 00 00[ ]+cmpsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 f7[ ]+crc32 %r31,%r22
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 37[ ]+crc32q \(%r31\),%r22
[ ]*[a-f0-9]+:[ ]*62 ec fc 08 f0 cb[ ]+crc32 %r19b,%r17
@@ -186,30 +186,30 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e2 bc 87 23 01 00 00[ ]+cmpbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ec 94 87 23 01 00 00[ ]+cmplxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ec bc 87 23 01 00 00[ ]+cmplxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpnbexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpnbxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpnlexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpnlxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e7 94 87 23 01 00 00[ ]+cmpaxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e7 bc 87 23 01 00 00[ ]+cmpaxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e3 94 87 23 01 00 00[ ]+cmpaexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e3 bc 87 23 01 00 00[ ]+cmpaexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ef 94 87 23 01 00 00[ ]+cmpgxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ef bc 87 23 01 00 00[ ]+cmpgxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 ed 94 87 23 01 00 00[ ]+cmpgexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ed bc 87 23 01 00 00[ ]+cmpgexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e1 94 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e1 bc 87 23 01 00 00[ ]+cmpnoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 eb 94 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 eb bc 87 23 01 00 00[ ]+cmpnpxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e9 94 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e9 bc 87 23 01 00 00[ ]+cmpnsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e5 94 87 23 01 00 00[ ]+cmpnexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e5 bc 87 23 01 00 00[ ]+cmpnexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e0 94 87 23 01 00 00[ ]+cmpoxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e0 bc 87 23 01 00 00[ ]+cmpoxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 ea 94 87 23 01 00 00[ ]+cmppxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 ea bc 87 23 01 00 00[ ]+cmppxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 da 35 00 e8 94 87 23 01 00 00[ ]+cmpsxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e8 bc 87 23 01 00 00[ ]+cmpsxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpzxadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
-[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpzxadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 da 35 00 e4 94 87 23 01 00 00[ ]+cmpexadd[ ]+%r25d,%edx,0x123\(%r31,%rax,4\)
+[ ]*[a-f0-9]+:[ ]*62 5a 85 00 e4 bc 87 23 01 00 00[ ]+cmpexadd[ ]+%r31,%r15,0x123\(%r31,%rax,4\)
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 f7[ ]+crc32 %r31,%r22
[ ]*[a-f0-9]+:[ ]*62 cc fc 08 f1 37[ ]+crc32q \(%r31\),%r22
[ ]*[a-f0-9]+:[ ]*62 ec fc 08 f0 cb[ ]+crc32 %r19b,%r17
--- a/gas/testsuite/gas/i386/x86-64-apx_f-evex.d
+++ b/gas/testsuite/gas/i386/x86-64-apx_f-evex.d
@@ -116,30 +116,30 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*62 d2 05 08 ee 94 80 23 01 00 00\s+\{evex\} cmplexadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 52 85 08 ec bc 80 23 01 00 00\s+\{evex\} cmplxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d2 05 08 ec 94 80 23 01 00 00\s+\{evex\} cmplxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 52 85 08 e7 bc 80 23 01 00 00\s+\{evex\} cmpnbexadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 d2 05 08 e7 94 80 23 01 00 00\s+\{evex\} cmpnbexadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 52 85 08 e3 bc 80 23 01 00 00\s+\{evex\} cmpnbxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 d2 05 08 e3 94 80 23 01 00 00\s+\{evex\} cmpnbxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 52 85 08 ef bc 80 23 01 00 00\s+\{evex\} cmpnlexadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 d2 05 08 ef 94 80 23 01 00 00\s+\{evex\} cmpnlexadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 52 85 08 ed bc 80 23 01 00 00\s+\{evex\} cmpnlxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 d2 05 08 ed 94 80 23 01 00 00\s+\{evex\} cmpnlxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 52 85 08 e7 bc 80 23 01 00 00\s+\{evex\} cmpaxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d2 05 08 e7 94 80 23 01 00 00\s+\{evex\} cmpaxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 52 85 08 e3 bc 80 23 01 00 00\s+\{evex\} cmpaexadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d2 05 08 e3 94 80 23 01 00 00\s+\{evex\} cmpaexadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 52 85 08 ef bc 80 23 01 00 00\s+\{evex\} cmpgxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d2 05 08 ef 94 80 23 01 00 00\s+\{evex\} cmpgxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 52 85 08 ed bc 80 23 01 00 00\s+\{evex\} cmpgexadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d2 05 08 ed 94 80 23 01 00 00\s+\{evex\} cmpgexadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 52 85 08 e1 bc 80 23 01 00 00\s+\{evex\} cmpnoxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d2 05 08 e1 94 80 23 01 00 00\s+\{evex\} cmpnoxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 52 85 08 eb bc 80 23 01 00 00\s+\{evex\} cmpnpxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d2 05 08 eb 94 80 23 01 00 00\s+\{evex\} cmpnpxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 52 85 08 e9 bc 80 23 01 00 00\s+\{evex\} cmpnsxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d2 05 08 e9 94 80 23 01 00 00\s+\{evex\} cmpnsxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 52 85 08 e5 bc 80 23 01 00 00\s+\{evex\} cmpnzxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 d2 05 08 e5 94 80 23 01 00 00\s+\{evex\} cmpnzxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 52 85 08 e5 bc 80 23 01 00 00\s+\{evex\} cmpnexadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d2 05 08 e5 94 80 23 01 00 00\s+\{evex\} cmpnexadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 52 85 08 e0 bc 80 23 01 00 00\s+\{evex\} cmpoxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d2 05 08 e0 94 80 23 01 00 00\s+\{evex\} cmpoxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 52 85 08 ea bc 80 23 01 00 00\s+\{evex\} cmppxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d2 05 08 ea 94 80 23 01 00 00\s+\{evex\} cmppxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 52 85 08 e8 bc 80 23 01 00 00\s+\{evex\} cmpsxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d2 05 08 e8 94 80 23 01 00 00\s+\{evex\} cmpsxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 52 85 08 e4 bc 80 23 01 00 00\s+\{evex\} cmpzxadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
-\s*[a-f0-9]+:\s*62 d2 05 08 e4 94 80 23 01 00 00\s+\{evex\} cmpzxadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 52 85 08 e4 bc 80 23 01 00 00\s+\{evex\} cmpexadd\s+%r15,%r15,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d2 05 08 e4 94 80 23 01 00 00\s+\{evex\} cmpexadd\s+%r15d,%edx,0x123\(%r8,%rax,4\)
\s*[a-f0-9]+:\s*62 d4 fc 08 ff cf\s+\{evex\} dec\s+%r15
\s*[a-f0-9]+:\s*62 d4 7c 08 ff cf\s+\{evex\} dec\s+%r15d
\s*[a-f0-9]+:\s*62 d4 7d 08 ff cf\s+\{evex\} dec\s+%r15w
--- a/gas/testsuite/gas/i386/x86-64-cmpccxadd.d
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d
@@ -39,38 +39,38 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\)
\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpaxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpaxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpaxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpaxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpaxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpaxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpaxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpaxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpaexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpaexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpaexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpaexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpaexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpaexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpaexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpaexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpgxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpgxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpgxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpgxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpgxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpgxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpgxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpgxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpgexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpgexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpgexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpgexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpgexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpgexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpgexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpgexadd %rbx,%rcx,-0x400\(%rdx\)
\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\)
@@ -95,14 +95,14 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\)
\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnexadd %rbx,%rcx,-0x400\(%rdx\)
\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\)
@@ -127,14 +127,14 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\)
\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpexadd %rbx,%rcx,-0x400\(%rdx\)
\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\)
@@ -167,38 +167,38 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\)
\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpaxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpaxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpaxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpaxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpaxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpaxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpaxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpaxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpaexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpaexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpaexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpaexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpaexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpaexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpaexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpaexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpgxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpgxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpgxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpgxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpgxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpgxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpgxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpgxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpgexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpgexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpgexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpgexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpgexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpgexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpgexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpgexadd %rbx,%rcx,-0x400\(%rdx\)
\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\)
@@ -223,14 +223,14 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\)
\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnexadd %rbx,%rcx,-0x400\(%rdx\)
\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\)
@@ -255,12 +255,12 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\)
\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\)
\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\)
-\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
-\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\)
-\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\)
-\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpexadd %rbx,%rcx,-0x400\(%rdx\)
#pass
--- a/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
@@ -39,38 +39,38 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx
\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpaxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpaxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpaxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpaxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpaxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpaxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpaxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpaxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpaexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpaexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpaexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpaexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpaexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpaexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpaexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpaexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpgxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpgxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpgxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpgxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpgxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpgxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpgxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpgxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpgexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpgexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpgexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpgexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpgexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpgexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpgexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpgexadd QWORD PTR \[rdx-0x400\],rcx,rbx
\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx
\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
@@ -95,14 +95,14 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx
\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnexadd QWORD PTR \[rdx-0x400\],rcx,rbx
\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx
\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
@@ -127,14 +127,14 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx
\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpexadd QWORD PTR \[rdx-0x400\],rcx,rbx
\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx
\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
@@ -167,38 +167,38 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx
\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpaxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpaxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpaxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpaxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpaxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpaxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpaxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpaxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpaexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpaexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpaexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpaexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpaexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpaexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpaexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpaexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpgxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpgxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpgxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpgxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpgxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpgxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpgxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpgxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpgexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpgexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpgexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpgexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpgexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpgexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpgexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpgexadd QWORD PTR \[rdx-0x400\],rcx,rbx
\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx
\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
@@ -223,14 +223,14 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx
\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnexadd QWORD PTR \[rdx-0x400\],rcx,rbx
\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx
\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
@@ -255,12 +255,12 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx
\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
-\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
-\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
-\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
-\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx
-\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
-\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpexadd QWORD PTR \[rdx-0x400\],rcx,rbx
#pass
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/3] x86/APX: convert ZU to operand constraint
2024-05-29 8:06 [PATCH 0/3] x86/APX: ZU support follow-up Jan Beulich
2024-05-29 8:07 ` [PATCH 1/3] x86/APX: support extended SETcc form Jan Beulich
2024-05-29 8:08 ` [PATCH 2/3] x86: disassembler macro for condition code Jan Beulich
@ 2024-05-29 8:09 ` Jan Beulich
2024-06-07 7:22 ` Cui, Lili
2 siblings, 1 reply; 13+ messages in thread
From: Jan Beulich @ 2024-05-29 8:09 UTC (permalink / raw)
To: Binutils; +Cc: Lili Cui, H.J. Lu
Extremely rarely used attributes are inefficient when represented by a
separate attribute. Convert it to an operand constraint, as already
suggested during review. The collision with RegKludge is pretty simple
to resolve.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4287,7 +4287,7 @@ build_apx_evex_prefix (void)
/* Encode the NDD bit of the instruction promoted from the legacy
space. ZU shares the same bit with NDD. */
if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
- || i.tm.opcode_modifier.zu)
+ || i.tm.opcode_modifier.operandconstraint == ZERO_UPPER)
i.vex.bytes[3] |= 0x10;
/* Encode the NF bit. */
@@ -10301,6 +10301,10 @@ process_operands (void)
i.types[first_reg_op + 1] = i.types[first_reg_op];
i.operands++;
i.reg_operands++;
+
+ /* For IMULZU switch around the constraint. */
+ if (i.tm.mnem_off == MN_imulzu)
+ i.tm.opcode_modifier.operandconstraint = ZERO_UPPER;
}
if (i.tm.opcode_modifier.modrm)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -492,7 +492,6 @@ static bitfield opcode_modifiers[] =
BITFIELD (NoEgpr),
BITFIELD (NF),
BITFIELD (Rex2),
- BITFIELD (ZU),
};
#define CLASS(n) #n, n
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -579,6 +579,8 @@ enum
#define DISTINCT_DEST 8
/* Instruction updates stack pointer implicitly. */
#define IMPLICIT_STACK_OP 9
+ /* Instruction zeroes upper part of register. */
+#define ZERO_UPPER 10
OperandConstraint,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
@@ -757,9 +759,6 @@ enum
/* Instrucion requires REX2 prefix. */
Rex2,
- /* Support zero upper */
- ZU,
-
/* The last bitfield in i386_opcode_modifier. */
Opcode_Modifier_Num
};
@@ -808,7 +807,6 @@ typedef struct i386_opcode_modifier
unsigned int noegpr:1;
unsigned int nf:1;
unsigned int rex2:1;
- unsigned int zu:1;
} i386_opcode_modifier;
/* Operand classes. */
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -85,6 +85,7 @@
#define RegKludge OperandConstraint=REG_KLUDGE
#define Ugh OperandConstraint=UGH
#define ImplicitStackOp OperandConstraint=IMPLICIT_STACK_OP
+#define ZU OperandConstraint=ZERO_UPPER
#define ATTSyntax Dialect=ATT_SYNTAX
#define ATTMnemonic Dialect=ATT_MNEMONIC
@@ -409,10 +410,12 @@ imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sS
// transformation.
imul, 0x6b, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 }
imul, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64 }
-imulzu, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF|ZU, { Imm8S, Reg16 }
imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
imul, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
-imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF|ZU, { Imm16, Reg16 }
+// ZU is omitted here, for colliding with RegKludge. process_operands() will
+// replace the constraint value after processing RegKludge.
+imulzu, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF/*|ZU*/, { Imm8S, Reg16 }
+imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF/*|ZU*/, { Imm16, Reg16 }
<mul>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 2/3] x86: disassembler macro for condition code
2024-05-29 8:08 ` [PATCH 2/3] x86: disassembler macro for condition code Jan Beulich
@ 2024-05-30 5:52 ` Jiang, Haochen
2024-05-30 6:36 ` Jan Beulich
0 siblings, 1 reply; 13+ messages in thread
From: Jiang, Haochen @ 2024-05-30 5:52 UTC (permalink / raw)
To: Beulich, Jan, Binutils; +Cc: Cui, Lili, H.J. Lu
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Wednesday, May 29, 2024 4:09 PM
> To: Binutils <binutils@sourceware.org>
> Cc: Cui, Lili <lili.cui@intel.com>; H.J. Lu <hjl.tools@gmail.com>
> Subject: [PATCH 2/3] x86: disassembler macro for condition code
>
> Both CMPccXADD and APX'es {,CF}CMOVcc have almost identical entries
> replicated 16 times each. Fold those to just one each by introducing a
> %CC macro. (Note that the recording of ->condition_code in print_insn()
> is merely for completeness for now; it's not used as long as only
> VEX/EVEX encodings would consume it.)
>
> This then also renders condition codes printed consistent across all
> respective insns; CMPxxXADD had a number of outliers so far.
Although the table seems much more "elegant" and alias is not that wrong,
I suppose we should still stick to documentation and output what it is in
documentation in disassembler for CMPccXADD, or the documentation is
useless.
Thx,
Haochen
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] x86: disassembler macro for condition code
2024-05-30 5:52 ` Jiang, Haochen
@ 2024-05-30 6:36 ` Jan Beulich
2024-05-30 6:44 ` Jiang, Haochen
0 siblings, 1 reply; 13+ messages in thread
From: Jan Beulich @ 2024-05-30 6:36 UTC (permalink / raw)
To: Jiang, Haochen; +Cc: Cui, Lili, H.J. Lu, Binutils
On 30.05.2024 07:52, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Wednesday, May 29, 2024 4:09 PM
>> To: Binutils <binutils@sourceware.org>
>> Cc: Cui, Lili <lili.cui@intel.com>; H.J. Lu <hjl.tools@gmail.com>
>> Subject: [PATCH 2/3] x86: disassembler macro for condition code
>>
>> Both CMPccXADD and APX'es {,CF}CMOVcc have almost identical entries
>> replicated 16 times each. Fold those to just one each by introducing a
>> %CC macro. (Note that the recording of ->condition_code in print_insn()
>> is merely for completeness for now; it's not used as long as only
>> VEX/EVEX encodings would consume it.)
>>
>> This then also renders condition codes printed consistent across all
>> respective insns; CMPxxXADD had a number of outliers so far.
>
> Although the table seems much more "elegant" and alias is not that wrong,
> I suppose we should still stick to documentation and output what it is in
> documentation in disassembler for CMPccXADD, or the documentation is
> useless.
I did long ago ask for the documentation to be updated, to name all (and
in particular the more sensible) possible spellings, just like is the case
with other condition-code insns. I hope that the latest when the insn is
integrated into Vol 2 of the SDM, this will finally happen. As to more
sensible: We're talking of condition codes resulting from comparisons here.
Z/NZ is less meaningful there than E/NE; Z/NZ are the better forms for
things like TEST.
Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 2/3] x86: disassembler macro for condition code
2024-05-30 6:36 ` Jan Beulich
@ 2024-05-30 6:44 ` Jiang, Haochen
2024-05-31 1:59 ` Jiang, Haochen
0 siblings, 1 reply; 13+ messages in thread
From: Jiang, Haochen @ 2024-05-30 6:44 UTC (permalink / raw)
To: Beulich, Jan; +Cc: Cui, Lili, H.J. Lu, Binutils
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Thursday, May 30, 2024 2:36 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: Cui, Lili <lili.cui@intel.com>; H.J. Lu <hjl.tools@gmail.com>; Binutils
> <binutils@sourceware.org>
> Subject: Re: [PATCH 2/3] x86: disassembler macro for condition code
>
> On 30.05.2024 07:52, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Wednesday, May 29, 2024 4:09 PM
> >> To: Binutils <binutils@sourceware.org>
> >> Cc: Cui, Lili <lili.cui@intel.com>; H.J. Lu <hjl.tools@gmail.com>
> >> Subject: [PATCH 2/3] x86: disassembler macro for condition code
> >>
> >> Both CMPccXADD and APX'es {,CF}CMOVcc have almost identical entries
> >> replicated 16 times each. Fold those to just one each by introducing a
> >> %CC macro. (Note that the recording of ->condition_code in print_insn()
> >> is merely for completeness for now; it's not used as long as only
> >> VEX/EVEX encodings would consume it.)
> >>
> >> This then also renders condition codes printed consistent across all
> >> respective insns; CMPxxXADD had a number of outliers so far.
> >
> > Although the table seems much more "elegant" and alias is not that wrong,
> > I suppose we should still stick to documentation and output what it is in
> > documentation in disassembler for CMPccXADD, or the documentation is
> > useless.
>
> I did long ago ask for the documentation to be updated, to name all (and
> in particular the more sensible) possible spellings, just like is the case
> with other condition-code insns. I hope that the latest when the insn is
> integrated into Vol 2 of the SDM, this will finally happen. As to more
Actually I am ok with both. Let me check with the documentation guy.
Thx,
Haochen
> sensible: We're talking of condition codes resulting from comparisons here.
> Z/NZ is less meaningful there than E/NE; Z/NZ are the better forms for
> things like TEST.
>
> Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] x86/APX: support extended SETcc form
2024-05-29 8:07 ` [PATCH 1/3] x86/APX: support extended SETcc form Jan Beulich
@ 2024-05-30 8:18 ` Cui, Lili
0 siblings, 0 replies; 13+ messages in thread
From: Cui, Lili @ 2024-05-30 8:18 UTC (permalink / raw)
To: Beulich, Jan, Binutils; +Cc: H.J. Lu
> As indicated during review, spelling/readability-wise
>
> setz %eax
>
> is easier than
>
> setzuz %al
>
> _and_ properly specifies the full register that's being modified. Permit that form
> to be used, even if the spec writers are unwilling to formally mention it.
>
> While there also correct the non-ZU EVEX form: That ought to also permit
> memory operands.
> ---
> In principle SETZUcc ought to also permit for memory operands, for (as per the
> spec) EVEX.ZU simply being ignored in that case. However, such forms are rather
> meaningless, so I'm not convinced we really want to permit that.
>
> --- a/gas/testsuite/gas/i386/x86-64-apx-zu-intel.d
> +++ b/gas/testsuite/gas/i386/x86-64-apx-zu-intel.d
> @@ -42,6 +42,9 @@ Disassembly of section .text:
> \s*[a-f0-9]+:\s*62 dc 7f 18 4f c1[ ]+setzug r25b
> \s*[a-f0-9]+:\s*d5 91 9f c1[ ]+setg r25b
> \s*[a-f0-9]+:\s*62 f4 7f 08 4f c0[ ]+\{evex\} setg al
> +\s*[a-f0-9]+:\s*62 f4 7f 08 4f 00[ ]+\{evex\} setg (BYTE PTR )?\[rax\]
> +\s*[a-f0-9]+:\s*62 f4 7f 18 4a c0[ ]+setzup al
> +\s*[a-f0-9]+:\s*62 f4 ff 18 4b c0[ ]+setzunp al
> \s*[a-f0-9]+:\s*62 f4 7d 18 6b c3 0a[ ]+imulzu ax,bx,0xa
> \s*[a-f0-9]+:\s*67 62 f4 7d 18 6b 00 0a[ ]+imulzu ax,WORD PTR \[eax\],0xa
> \s*[a-f0-9]+:\s*62 ec 7d 18 6b c1 0a[ ]+imulzu r16w,r17w,0xa
> --- a/gas/testsuite/gas/i386/x86-64-apx-zu.d
> +++ b/gas/testsuite/gas/i386/x86-64-apx-zu.d
> @@ -42,6 +42,9 @@ Disassembly of section .text:
> \s*[a-f0-9]+:\s*62 dc 7f 18 4f c1[ ]+setzug %r25b
> \s*[a-f0-9]+:\s*d5 91 9f c1[ ]+setg %r25b
> \s*[a-f0-9]+:\s*62 f4 7f 08 4f c0[ ]+\{evex\} setg %al
> +\s*[a-f0-9]+:\s*62 f4 7f 08 4f 00[ ]+\{evex\} setg \(%rax\)
> +\s*[a-f0-9]+:\s*62 f4 7f 18 4a c0[ ]+setzup %al
> +\s*[a-f0-9]+:\s*62 f4 ff 18 4b c0[ ]+setzunp %al
> \s*[a-f0-9]+:\s*62 f4 7d 18 6b c3 0a[ ]+imulzu \$0xa,%bx,%ax
> \s*[a-f0-9]+:\s*67 62 f4 7d 18 6b 00 0a[ ]+imulzu \$0xa,\(%eax\),%ax
> \s*[a-f0-9]+:\s*62 ec 7d 18 6b c1 0a[ ]+imulzu \$0xa,%r17w,%r16w
> --- a/gas/testsuite/gas/i386/x86-64-apx-zu.s
> +++ b/gas/testsuite/gas/i386/x86-64-apx-zu.s
> @@ -36,6 +36,9 @@ _start:
> setzug %r25b
> setg %r25b
> {evex} setg %al
> + {evex} setg (%rax)
> + setpe %eax
> + setpo %rax
>
> .intel_syntax noprefix
> imulzu ax,bx, 10
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -533,8 +533,11 @@ loopne, 0xe0, x64, JumpByte|No_bSuf|No_w
>
> // Set byte on flag instructions.
> set<cc>, 0xf9<cc:opc>/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
> { Reg8|Unspecified|BaseIndex } -set<cc>, 0xf24<cc:opc>/0, APX_F,
> Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4, { Reg8 }
> +set<cc>, 0xf24<cc:opc>/0, APX_F,
> +Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4, {
> +Reg8|Unspecified|BaseIndex }
> setzu<cc>, 0xf24<cc:opc>/0, APX_F,
> Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4|ZU, { Reg8 }
> +// As an extension, allow SETcc without the ZU infix, instead taking
> +the full // register as operand.
> +set<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|ZU, {
> +Reg32|Reg64 }
>
> // String manipulation.
> cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}
Thanks for fixing the memory issue with non-ZU EVEX formats, this patch is OK for me.
Lili.
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 2/3] x86: disassembler macro for condition code
2024-05-30 6:44 ` Jiang, Haochen
@ 2024-05-31 1:59 ` Jiang, Haochen
2024-06-06 2:27 ` Jiang, Haochen
0 siblings, 1 reply; 13+ messages in thread
From: Jiang, Haochen @ 2024-05-31 1:59 UTC (permalink / raw)
To: Beulich, Jan; +Cc: Cui, Lili, H.J. Lu, Binutils
> > >> This then also renders condition codes printed consistent across
> > >> all respective insns; CMPxxXADD had a number of outliers so far.
> > >
> > > Although the table seems much more "elegant" and alias is not that
> > > wrong, I suppose we should still stick to documentation and output
> > > what it is in documentation in disassembler for CMPccXADD, or the
> > > documentation is useless.
> >
> > I did long ago ask for the documentation to be updated, to name all
> > (and in particular the more sensible) possible spellings, just like is
> > the case with other condition-code insns. I hope that the latest when
> > the insn is integrated into Vol 2 of the SDM, this will finally
> > happen. As to more
>
> Actually I am ok with both. Let me check with the documentation guy.
I am ok with that. I suppose documentation will name that in the future.
Thx,
Haochen
>
> Thx,
> Haochen
>
> > sensible: We're talking of condition codes resulting from comparisons here.
> > Z/NZ is less meaningful there than E/NE; Z/NZ are the better forms for
> > things like TEST.
> >
> > Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 2/3] x86: disassembler macro for condition code
2024-05-31 1:59 ` Jiang, Haochen
@ 2024-06-06 2:27 ` Jiang, Haochen
2024-06-06 6:17 ` Jan Beulich
0 siblings, 1 reply; 13+ messages in thread
From: Jiang, Haochen @ 2024-06-06 2:27 UTC (permalink / raw)
To: Beulich, Jan; +Cc: Cui, Lili, H.J. Lu, Binutils
> > > I did long ago ask for the documentation to be updated, to name all
> > > (and in particular the more sensible) possible spellings, just like
> > > is the case with other condition-code insns. I hope that the latest
> > > when the insn is integrated into Vol 2 of the SDM, this will finally
> > > happen. As to more
> >
> > Actually I am ok with both. Let me check with the documentation guy.
>
> I am ok with that. I suppose documentation will name that in the future.
>
Hi Jan,
Could we hold this patch for a while? Someone internal just jump out against
adding them. More discussion is needed. I am sorry for that :(.
Thx,
Haochen
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] x86: disassembler macro for condition code
2024-06-06 2:27 ` Jiang, Haochen
@ 2024-06-06 6:17 ` Jan Beulich
2024-06-06 6:27 ` Jiang, Haochen
0 siblings, 1 reply; 13+ messages in thread
From: Jan Beulich @ 2024-06-06 6:17 UTC (permalink / raw)
To: Jiang, Haochen; +Cc: Cui, Lili, H.J. Lu, Binutils
On 06.06.2024 04:27, Jiang, Haochen wrote:
>>>> I did long ago ask for the documentation to be updated, to name all
>>>> (and in particular the more sensible) possible spellings, just like
>>>> is the case with other condition-code insns. I hope that the latest
>>>> when the insn is integrated into Vol 2 of the SDM, this will finally
>>>> happen. As to more
>>>
>>> Actually I am ok with both. Let me check with the documentation guy.
>>
>> I am ok with that. I suppose documentation will name that in the future.
>
> Could we hold this patch for a while? Someone internal just jump out against
> adding them. More discussion is needed. I am sorry for that :(.
Just on a vague "someone" / "something" - no, not really. If there are
counter arguments, please name them so they can be addressed. Otherwise
I'm pretty determined to have this in ahead of Lili's CCMPcc/CTESTcc
patch, which I expect may become ready with the next iteration.
Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 2/3] x86: disassembler macro for condition code
2024-06-06 6:17 ` Jan Beulich
@ 2024-06-06 6:27 ` Jiang, Haochen
0 siblings, 0 replies; 13+ messages in thread
From: Jiang, Haochen @ 2024-06-06 6:27 UTC (permalink / raw)
To: Beulich, Jan; +Cc: Cui, Lili, H.J. Lu, Binutils
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Thursday, June 6, 2024 2:18 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: Cui, Lili <lili.cui@intel.com>; H.J. Lu <hjl.tools@gmail.com>; Binutils
> <binutils@sourceware.org>
> Subject: Re: [PATCH 2/3] x86: disassembler macro for condition code
>
> On 06.06.2024 04:27, Jiang, Haochen wrote:
> >>>> I did long ago ask for the documentation to be updated, to name all
> >>>> (and in particular the more sensible) possible spellings, just like
> >>>> is the case with other condition-code insns. I hope that the latest
> >>>> when the insn is integrated into Vol 2 of the SDM, this will finally
> >>>> happen. As to more
> >>>
> >>> Actually I am ok with both. Let me check with the documentation guy.
> >>
> >> I am ok with that. I suppose documentation will name that in the future.
> >
> > Could we hold this patch for a while? Someone internal just jump out against
> > adding them. More discussion is needed. I am sorry for that :(.
>
> Just on a vague "someone" / "something" - no, not really. If there are
> counter arguments, please name them so they can be addressed. Otherwise
> I'm pretty determined to have this in ahead of Lili's CCMPcc/CTESTcc
> patch, which I expect may become ready with the next iteration.
Let's go with the patch first. I suppose it is not a blocking issue.
Thx,
Haochen
>
> Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 3/3] x86/APX: convert ZU to operand constraint
2024-05-29 8:09 ` [PATCH 3/3] x86/APX: convert ZU to operand constraint Jan Beulich
@ 2024-06-07 7:22 ` Cui, Lili
0 siblings, 0 replies; 13+ messages in thread
From: Cui, Lili @ 2024-06-07 7:22 UTC (permalink / raw)
To: Beulich, Jan, Binutils; +Cc: H.J. Lu
> Extremely rarely used attributes are inefficient when represented by a separate
> attribute. Convert it to an operand constraint, as already suggested during
> review. The collision with RegKludge is pretty simple to resolve.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -4287,7 +4287,7 @@ build_apx_evex_prefix (void)
> /* Encode the NDD bit of the instruction promoted from the legacy
> space. ZU shares the same bit with NDD. */
> if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
> - || i.tm.opcode_modifier.zu)
> + || i.tm.opcode_modifier.operandconstraint == ZERO_UPPER)
> i.vex.bytes[3] |= 0x10;
>
> /* Encode the NF bit. */
> @@ -10301,6 +10301,10 @@ process_operands (void)
> i.types[first_reg_op + 1] = i.types[first_reg_op];
> i.operands++;
> i.reg_operands++;
> +
> + /* For IMULZU switch around the constraint. */
> + if (i.tm.mnem_off == MN_imulzu)
> + i.tm.opcode_modifier.operandconstraint = ZERO_UPPER;
> }
>
> if (i.tm.opcode_modifier.modrm)
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -492,7 +492,6 @@ static bitfield opcode_modifiers[] =
> BITFIELD (NoEgpr),
> BITFIELD (NF),
> BITFIELD (Rex2),
> - BITFIELD (ZU),
> };
>
> #define CLASS(n) #n, n
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -579,6 +579,8 @@ enum
> #define DISTINCT_DEST 8
> /* Instruction updates stack pointer implicitly. */ #define
> IMPLICIT_STACK_OP 9
> + /* Instruction zeroes upper part of register. */ #define ZERO_UPPER
> +10
> OperandConstraint,
> /* instruction ignores operand size prefix and in Intel mode ignores
> mnemonic size suffix check. */
> @@ -757,9 +759,6 @@ enum
> /* Instrucion requires REX2 prefix. */
> Rex2,
>
> - /* Support zero upper */
> - ZU,
> -
> /* The last bitfield in i386_opcode_modifier. */
> Opcode_Modifier_Num
> };
> @@ -808,7 +807,6 @@ typedef struct i386_opcode_modifier
> unsigned int noegpr:1;
> unsigned int nf:1;
> unsigned int rex2:1;
> - unsigned int zu:1;
> } i386_opcode_modifier;
>
> /* Operand classes. */
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -85,6 +85,7 @@
> #define RegKludge OperandConstraint=REG_KLUDGE
> #define Ugh OperandConstraint=UGH
> #define ImplicitStackOp OperandConstraint=IMPLICIT_STACK_OP
> +#define ZU OperandConstraint=ZERO_UPPER
>
> #define ATTSyntax Dialect=ATT_SYNTAX
> #define ATTMnemonic Dialect=ATT_MNEMONIC
> @@ -409,10 +410,12 @@ imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sS //
> transformation.
> imul, 0x6b, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S,
> Reg16|Reg32|Reg64 } imul, 0x6b, APX_F,
> Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm8S,
> Reg16|Reg32|Reg64 } -imulzu, 0x6b, APX_F,
> Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF|ZU, { Imm8S, Reg16 }
> imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge,
> { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } imul, 0x69, APX_F,
> Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF,
> { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } -imulzu, 0x69, APX_F,
> Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF|ZU, { Imm16, Reg16 }
> +// ZU is omitted here, for colliding with RegKludge.
> +process_operands() will // replace the constraint value after processing
> RegKludge.
> +imulzu, 0x6b, APX_F,
> +Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF/*|ZU*/, { Imm8S,
> Reg16 }
> +imulzu, 0x69, APX_F,
> +Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF/*|ZU*/, { Imm16,
> Reg16 }
>
> <mul>
>
LGTM, thanks!
Lili.
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-06-07 7:22 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-29 8:06 [PATCH 0/3] x86/APX: ZU support follow-up Jan Beulich
2024-05-29 8:07 ` [PATCH 1/3] x86/APX: support extended SETcc form Jan Beulich
2024-05-30 8:18 ` Cui, Lili
2024-05-29 8:08 ` [PATCH 2/3] x86: disassembler macro for condition code Jan Beulich
2024-05-30 5:52 ` Jiang, Haochen
2024-05-30 6:36 ` Jan Beulich
2024-05-30 6:44 ` Jiang, Haochen
2024-05-31 1:59 ` Jiang, Haochen
2024-06-06 2:27 ` Jiang, Haochen
2024-06-06 6:17 ` Jan Beulich
2024-06-06 6:27 ` Jiang, Haochen
2024-05-29 8:09 ` [PATCH 3/3] x86/APX: convert ZU to operand constraint Jan Beulich
2024-06-07 7:22 ` Cui, Lili
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