public inbox for binutils@sourceware.org
 help / color / mirror / Atom feed
From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: "Beulich, Jan" <JBeulich@suse.com>,
	"Cui, Lili" <lili.cui@intel.com>,
	Binutils <binutils@sourceware.org>
Subject: RE: [PATCH 6/6] x86: optimize {,V}PEXTR{D,Q} with immediate of 0
Date: Wed, 19 Jun 2024 02:01:02 +0000	[thread overview]
Message-ID: <SA1PR11MB59465EE934CE271578F3F7E8ECCF2@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CAMe9rOqrDN1fgFHaBHQ_XhJh8Kg=W+QeuNQBF9=h1huGONW0QQ@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 2957 bytes --]

I see, that refreshes my understanding on that. I have no concern now.

Thx,
Haochen

From: H.J. Lu <hjl.tools@gmail.com>
Sent: Wednesday, June 19, 2024 4:38 AM
To: Jiang, Haochen <haochen.jiang@intel.com>
Cc: Beulich, Jan <JBeulich@suse.com>; Cui, Lili <lili.cui@intel.com>; Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 6/6] x86: optimize {,V}PEXTR{D,Q} with immediate of 0

-Os should optimize for code size. Other optimizations should
take performance into account.

On Tue, Jun 18, 2024, 2:23 PM Jiang, Haochen <haochen.jiang@intel.com<mailto:haochen.jiang@intel.com>> wrote:
> >> Wait. While the compiler may use PSRLDQ here, based on knowing
> >> assumptions
> >> made elsewhere, the assembler can't: The replacement insn must generate the
> >> exact same result in the destination register. PSRLDQ with an immediate of
> >> 0 (which effectively you're suggesting to use here) doesn't alter the
> >> destination register at all, though. When really we want the upper bits of
> >> the register cleared.
> >
> > pextrd/q also doesn't clear them at all. For vpextrd/q and vpsrldq, they will
> > both clear higher bits. So they will be the same.
>
> Wait - your suggestion is even more confusing: The destination of PSRLDQ is
> an XMM register, whereas the destination of PEXTR* is a GPR or memory. This
> is properly expressed in the constraints in the compiler, but clearly we
> can't replace insns like this in the assembler.

Yes, I realized that I am wrong here, there are no constraints. vmovd/q would be
definitely better and doable here if we would like to do something.

> >>> Also, I suppose the optimization related to latency should not be done in
> >>> assembler.
> >>
> >> Why? We have -O, -O1, and -O2 alongside -Os for a reason.
> >
> > I am quite conservative on the optimization in assembler. If we are also going to
> > optimize those hand-written code, the optimization could work.
> >
> > However, when they hand write some code, are we supposed to change them?
>
> Well, if we aren't to, people simply don't pass -O.
>
> > For -Os, we could give them all the optimizations we have, but for -O, I am not
> > that sure.
> >
> > And I suppose we might add too much burden for the assembler if we are going
> > to add too much optimizations related to latency. It will become another compiler.
> > Are we supposed to copy all the optimizations from compiler?
>
> Probably not all (and many aren't the the insn level anyway, nor do we - so
> far at least - optimize for latency/throughput at the expense of code size).
> But yes - this specific aspect is why I keep raising questions on what
> optimizations are worth it vs where we'd better leave code alone.

H.J., what is your opinion on that?

Thx,
Haochen

>
> Jan
>
> > IMO, optimization to
> > codesize is ok, but for latency, I am a little concerned.
> >
> > Thx,
> > Haochen
> >
> >>
> >> Jan

  reply	other threads:[~2024-06-19  2:01 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-14 12:10 [PATCH 0/6] x86: a few more optimizations Jan Beulich
2024-06-14 12:12 ` [PATCH 1/6] x86: optimize left-shift-by-1 Jan Beulich
2024-06-17  2:56   ` Jiang, Haochen
2024-06-17  8:40     ` Jan Beulich
2024-06-14 12:12 ` [PATCH 2/6] x86/APX: optimize {nf} forms of ADD/SUB with immediate of 0x80 Jan Beulich
2024-06-14 12:13 ` [PATCH 3/6] x86/APX: optimize {nf}-form rotate-by-width-less-1 Jan Beulich
2024-06-14 12:13 ` [PATCH 4/6] x86/APX: optimize certain {nf}-form insns to LEA Jan Beulich
2024-06-14 12:14 ` [PATCH 5/6] x86/APX: optimize certain {nf}-form insns to BMI2 ones Jan Beulich
2024-06-17  6:36   ` Jiang, Haochen
2024-06-14 12:14 ` [PATCH 6/6] x86: optimize {,V}PEXTR{D,Q} with immediate of 0 Jan Beulich
2024-06-17  6:49   ` Jiang, Haochen
2024-06-17  8:56     ` Jan Beulich
2024-06-18  3:25       ` Jiang, Haochen
2024-06-18  6:14         ` Jan Beulich
2024-06-18  6:23           ` Jiang, Haochen
2024-06-18 20:37             ` H.J. Lu
2024-06-19  2:01               ` Jiang, Haochen [this message]
2024-06-17  2:51 ` [PATCH 0/6] x86: a few more optimizations Jiang, Haochen
2024-06-17  8:33   ` Jan Beulich
2024-06-17  8:09 ` Cui, Lili
2024-06-17  8:37   ` Jan Beulich
2024-06-17  9:12     ` Cui, Lili

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=SA1PR11MB59465EE934CE271578F3F7E8ECCF2@SA1PR11MB5946.namprd11.prod.outlook.com \
    --to=haochen.jiang@intel.com \
    --cc=JBeulich@suse.com \
    --cc=binutils@sourceware.org \
    --cc=hjl.tools@gmail.com \
    --cc=lili.cui@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).