From 6a6c7d729264066d79d97d7a3d89c0973d2b6a38 Mon Sep 17 00:00:00 2001
From: Kong Lingling <lingling.kong@intel.com>
Date: Fri, 17 Jun 2022 10:19:15 +0800
Subject: [PATCH 6/8] Support Intel RAO-INT

gas/ChangeLog:

	* NEWS: Support Intel RAO-INT.
	* config/tc-i386.c: Add raoint.
	* doc/c-i386.texi: Document .raoint.
	* testsuite/gas/i386/i386.exp: Run RAO_INT tests.
	* testsuite/gas/i386/raoint-intel.d: New test.
	* testsuite/gas/i386/raoint.d: Ditto.
	* testsuite/gas/i386/raoint.s: Ditto.
	* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_0F38FC): New.
	(prefix_table): Add PREFIX_0F38FC.
	* i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
	CPU_ANY_RAO_INT_FLAGS.
	* i386-init.h: Regenerated.
	* i386-opc.h: (CpuRAO_INT): New.
	(i386_cpu_flags): Add cpuraoint.
	* i386-opc.tbl: Add RAO_INT instructions.
	* i386-tbl.h: Regenerated.
---
 gas/NEWS                                     |    2 +
 gas/config/tc-i386.c                         |    1 +
 gas/doc/c-i386.texi                          |    3 +-
 gas/testsuite/gas/i386/i386.exp              |    4 +
 gas/testsuite/gas/i386/raoint-intel.d        |   18 +
 gas/testsuite/gas/i386/raoint.d              |   18 +
 gas/testsuite/gas/i386/raoint.s              |   15 +
 gas/testsuite/gas/i386/x86-64-raoint-intel.d |   18 +
 gas/testsuite/gas/i386/x86-64-raoint.d       |   18 +
 gas/testsuite/gas/i386/x86-64-raoint.s       |   15 +
 opcodes/i386-dis.c                           |   11 +-
 opcodes/i386-gen.c                           |    5 +
 opcodes/i386-init.h                          |  514 +-
 opcodes/i386-opc.h                           |    5 +-
 opcodes/i386-opc.tbl                         |    9 +
 opcodes/i386-tbl.h                           | 7902 +++++++++---------
 16 files changed, 4386 insertions(+), 4172 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/raoint-intel.d
 create mode 100644 gas/testsuite/gas/i386/raoint.d
 create mode 100644 gas/testsuite/gas/i386/raoint.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s

diff --git a/gas/NEWS b/gas/NEWS
index 9757209a9f..f352c5ab89 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for Intel RAO-INT instructions.
+
 * Add support for Intel CMPccXADD instructions.
 
 * Add support for Intel AVX-NE-CONVERT instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index cd3d1377a1..985b64b6e1 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1098,6 +1098,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
   SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
   SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
+  SUBARCH (rao_int, RAO_INT, RAO_INT, false),
 };
 
 #undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 24ea55579e..82267389f2 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -198,6 +198,7 @@ accept various extension mnemonics.  For example,
 @code{avx_vnni_int8},
 @code{avx_ne_convert},
 @code{cmpccxadd},
+@code{rao_int},
 @code{amx_int8},
 @code{amx_bf16},
 @code{amx_tile},
@@ -1491,7 +1492,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
 @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
-@item @samp{.cmpccxadd}
+@item @samp{.cmpccxadd} @tab @samp{.rao_int}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index fb2e2aa446..1eb0eabb6b 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -486,6 +486,8 @@ if [gas_32_check] then {
     run_dump_test "avx-ne-convert"
     run_dump_test "avx-ne-convert-intel"
     run_list_test "cmpccxadd-inval"
+    run_dump_test "raoint"
+    run_dump_test "raoint-intel"
     run_list_test "sg"
     run_dump_test "clzero"
     run_dump_test "invlpgb"
@@ -1162,6 +1164,8 @@ if [gas_64_check] then {
     run_dump_test "x86-64-avx-ne-convert-intel"
     run_dump_test "x86-64-cmpccxadd"
     run_dump_test "x86-64-cmpccxadd-intel"
+    run_dump_test "x86-64-raoint"
+    run_dump_test "x86-64-raoint-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d
new file mode 100644
index 0000000000..2c22b9c8d0
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 RAO_INT insns (Intel disassembly)
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    DWORD PTR \[eax\],edx
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   DWORD PTR \[eax\],edx
diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d
new file mode 100644
index 0000000000..4a6a4e9b21
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 RAO_INT insns
+#source: raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand   %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor    %edx,\(%eax\)
+\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor   %edx,\(%eax\)
diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s
new file mode 100644
index 0000000000..63398dfb82
--- /dev/null
+++ b/gas/testsuite/gas/i386/raoint.s
@@ -0,0 +1,15 @@
+# Check 32bit AVX-NE-CONVERT instructions
+
+	.allow_index_reg
+	.text
+_start:
+        aadd    %edx, (%eax)     #RAO-INT
+        aand    %edx, (%eax)     #RAO-INT
+        aor     %edx, (%eax)     #RAO-INT
+        axor    %edx, (%eax)     #RAO-INT
+
+.intel_syntax noprefix
+        aadd    DWORD PTR [eax], %edx    #RAO-INT
+        aand    DWORD PTR [eax], %edx    #RAO-INT
+        aor     DWORD PTR [eax], %edx    #RAO-INT
+        axor    DWORD PTR [eax], %edx    #RAO-INT
diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
new file mode 100644
index 0000000000..5b5c9051ac
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 RAO_INT insns (Intel disassembly)
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    QWORD PTR \[rax\],rdx
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   QWORD PTR \[rax\],rdx
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d
new file mode 100644
index 0000000000..ccdf027737
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 RAO_INT insns
+#source: x86-64-raoint.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand   %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor    %rdx,\(%rax\)
+\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor   %rdx,\(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s
new file mode 100644
index 0000000000..645bcfc3c4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-raoint.s
@@ -0,0 +1,15 @@
+# Check 64bit RAO_INT instructions
+
+	.allow_index_reg
+	.text
+_start:
+        aadd    %rdx, (%rax)     #RAO-INT
+        aand    %rdx, (%rax)     #RAO-INT
+        aor     %rdx, (%rax)     #RAO-INT
+        axor    %rdx, (%rax)     #RAO-INT
+
+.intel_syntax noprefix
+        aadd    QWORD PTR [rax], %rdx    #RAO-INT
+        aand    QWORD PTR [rax], %rdx    #RAO-INT
+        aor     QWORD PTR [rax], %rdx    #RAO-INT
+        axor    QWORD PTR [rax], %rdx    #RAO-INT
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 1dc96636a4..dba5369e32 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1070,6 +1070,7 @@ enum
   PREFIX_0F38F8,
   PREFIX_0F38FA,
   PREFIX_0F38FB,
+  PREFIX_0F38FC,
   PREFIX_0F3A0F,
   PREFIX_VEX_0F10,
   PREFIX_VEX_0F11,
@@ -3582,6 +3583,14 @@ static const struct dis386 prefix_table[][4] = {
     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
   },
 
+  /* PREFIX_0F38FC */
+  {
+    { "aadd",	{ Edq, Gdq }, 0 },
+    { "axor",	{ Edq, Gdq }, 0 },
+    { "aand",	{ Edq, Gdq }, 0 },
+    { "aor",	{ Edq, Gdq }, 0 },
+  },
+
   /* PREFIX_0F3A0F */
   {
     { Bad_Opcode },
@@ -4783,7 +4792,7 @@ static const struct dis386 three_byte_table[][256] = {
     { MOD_TABLE (MOD_0F38F9) },
     { PREFIX_TABLE (PREFIX_0F38FA) },
     { PREFIX_TABLE (PREFIX_0F38FB) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38FC) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index eca1b729ae..68269bf909 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -253,6 +253,8 @@ static initializer cpu_flag_init[] =
     "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
   { "CPU_CMPCCXADD_FLAGS",
     "CpuCMPCCXADD" },
+  { "CPU_RAO_INT_FLAGS",
+    "CpuRAO_INT" },
   { "CPU_IAMCU_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
   { "CPU_ADX_FLAGS",
@@ -455,6 +457,8 @@ static initializer cpu_flag_init[] =
     "CpuAVX_NE_CONVERT" },
   { "CPU_ANY_CMPCCXADD_FLAGS",
     "CpuCMPCCXADD" },
+  { "CPU_ANY_RAO_INT_FLAGS",
+    "CpuRAO_INT" },
 };
 
 static initializer operand_type_init[] =
@@ -660,6 +664,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuAVX_VNNI_INT8),
   BITFIELD (CpuAVX_NE_CONVERT),
   BITFIELD (CpuCMPCCXADD),
+  BITFIELD (CpuRAO_INT),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index a8c8c67834..53475465b6 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -217,6 +217,8 @@ enum
   CpuAVX_NE_CONVERT,
   /* Intel CMPccXADD instructions support required.  */
   CpuCMPCCXADD,
+  /* Intel RAO INT Instructions support required.  */
+  CpuRAO_INT,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -298,7 +300,7 @@ enum
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
-// #define CpuUnused	(CpuMax + 1)
+#define CpuUnused	(CpuMax + 1)
 
 /* We can check if an instruction is available with array instead
    of bitfield. */
@@ -400,6 +402,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx_vnni_int8:1;
       unsigned int cpuavx_ne_convert:1;
       unsigned int cpucmpccxadd:1;
+      unsigned int cpurao_int:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1bb6bc8966..b1727afb46 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3298,3 +3298,12 @@ vcvtneps2bf16<Vxy>, 0xf372, None, CpuAVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|V
 cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
 
 // CMPCCXADD instructions end.
+
+// RAO-INT instructions.
+
+aadd, 0xf38fc, None, CpuRAO_INT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aand, 0x660f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+
+// RAO-INT instructions end.
-- 
2.18.1

