> >  gas/testsuite/gas/i386/x86-64-lockbad-1.l     |  104 +-
> >  gas/testsuite/gas/i386/x86-64-lockbad-1.s     |    4 +
> 
> As for earlier patches I question the additions here. The purpose of this test
> (and its 32-bit counterpart) isn't to cover all insns not valid with LOCK, but just
> forms of insns which _may_ allow for LOCK. (But yes, these tests aren't really
> complete.)
> 
Done.

> Note also how your ChangeLog entry doesn't mention tests you're altering.
> You're not required anymore to provide ChangeLog entries, but if you do I
> think they will want to match the actual patch.
> 
Done.

> >        /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> >  	 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> > -	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote.  */
> > +	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
> > +	 prefetchit1.  */
> >        if (i.tm.opcode_modifier.anysize)
> >  	return 0;
> 
> Rather than further increasing the comment volume (and hence making it
> harder to recognize quickly what is or is not covered here), may I suggest to
> fold all mentioning of prefetches here into a single "prefetch*"?
> 
Done.

> 
> This is the disassembler side test. An assembler side counterpart is needed
> as well, which I assume will point out that you also need to make another
> change to the assembler (to actually reject non-RIP- relative addressing).
> 
Added warning for illegal input of PREFECHI

> > @@ -1297,6 +1300,8 @@ enum
> >    X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
> >    X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
> >    X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
> > +  X86_64_MOD_0F18_REG_6,
> > +  X86_64_MOD_0F18_REG_7,
> 
> X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0
> respectively.
Done.

> > +    { "nopQ",		{ Ev }, 0 },
> > +    { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
> > +  },
> 
> Nit: Please use consistent padding (tabs) after the first comma each.
Done.

> > +    {
> > +      if (ins->intel_syntax)
> > +	ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
> > +      else
> > +	ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
> 
> Why "nopl"? There's no NP ahead of the opcode (and you also don't go
> through prefix_table[]), so I expect operand size should be expressed here
> correctly.
I changed it to nop.

> With the restriction to RIP-relative addressing I think a better form of
> expressing such operands would be along the lines of CALL/JMP:
> 
> 	prefetchit0 code_label
> 	...
> code_label:
> 
> I think it should be suggested to those having defined the ISA extension to at
> least permit assemblers to support this form (and then do so here, along
> with the present forms, unless the doc was changed to _only_ allow for the
> alternative form).
> 
Regarding this code_lable , I suppose we can't support it for a short time.
@ H.J what do you think of this place? Thanks.



Subject: [PATCH] Support Intel PREFETCHI

gas/ChangeLog:

	* NEWS: Add support for Intel PREFETCHI instruction.
	* config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches.
	(check_VecOperands): Add warning for illegal input of PREFETCHI.
	* doc/c-i386.texi: Document .prefetchi.
	* testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
	* testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI.
	* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetch.d: New test.
	* testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise..
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.s: Likewise.

opcodes/ChangeLog:

	* i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7
	(x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0.
	(mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
	(PREFETCHI_Fixup): New.
	* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS.
	(cpu_flags): Add CpuPREFETCHI.
	(struct): Add RegRIP.
	* i386-opc.h (CpuPREFETCHI): New.
	(i386_cpu_flags): Add cpuprefetchi.
	* i386-opc.tbl: Add Intel PREFETCHI instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
---
 gas/NEWS                                      |  2 +
 gas/config/tc-i386.c                          | 13 ++++--
 gas/doc/c-i386.texi                           |  3 +-
 gas/testsuite/gas/i386/i386.exp               |  3 ++
 gas/testsuite/gas/i386/x86-64-lfence-load.d   |  2 +
 gas/testsuite/gas/i386/x86-64-lfence-load.s   |  2 +
 gas/testsuite/gas/i386/x86-64-prefetch.d      |  4 +-
 .../gas/i386/x86-64-prefetchi-intel.d         | 16 +++++++
 .../i386/x86-64-prefetchi-inval-register.d    | 13 ++++++
 .../i386/x86-64-prefetchi-inval-register.s    |  9 ++++
 .../gas/i386/x86-64-prefetchi-warn.l          |  5 +++
 .../gas/i386/x86-64-prefetchi-warn.s          | 11 +++++
 gas/testsuite/gas/i386/x86-64-prefetchi.d     | 15 +++++++
 gas/testsuite/gas/i386/x86-64-prefetchi.s     | 14 ++++++
 opcodes/i386-dis.c                            | 43 ++++++++++++++++++-
 opcodes/i386-gen.c                            |  4 ++
 opcodes/i386-opc.h                            |  4 ++
 opcodes/i386-opc.tbl                          |  8 ++++
 18 files changed, 163 insertions(+), 8 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
 create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.s

diff --git a/gas/NEWS b/gas/NEWS
index 961449545d..5eb479f5a1 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for Intel PREFETCHI instructions.
+
 * Add support for Intel AMX-FP16 instructions.
 
 * Add support for Intel MSRLIST instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c1623f216e..67cc61a7e7 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (rao_int, RAO_INT, RAO_INT, false),
   SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
   SUBARCH (msrlist, MSRLIST, MSRLIST, false),
+  SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false),
 };
 
 #undef SUBARCH
@@ -4520,9 +4521,8 @@ load_insn_p (void)
 
   if (!any_vex_p)
     {
-      /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
-	 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
-	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote.  */
+      /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
+	 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote.  */
       if (i.tm.opcode_modifier.anysize)
 	return 0;
 
@@ -6363,6 +6363,13 @@ check_VecOperands (const insn_template *t)
 	    i.types[op].bitfield.disp8 = 0;
 	  }
     }
+  /* Check if IP-relative addressing requirements can be satisfied.  */
+  for (op = 0; op < t->operands; op++)
+    {
+      if (t->operand_types[op].bitfield.instance == RegRIP
+	  && !(i.base_reg && i.base_reg->reg_num == RegIP))
+	as_warn (_("only support RIP-relative address"));
+    }
 
   i.memshift = 0;
 
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index b33f17c698..fae902c034 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -201,6 +201,7 @@ accept various extension mnemonics.  For example,
 @code{rao_int},
 @code{wrmsrns},
 @code{msrlist},
+@code{prefetchi},
 @code{amx_int8},
 @code{amx_bf16},
 @code{amx_fp16},
@@ -1496,7 +1497,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
 @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
 @item @samp{.cmpccxadd} @tab @samp{.rao_int} @tab @samp{.wrmsrns}
-@item @samp{.msrlist}
+@item @samp{.msrlist} @tab @samp{.prefetchi}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9f5fa7f612..80bd2835ca 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1209,6 +1209,9 @@ if [gas_64_check] then {
     run_dump_test "x86-64-tdx"
     run_dump_test "x86-64-tsxldtrk"
     run_dump_test "x86-64-hreset"
+    run_dump_test "x86-64-prefetchi"
+    run_dump_test "x86-64-prefetchi-intel"
+    run_dump_test "x86-64-prefetchi-inval-register"
     run_dump_test "x86-64-vp2intersect"
     run_dump_test "x86-64-vp2intersect-intel"
     run_list_test "x86-64-vp2intersect-inval-bcast"
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d
index 2af86fc93f..17c3b9f286 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.d
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d
@@ -33,6 +33,8 @@ Disassembly of section .text:
  +[a-f0-9]+:	0f 18 55 00          	prefetcht1 0x0\(%rbp\)
  +[a-f0-9]+:	0f 18 5d 00          	prefetcht2 0x0\(%rbp\)
  +[a-f0-9]+:	0f 0d 4d 00          	prefetchw 0x0\(%rbp\)
+ +[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+ +[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
  +[a-f0-9]+:	0f a1                	pop    %fs
  +[a-f0-9]+:	0f ae e8             	lfence
  +[a-f0-9]+:	9d                   	popf
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s
index 2a3ac6b7d2..c478082416 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.s
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s
@@ -20,6 +20,8 @@ _start:
 	prefetcht1 (%rbp)
 	prefetcht2 (%rbp)
 	prefetchw (%rbp)
+	prefetchit0 0x12345678(%rip)
+	prefetchit1 0x12345678(%rip)
 	pop %fs
 	popf
 	xlatb (%rbx)
diff --git a/gas/testsuite/gas/i386/x86-64-prefetch.d b/gas/testsuite/gas/i386/x86-64-prefetch.d
index 121592b6ec..246e296956 100644
--- a/gas/testsuite/gas/i386/x86-64-prefetch.d
+++ b/gas/testsuite/gas/i386/x86-64-prefetch.d
@@ -23,5 +23,5 @@ Disassembly of section .text:
 \s*[a-f0-9]+:	0f 18 18             	prefetcht2 \(%rax\)
 \s*[a-f0-9]+:	0f 18 20             	nopl   \(%rax\)
 \s*[a-f0-9]+:	0f 18 28             	nopl   \(%rax\)
-\s*[a-f0-9]+:	0f 18 30             	nopl   \(%rax\)
-\s*[a-f0-9]+:	0f 18 38             	nopl   \(%rax\)
+\s*[a-f0-9]+:	0f 18 30             	nop    \(%rax\)
+\s*[a-f0-9]+:	0f 18 38             	nop    \(%rax\)
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
new file mode 100644
index 0000000000..7f72f0a1eb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dwMintel
+#name: x86-64 PREFETCHI insns (Intel disassembly)
+#source: x86-64-prefetchi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
new file mode 100644
index 0000000000..4c2f19b697
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI INVAL REGISTER insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <\.text>:
+[ 	]*[a-f0-9]+:[ 	]0f 18 39[ 	]*nop    \(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]0f 18 31[ 	]*nop    \(%rcx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
new file mode 100644
index 0000000000..550449a0c9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
@@ -0,0 +1,9 @@
+.text
+        #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs.
+        .byte 0x0f
+        .byte 0x18
+        .byte 0x39
+        #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs.
+        .byte 0x0f
+        .byte 0x18
+        .byte 0x31
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
new file mode 100644
index 0000000000..4e15389463
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:[0-9]*: Warning: only support RIP-relative address
+.*:[0-9]*: Warning: only support RIP-relative address
+.*:[0-9]*: Warning: only support RIP-relative address
+.*:[0-9]*: Warning: only support RIP-relative address
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
new file mode 100644
index 0000000000..330ff31c75
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
@@ -0,0 +1,11 @@
+# Check error for ICACHE-PREFETCH 64-bit instruction
+
+	.allow_index_reg
+	.text
+_start:
+	prefetchit0     0x12345678(%rax)
+	prefetchit1     0x12345678(%rax)
+
+	.intel_syntax noprefix
+	prefetchit0     BYTE PTR [rax+0x12345678]
+	prefetchit1     BYTE PTR [rax+0x12345678]
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.d b/gas/testsuite/gas/i386/x86-64-prefetchi.d
new file mode 100644
index 0000000000..c8ab92d147
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.d
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.s b/gas/testsuite/gas/i386/x86-64-prefetchi.s
new file mode 100644
index 0000000000..cc7c61e9a9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.s
@@ -0,0 +1,14 @@
+# Check 64bit PREFETCHI instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+        prefetchit0     0x12345678(%rip)
+        prefetchit1     0x12345678(%rip)
+
+        .intel_syntax noprefix
+
+        prefetchit0     BYTE PTR [rip+0x12345678]
+        prefetchit1     BYTE PTR [rip+0x12345678]
+
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 27ae8eaf46..ccf151c2d9 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int);
 
 static void MOVSXD_Fixup (instr_info *, int, int);
 static void DistinctDest_Fixup (instr_info *, int, int);
+static void PREFETCHI_Fixup (instr_info *, int, int);
 
 /* This character is used to encode style information within the output
    buffers.  See oappend_insert_style for more details.  */
@@ -841,6 +842,8 @@ enum
   MOD_0F18_REG_1,
   MOD_0F18_REG_2,
   MOD_0F18_REG_3,
+  MOD_0F18_REG_6,
+  MOD_0F18_REG_7,
   MOD_0F1A_PREFIX_0,
   MOD_0F1B_PREFIX_0,
   MOD_0F1B_PREFIX_1,
@@ -1280,6 +1283,8 @@ enum
   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
+  X86_64_0F18_REG_6_MOD_0,
+  X86_64_0F18_REG_7_MOD_0,
   X86_64_0F24,
   X86_64_0F26,
   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
@@ -2751,8 +2756,8 @@ static const struct dis386 reg_table[][8] = {
     { MOD_TABLE (MOD_0F18_REG_3) },
     { "nopQ",		{ Ev }, 0 },
     { "nopQ",		{ Ev }, 0 },
-    { "nopQ",		{ Ev }, 0 },
-    { "nopQ",		{ Ev }, 0 },
+    { MOD_TABLE (MOD_0F18_REG_6) },
+    { MOD_TABLE (MOD_0F18_REG_7) },
   },
   /* REG_0F1C_P_0_MOD_0 */
   {
@@ -4394,6 +4399,18 @@ static const struct dis386 x86_64_table[][2] = {
     { "psmash",	{ Skip_MODRM }, 0 },
   },
 
+  /* X86_64_0F18_REG_6_MOD_0 */
+  {
+    { "nopQ",		{ Ev }, 0 },
+    { "prefetchit1",	{ { PREFETCHI_Fixup, b_mode } }, 0 },
+  },
+
+  /* X86_64_0F18_REG_7_MOD_0 */
+  {
+    { "nopQ",		{ Ev }, 0 },
+    { "prefetchit0",	{ { PREFETCHI_Fixup, b_mode } }, 0 },
+  },
+
   {
     /* X86_64_0F24 */
     { "movZ",		{ Em, Td }, 0 },
@@ -8193,6 +8210,16 @@ static const struct dis386 mod_table[][2] = {
     { "prefetcht2",	{ Mb }, 0 },
     { "nopQ",		{ Ev }, 0 },
   },
+  {
+    /* MOD_0F18_REG_6 */
+    { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
+    { "nopQ",		{ Ev }, 0 },
+  },
+  {
+    /* MOD_0F18_REG_7 */
+    { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
+    { "nopQ",		{ Ev }, 0 },
+  },
   {
     /* MOD_0F1A_PREFIX_0 */
     { "bndldx",		{ Gbnd, Mv_bnd }, 0 },
@@ -13940,3 +13967,15 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
     }
   oappend (ins, "sae}");
 }
+
+static void
+PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
+{
+  if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
+    {
+      ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
+      bytemode = v_mode;
+    }
+
+  OP_M (ins, bytemode, sizeflag);
+}
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 237f147ad4..60ec3504dd 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
     "CpuWRMSRNS" },
   { "CPU_MSRLIST_FLAGS",
     "CpuMSRLIST" },
+  { "CPU_PREFETCHI_FLAGS",
+    "CpuPREFETCHI"},
   { "CPU_IAMCU_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
   { "CPU_ADX_FLAGS",
@@ -677,6 +679,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuRAO_INT),
   BITFIELD (CpuWRMSRNS),
   BITFIELD (CpuMSRLIST),
+  BITFIELD (CpuPREFETCHI),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
@@ -802,6 +805,7 @@ static const struct {
     INSTANCE (RegC),
     INSTANCE (RegD),
     INSTANCE (RegB),
+    INSTANCE (RegRIP),
 };
 
 #undef INSTANCE
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 645abe7f34..9e4931530a 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -223,6 +223,8 @@ enum
   CpuWRMSRNS,
   /* Intel MSRLIST Instructions support required.  */
   CpuMSRLIST,
+  /* PREFETCHI instruction required */
+  CpuPREFETCHI,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -411,6 +413,7 @@ typedef union i386_cpu_flags
       unsigned int cpurao_int:1;
       unsigned int cpuwrmsrns:1;
       unsigned int cpumsrlist:1;
+      unsigned int cpuprefetchi:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
@@ -814,6 +817,7 @@ enum operand_instance
   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
   RegB,  /* %bl / %bx / %ebx / %rbx */
+  RegRIP,  /* %rip */
 };
 
 /* Position of operand_type bits.  */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index bb5dc6799d..370dc10b9e 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -40,6 +40,7 @@
 #define RegC Instance=RegC
 #define RegD Instance=RegD
 #define RegB Instance=RegB
+#define RegRIP Instance=RegRIP
 
 #define ShiftCount   RegC|Byte
 #define InOutPortReg RegD|Word
@@ -3323,3 +3324,10 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 
 // MSRLIST instructions end.
+
+// PREFETCHI instructions.
+
+prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegRIP|BaseIndex }
+prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegRIP|BaseIndex }
+
+// PREFETCHI instructions end.
-- 
2.17.1
Thanks,
Lili.