From: "Hu, Lin1" <lin1.hu@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>, Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: RE: [PATCH] x86: allow 32-bit reg to be used with U{RD,WR}MSR
Date: Mon, 4 Dec 2023 01:45:04 +0000 [thread overview]
Message-ID: <SJ0PR11MB5940D57B799081597108FED0A686A@SJ0PR11MB5940.namprd11.prod.outlook.com> (raw)
In-Reply-To: <90620ac0-6f37-4fdc-b9be-1e01950a081d@suse.com>
I talked to the people involved. They found the eds description about "ignoring h32 bits of the MSR address for register variants" is a documentation bug. The right version is USER_MSR have a GP fault on h32 of the MSR address for the register version. So they update the description from #GP(0) If MSR_address[63:0] & 0x0000_0000_FFFF_C000 != 0
to #GP(0) If MSR_address[63:0] & 0xFFFF_FFFF_FFFF_C000 != 0. And the source register will still be r64 in the spec.
BRs,
Lin
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, November 24, 2023 5:18 PM
> To: Binutils <binutils@sourceware.org>
> Cc: H.J. Lu <hjl.tools@gmail.com>; Hu, Lin1 <lin1.hu@intel.com>
> Subject: [PATCH] x86: allow 32-bit reg to be used with U{RD,WR}MSR
>
> ... as MSR index specifier: It is unreasonable to demand that people write
> less readable / understandable code, just because the present
> documentation mentions only Reg64. Whether to also adjust the
> disassembler is a separate question, perhaps indeed more tightly tied to
> what the spec says.
>
> --- a/gas/testsuite/gas/i386/x86-64-user_msr.s
> +++ b/gas/testsuite/gas/i386/x86-64-user_msr.s
> @@ -5,7 +5,7 @@ _start:
> urdmsr %r14, %r12
> urdmsr %r14, %rax
> urdmsr %rdx, %r12
> - urdmsr %rdx, %rax
> + urdmsr %edx, %rax
> urdmsr $51515151, %r12
> urdmsr $51515151, %rax
> urdmsr $0x7f, %r12
> @@ -14,7 +14,7 @@ _start:
> uwrmsr %r12, %r14
> uwrmsr %rax, %r14
> uwrmsr %r12, %rdx
> - uwrmsr %rax, %rdx
> + uwrmsr %rax, %edx
> uwrmsr %r12, $51515151
> uwrmsr %rax, $51515151
> uwrmsr %r12, $0x7f
> @@ -24,7 +24,7 @@ _start:
> .intel_syntax noprefix
> urdmsr r12, r14
> urdmsr rax, r14
> - urdmsr r12, rdx
> + urdmsr r12, edx
> urdmsr rax, rdx
> urdmsr r12, 51515151
> urdmsr rax, 51515151
> @@ -33,7 +33,7 @@ _start:
> urdmsr r12, 0x80000000
> uwrmsr r14, r12
> uwrmsr r14, rax
> - uwrmsr rdx, r12
> + uwrmsr edx, r12
> uwrmsr rdx, rax
> uwrmsr 51515151, r12
> uwrmsr 51515151, rax
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3359,9 +3359,9 @@ eretu, 0xf30f01ca, FRED, NoSuf, {}
>
> // USER_MSR instructions.
>
> -urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 }
> +urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg32|Reg64,
> +Reg64 }
> urdmsr, 0xf2f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf,
> { Imm32, Reg64 } -uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64,
> { Reg64, Reg64 }
> +uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64,
> Reg32|Reg64
> +}
> // Immediates want to be first; md_assemble() takes care of swapping
> operands // accordingly.
> uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf,
> { Imm32, Reg64 }
next prev parent reply other threads:[~2023-12-04 1:45 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-24 9:18 Jan Beulich
2023-12-04 1:45 ` Hu, Lin1 [this message]
2023-12-04 7:17 ` Jan Beulich
2023-12-12 7:13 ` Hu, Lin1
2023-12-12 8:13 ` Jan Beulich
2023-12-12 8:51 ` Hu, Lin1
2023-12-12 9:20 ` Jan Beulich
2023-12-13 2:23 ` Hu, Lin1
2023-12-13 6:59 ` Jan Beulich
2023-12-13 8:40 ` Hu, Lin1
2023-12-13 8:50 ` Jan Beulich
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