[PATCH v3] RISC-V: Add support for svvptc extension.

[PATCH v3] RISC-V: Add support for svvptc extension.

[chendongyan]

[-- Attachment #1: Type: text/plain, Size: 2860 bytes --]

This implements the svvptc extensons, version 1.0[1].

[1] https://github.com/riscv/riscv-svvptc

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_multi_subset_supports): Handle svvptc.
        (riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

        * NEWS: Updated.
        * testsuite/gas/riscv/march-help.l: Ditto.

modify gas/NEWS
---
 bfd/elfxx-riscv.c                    | 5 +++++
 gas/NEWS                             | 2 ++
 gas/testsuite/gas/riscv/march-help.l | 1 +
 3 files changed, 8 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 701c7242920..44484f12967 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1459,6 +1459,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"svinval",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svnapot",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svpbmt",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"svvptc",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };

@@ -2726,6 +2727,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zcmt");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
+    case INSN_CLASS_SVVPTC:
+      return riscv_subset_supports (rps, "svvptc");
     case INSN_CLASS_H:
       return riscv_subset_supports (rps, "h");
     case INSN_CLASS_XCVALU:
@@ -3010,6 +3013,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zcmt";
     case INSN_CLASS_SVINVAL:
       return "svinval";
+    case INSN_CLASS_SVVPTC:
+      return "svvptc";
     case INSN_CLASS_H:
       return _("h");
     case INSN_CLASS_XCVALU:
diff --git a/gas/NEWS b/gas/NEWS
index 67ca298d11e..848e7c14878 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -9,6 +9,8 @@
 * Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi and CORE-V
   (xcvbitmanip, xcvsimd) extensions with version 1.0.

+  Add support for the RISC-V svvptc extension, version 1.0.
+
 Changes in 2.43:

 * Add support for LoongArch .option for fine-grained control of assembly
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 4234b05598f..011bd6fea19 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -133,6 +133,7 @@ All available -march extensions for RISC-V:
         svinval                                 1.0
         svnapot                                 1.0
         svpbmt                                  1.0
+       svvptc                                  1.0
         xcvalu                                  1.0
         xcvbi                                   1.0
         xcvbitmanip                             1.0
--
2.43.0