* [Patch, AArch64, Binutils] Make hint space instructions valid for Armv8-a
@ 2020-04-16 14:57 Sudakshina Das
2020-04-17 14:09 ` Nick Clifton
0 siblings, 1 reply; 3+ messages in thread
From: Sudakshina Das @ 2020-04-16 14:57 UTC (permalink / raw)
To: binutils; +Cc: nickc, Richard Earnshaw
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Hi
There are a few instruction in AArch64 that are in the HINT space. Any of these instructions should
be accepted by the assembler/disassembler at any architecture version. This patch fixes the existing
instructions that are not behaving accordingly.
I have used all of the instructions mentioned in the following to make the changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/hint-hint-instruction
Build and regression tested on aarch64-none-linux-gnu.
Is this okay for trunk and a backport for 2.34?
Thanks
Sudi
PS: I have not added the regenerated files to the patch to make it easier for review. I will add them
to the final commit.
gas/ChangeLog:
2020-xx-xx Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/bti.d: Update -march option.
* testsuite/gas/aarch64/illegal-bti.d: Remove.
* testsuite/gas/aarch64/illegal-bti.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
opcodes/ChangeLog:
2020-xx-xx Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
(aarch64_feature_ras, RAS): Likewise.
(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
autiaz, autiasp, autibz, autibsp to be CORE_INSN.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
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diff --git a/gas/testsuite/gas/aarch64/bti.d b/gas/testsuite/gas/aarch64/bti.d
index e1ac7005dff4b3130759eea5fff88f0cea62f66b..434efa32cde1ea814838d6876cd54af6dd579e9f 100644
--- a/gas/testsuite/gas/aarch64/bti.d
+++ b/gas/testsuite/gas/aarch64/bti.d
@@ -1,4 +1,4 @@
-#as: -march=armv8.5-a
+#as: -march=armv8-a
#objdump: -dr
.*: file format .*
diff --git a/gas/testsuite/gas/aarch64/illegal-bti.d b/gas/testsuite/gas/aarch64/illegal-bti.d
deleted file mode 100644
index 174d97a0376771d02a197bca7d59b74fb504102e..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/illegal-bti.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=armv8-a
-#source: bti.s
-#error_output: illegal-bti.l
diff --git a/gas/testsuite/gas/aarch64/illegal-bti.l b/gas/testsuite/gas/aarch64/illegal-bti.l
deleted file mode 100644
index d18f8c57d293cedf2d3e79883173eb0c54765a6e..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/illegal-bti.l
+++ /dev/null
@@ -1,8 +0,0 @@
-[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: selected processor does not support `bti'
-[^:]*:[0-9]+: Error: selected processor does not support `bti c'
-[^:]*:[0-9]+: Error: selected processor does not support `bti j'
-[^:]*:[0-9]+: Error: selected processor does not support `bti jc'
-[^:]*:[0-9]+: Error: selected processor does not support `bti C'
-[^:]*:[0-9]+: Error: selected processor does not support `bti J'
-[^:]*:[0-9]+: Error: selected processor does not support `bti JC'
diff --git a/gas/testsuite/gas/aarch64/illegal-ras-1.l b/gas/testsuite/gas/aarch64/illegal-ras-1.l
index e8803e5a71beb860ec764785d462f3bb994a41dd..bf8ca6b98a91eb06edf212d2790838b20222302c 100644
--- a/gas/testsuite/gas/aarch64/illegal-ras-1.l
+++ b/gas/testsuite/gas/aarch64/illegal-ras-1.l
@@ -1,5 +1,4 @@
[^:]+: Assembler messages:
-^[^:]+:[0-9]+: Error: selected processor does not support `esb'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
@@ -18,7 +17,6 @@
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
-^[^:]+:[0-9]+: Error: selected processor does not support `esb'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
diff --git a/gas/testsuite/gas/aarch64/illegal-ras-1.s b/gas/testsuite/gas/aarch64/illegal-ras-1.s
index 5d61fb7896900036336508e0d2f279106d0ba33c..ae85e8d892b5a467b5ab1a75552b2e626a94a618 100644
--- a/gas/testsuite/gas/aarch64/illegal-ras-1.s
+++ b/gas/testsuite/gas/aarch64/illegal-ras-1.s
@@ -12,7 +12,6 @@
/* ARMv8-A. */
.arch armv8-a
- esb
hint #0x10
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
@@ -33,7 +32,6 @@
/* ARMv8.1-A. */
.arch armv8.1-a
- esb
hint #0x10
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 2bc69a38ee0ddad72a4a97cd40c1d4235a6621d1..3c3731d6d0e30e6fa2dc2d144e39ca0bb56d0f91 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2332,16 +2332,12 @@ static const aarch64_feature_set aarch64_feature_lor =
AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
static const aarch64_feature_set aarch64_feature_rdma =
AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
-static const aarch64_feature_set aarch64_feature_ras =
- AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
static const aarch64_feature_set aarch64_feature_v8_2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
static const aarch64_feature_set aarch64_feature_fp_f16 =
AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
static const aarch64_feature_set aarch64_feature_simd_f16 =
AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
-static const aarch64_feature_set aarch64_feature_stat_profile =
- AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
static const aarch64_feature_set aarch64_feature_sve =
AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0);
static const aarch64_feature_set aarch64_feature_v8_3 =
@@ -2379,8 +2375,6 @@ static const aarch64_feature_set aarch64_feature_sb =
AARCH64_FEATURE (AARCH64_FEATURE_SB, 0);
static const aarch64_feature_set aarch64_feature_predres =
AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
-static const aarch64_feature_set aarch64_feature_bti =
- AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
static const aarch64_feature_set aarch64_feature_memtag =
AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0);
static const aarch64_feature_set aarch64_feature_bfloat16 =
@@ -2423,8 +2417,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
#define RDMA &aarch64_feature_rdma
#define FP_F16 &aarch64_feature_fp_f16
#define SIMD_F16 &aarch64_feature_simd_f16
-#define RAS &aarch64_feature_ras
-#define STAT_PROFILE &aarch64_feature_stat_profile
#define ARMV8_2 &aarch64_feature_v8_2
#define SVE &aarch64_feature_sve
#define ARMV8_3 &aarch64_feature_v8_3
@@ -2443,7 +2435,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
#define FRINTTS &aarch64_feature_frintts
#define SB &aarch64_feature_sb
#define PREDRES &aarch64_feature_predres
-#define BTI &aarch64_feature_bti
#define MEMTAG &aarch64_feature_memtag
#define TME &aarch64_feature_tme
#define SVE2 &aarch64_feature_sve2
@@ -2518,8 +2509,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
{ NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL }
#define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
-#define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
- { NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -3838,19 +3827,20 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- BTI_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)),
+ CORE_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, 0, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)),
CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS, 0, 0, NULL},
- {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {}, F_ALIAS, 0, 0, NULL},
+ CORE_INSN ("dgh", 0xd50320df, 0xffffffff, ic_system, 0, OP0 (), {}, 0),
+ CORE_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("esb", 0xd503221f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("psb", 0xd503223f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
@@ -3877,14 +3867,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
- V8_3_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
- V8_3_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+ CORE_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
/* Test & branch (immediate). */
CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),
CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),
@@ -5069,9 +5059,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
- /* V8.6 instructions */
- V8_6_INSN("dgh", 0xd50320df, 0xffffffff, aarch64_misc, OP0 (), {}, 0),
-
/* Matrix Multiply instructions. */
INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
INT8MATMUL_SVE_INSNC ("ummla", 0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Patch, AArch64, Binutils] Make hint space instructions valid for Armv8-a
2020-04-16 14:57 [Patch, AArch64, Binutils] Make hint space instructions valid for Armv8-a Sudakshina Das
@ 2020-04-17 14:09 ` Nick Clifton
2020-04-20 10:09 ` Sudakshina Das
0 siblings, 1 reply; 3+ messages in thread
From: Nick Clifton @ 2020-04-17 14:09 UTC (permalink / raw)
To: Sudakshina Das, binutils; +Cc: Richard Earnshaw
Hi Sudi,
> gas/ChangeLog:
> 2020-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * testsuite/gas/aarch64/bti.d: Update -march option.
> * testsuite/gas/aarch64/illegal-bti.d: Remove.
> * testsuite/gas/aarch64/illegal-bti.l: Remove.
> * testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
> * testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
>
> opcodes/ChangeLog:
> 2020-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
> (aarch64_feature_ras, RAS): Likewise.
> (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
> (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
> autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
> autiaz, autiasp, autibz, autibsp to be CORE_INSN.
> * aarch64-asm-2.c: Regenerated.
> * aarch64-dis-2.c: Regenerated.
> * aarch64-opc-2.c: Regenerated.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [Patch, AArch64, Binutils] Make hint space instructions valid for Armv8-a
2020-04-17 14:09 ` Nick Clifton
@ 2020-04-20 10:09 ` Sudakshina Das
0 siblings, 0 replies; 3+ messages in thread
From: Sudakshina Das @ 2020-04-20 10:09 UTC (permalink / raw)
To: nickc, binutils; +Cc: Richard Earnshaw
Hi Nick
> -----Original Message-----
> From: Nick Clifton <nickc@redhat.com>
> Sent: 17 April 2020 15:10
> To: Sudakshina Das <Sudi.Das@arm.com>; binutils@sourceware.org
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>
> Subject: Re: [Patch, AArch64, Binutils] Make hint space instructions valid for
> Armv8-a
>
> Hi Sudi,
>
> > gas/ChangeLog:
> > 2020-xx-xx Sudakshina Das <sudi.das@arm.com>
> >
> > * testsuite/gas/aarch64/bti.d: Update -march option.
> > * testsuite/gas/aarch64/illegal-bti.d: Remove.
> > * testsuite/gas/aarch64/illegal-bti.l: Remove.
> > * testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
> > * testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
> >
> > opcodes/ChangeLog:
> > 2020-xx-xx Sudakshina Das <sudi.das@arm.com>
> >
> > * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
> > (aarch64_feature_ras, RAS): Likewise.
> > (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
> > (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
> > autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
> > autiaz, autiasp, autibz, autibsp to be CORE_INSN.
> > * aarch64-asm-2.c: Regenerated.
> > * aarch64-dis-2.c: Regenerated.
> > * aarch64-opc-2.c: Regenerated.
>
> Approved - please apply.
Thank you. Applied as 8a6e1d1d7. Will wait a few days before backporting.
Sudi
>
> Cheers
> Nick
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-04-16 14:57 [Patch, AArch64, Binutils] Make hint space instructions valid for Armv8-a Sudakshina Das
2020-04-17 14:09 ` Nick Clifton
2020-04-20 10:09 ` Sudakshina Das
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