diff --git a/binutils/testsuite/binutils-all/aarch64/in-order-all.d b/binutils/testsuite/binutils-all/aarch64/in-order-all.d index a484ca7..a6daea8 100644 --- a/binutils/testsuite/binutils-all/aarch64/in-order-all.d +++ b/binutils/testsuite/binutils-all/aarch64/in-order-all.d @@ -10,7 +10,7 @@ Disassembly of section \.func1: .+ : [^:]+: 8b010000 add x0, x0, x1 -[^:]+: 00000000 \.inst 0x00000000 ; undefined +[^:]+: 00000000 udf #0 Disassembly of section \.func2: @@ -25,12 +25,12 @@ Disassembly of section \.func3: [^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1 -[^:]+: 00000000 \.inst 0x00000000 ; undefined +[^:]+: 00000000 udf #0 Disassembly of section \.rodata: .+ <\.rodata>: -[^:]+: 00000000 \.inst 0x00000000 ; undefined +[^:]+: 00000000 udf #0 Disassembly of section .global: diff --git a/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d b/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d index d3aa79e..955d190 100644 --- a/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d +++ b/binutils/testsuite/binutils-all/aarch64/out-of-order-all.d @@ -20,7 +20,7 @@ Disassembly of section \.func1: .+ : [^:]+: 8b010000 add x0, x0, x1 -[^:]+: 00000000 \.inst 0x00000000 ; undefined +[^:]+: 00000000 udf #0 Disassembly of section \.func3: @@ -30,9 +30,9 @@ Disassembly of section \.func3: [^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1 -[^:]+: 00000000 \.inst 0x00000000 ; undefined +[^:]+: 00000000 udf #0 Disassembly of section \.rodata: .+ <\.rodata>: -[^:]+: 00000000 \.inst 0x00000000 ; undefined +[^:]+: 00000000 udf #0 diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 69ccc59..da786ba 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6149,6 +6149,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) break; case AARCH64_OPND_EXCEPTION: + case AARCH64_OPND_UNDEFINED: po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp, imm_reg_type)); assign_imm_if_const_or_fixup_later (&inst.reloc, info, @@ -7745,11 +7746,12 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value) switch (opnd) { case AARCH64_OPND_EXCEPTION: + case AARCH64_OPND_UNDEFINED: if (unsigned_overflow (value, 16)) as_bad_where (fixP->fx_file, fixP->fx_line, _("immediate out of range")); insn = get_aarch64_insn (buf); - insn |= encode_svc_imm (value); + insn |= (opnd == AARCH64_OPND_EXCEPTION) ? encode_svc_imm (value) : value; put_aarch64_insn (buf, insn); break; diff --git a/gas/testsuite/gas/aarch64/udf.d b/gas/testsuite/gas/aarch64/udf.d new file mode 100644 index 0000000..ae6432b --- /dev/null +++ b/gas/testsuite/gas/aarch64/udf.d @@ -0,0 +1,9 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +.*: 0000002a udf #42 +.*: 0000ffff udf #65535 diff --git a/gas/testsuite/gas/aarch64/udf.s b/gas/testsuite/gas/aarch64/udf.s new file mode 100644 index 0000000..fec30a3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/udf.s @@ -0,0 +1,5 @@ +// Test file for AArch64 udf. + +.text +udf #42 +udf #65535 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index c152952..817ca1e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -272,6 +272,7 @@ enum aarch64_opnd AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ AARCH64_OPND_BIT_NUM, /* Immediate. */ AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ + AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for diff --git a/ld/testsuite/ld-aarch64/erratum843419_tls_ie.d b/ld/testsuite/ld-aarch64/erratum843419_tls_ie.d index eba5a20..4d2b111 100644 --- a/ld/testsuite/ld-aarch64/erratum843419_tls_ie.d +++ b/ld/testsuite/ld-aarch64/erratum843419_tls_ie.d @@ -23,10 +23,10 @@ Disassembly of section .e843419: [ ]*20001010: 0b0700e0 add w0, w7, w7 [ ]*20001014: 910043ff add sp, sp, #0x10 [ ]*20001018: d65f03c0 ret -[ ]*2000101c: 00000000 .inst 0x00000000 ; undefined +[ ]*2000101c: 00000000 udf #0 [ ]*20001020: 14000400 b 20002020 [ ]*20001024: d503201f nop -[ ]*20001028: 00000000 .inst 0x00000000 ; undefined +[ ]*20001028: 00000000 udf #0 [ ]*2000102c: 17fffff7 b 20001008 ... diff --git a/ld/testsuite/ld-aarch64/farcall-b-section.d b/ld/testsuite/ld-aarch64/farcall-b-section.d index 7314eaf..40b1072 100644 --- a/ld/testsuite/ld-aarch64/farcall-b-section.d +++ b/ld/testsuite/ld-aarch64/farcall-b-section.d @@ -19,7 +19,7 @@ Disassembly of section .text: 1018: 90040010 adrp x16, 8001000 101c: 91001210 add x16, x16, #0x4 1020: d61f0200 br x16 - 1024: 00000000 .inst 0x00000000 ; undefined + 1024: 00000000 udf #0 .* <___veneer>: 1028: 90040010 adrp x16, 8001000 diff --git a/ld/testsuite/ld-aarch64/farcall-back.d b/ld/testsuite/ld-aarch64/farcall-back.d index fcd0a29..20204ee 100644 --- a/ld/testsuite/ld-aarch64/farcall-back.d +++ b/ld/testsuite/ld-aarch64/farcall-back.d @@ -27,7 +27,7 @@ Disassembly of section .text: 2028: f07ffff0 adrp x16, 100001000 202c: 91002210 add x16, x16, #0x8 2030: d61f0200 br x16 - 2034: 00000000 .inst 0x00000000 ; undefined + 2034: 00000000 udf #0 0000000000002038 <__bar3_veneer>: 2038: 58000090 ldr x16, 2048 <__bar3_veneer\+0x10> diff --git a/ld/testsuite/ld-aarch64/farcall-bl-section.d b/ld/testsuite/ld-aarch64/farcall-bl-section.d index 86b7a0b..b3ed36f 100644 --- a/ld/testsuite/ld-aarch64/farcall-bl-section.d +++ b/ld/testsuite/ld-aarch64/farcall-bl-section.d @@ -19,7 +19,7 @@ Disassembly of section .text: 1018: 90040010 adrp x16, 8001000 101c: 91001210 add x16, x16, #0x4 1020: d61f0200 br x16 - 1024: 00000000 .inst 0x00000000 ; undefined + 1024: 00000000 udf #0 .* <___veneer>: 1028: 90040010 adrp x16, 8001000 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 54701ff..e917d61 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -251,6 +251,7 @@ const aarch64_field fields[] = { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */ { 5, 14 }, /* imm14: in test bit and branch instructions. */ { 5, 16 }, /* imm16: in exception instructions. */ + { 0, 16 }, /* imm16_2: in udf instruction. */ { 0, 26 }, /* imm26: in unconditional branch instructions. */ { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */ { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */ @@ -3357,6 +3358,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_IMM0: case AARCH64_OPND_IMMR: case AARCH64_OPND_IMMS: + case AARCH64_OPND_UNDEFINED: case AARCH64_OPND_FBITS: case AARCH64_OPND_TME_UIMM16: case AARCH64_OPND_SIMM5: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 709d519..a197df6 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -78,6 +78,7 @@ enum aarch64_field_kind FLD_imm12, FLD_imm14, FLD_imm16, + FLD_imm16_2, FLD_imm26, FLD_imms, FLD_immr, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 46c0386..5ad7180 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3354,6 +3354,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), + CORE_INSN ("udf", 0x00000000, 0xffff0000, exception, 0, OP1 (UNDEFINED), {}, 0), CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), @@ -5238,6 +5239,8 @@ struct aarch64_opcode aarch64_opcode_table[] = "the bit number to be tested") \ Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ "a 16-bit unsigned immediate") \ + Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_2), \ + "a 16-bit unsigned immediate") \ Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ "a 5-bit unsigned immediate") \ Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \