From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id D56F63858D1E for ; Thu, 14 Jul 2022 02:09:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D56F63858D1E Received: by mail-pj1-x102e.google.com with SMTP id z12-20020a17090a7b8c00b001ef84000b8bso6727282pjc.1 for ; Wed, 13 Jul 2022 19:09:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=5DpzO/Qkf9ABTJql5Kw0zNkXAjM2Z/axy+4oC+TkEiY=; b=7gNEhtwckKMdU9T59IHU1EfjJIa9eOjRXkrpIzJ1FJJdE4Ao9HgYzHZk+Kxppzzcit ShpL59jgB9XuAwUvGM0ZQm1DPWXYSU4/Vxy4cNaMwLuOsi0wEhSi6MyLBvdHDxl/sn+g 45mTmbFPxEwP17Si6TwlPD3GBXxtHn7In/bDAhbV4Br9z2P+xUDzcsVF8dff4koapRo3 K/lyoJEgd0yfGIq9sfMT2hDY+jDMLj6GZs+pgARnAY+eK4dLSdBnsL0xOf7uUMIi4SzT w3vPq3SYSK4wuavV6lpzOwrjPszgQvqV6GYPZo0JRihs7ldTjgw/vVzNttFwscK5HEH9 hvHg== X-Gm-Message-State: AJIora8RybbECNI2/glLHV4bCWGICJx0T9JLiYIQLBAIuttKJareV3iX zZgU7KokhOTaqJgtmacIFrMgv99LrVE= X-Google-Smtp-Source: AGRyM1v38NFsxVdaAPOxmKQ4+35T2pLM7xRIEB6WceRDFwAYANw0V6tUCH3m3Zj+3szTN/uUjkKGcA== X-Received: by 2002:a17:90b:1d8a:b0:1f0:419f:66b1 with SMTP id pf10-20020a17090b1d8a00b001f0419f66b1mr13906083pjb.119.1657764583887; Wed, 13 Jul 2022 19:09:43 -0700 (PDT) Received: from squeak.grove.modra.org ([2406:3400:51d:8cc0:3d89:8c2d:9f36:23af]) by smtp.gmail.com with ESMTPSA id b10-20020a655cca000000b0040c97f0057dsm67436pgt.17.2022.07.13.19.09.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 19:09:43 -0700 (PDT) Received: by squeak.grove.modra.org (Postfix, from userid 1000) id 9BA661140149; Thu, 14 Jul 2022 11:39:40 +0930 (ACST) Date: Thu, 14 Jul 2022 11:39:40 +0930 From: Alan Modra To: Andrew Burgess Cc: binutils@sourceware.org Subject: Re: [PATCH] libopcodes/ppc: add support for disassembler styling Message-ID: References: <20220712133609.3348690-1-aburgess@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220712133609.3348690-1-aburgess@redhat.com> X-Spam-Status: No, score=-3028.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jul 2022 02:09:46 -0000 On Tue, Jul 12, 2022 at 02:36:09PM +0100, Andrew Burgess via Binutils wrote: > This commit adds disassembler styling to the libopcodes ppc > disassembler. This conversion was pretty straight forward, I just > converted the fprintf_func calls to fprintf_styled_func calls and > added an appropriate style. Thanks for doing this! The patch is OK as-is, but see comments below if you'd like to make some improvements. > For testing the new styling I just assembled then disassembled the > source files in gas/testsuite/gas/ppc and manually checked that the > styling looked reasonable. > > I think the only slightly weird case was how things like '4*cr1+eq' > are styled. As best I can tell, this construct, used for example in > this instruction: > > crand 4*cr1+lt,4*cr1+gt,4*cr1+eq > > is used to access a field of a control register (NOTE: I know very > little about the PPC ISA, so please correct me if I'm wrong). As > such, I have styled the entire construct as a register. In some cases > constructs similar to the above can be simplified to just 'eq', as > this is still referencing a register field, this is still styled as a > register. This field is also present in conditional branches, and looking at those is perhaps is the best way to understand what ought to be done here. eg. this instruction lab: beq 7,lab disassembles with "objdump -d" to beq cr7,0 and with "objdump -d -Mraw" to see the underlying hardware insn bc 12,4*cr7+eq,0 So the field probably ought to disassemble the "4*" and "+" as text, the "eq" the same as the opcode mnemonic, and the "cr7" as a register. At least, that seems a reasonable way to highlight the "interesting bits" to me. > else if ((operand->flags & PPC_OPERAND_UDI) != 0) > - (*info->fprintf_func) (info->stream, "%" PRId64, value); > + (*info->fprintf_styled_func) (info->stream, dis_style_text, > + "%" PRId64, value); I think these are likely best disassembled as registers. I really don't know that much about the Xilinx embedded cpu, but I believe it has these "user defined instructions" where the field is configurable as a register or immediate. -- Alan Modra Australia Development Lab, IBM