From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id E96C5396DC1B for ; Thu, 2 Jun 2022 14:06:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E96C5396DC1B Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 44D1D30008A; Thu, 2 Jun 2022 14:06:43 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Weiwei Li , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [PATCH 5/9] RISC-V: Fix disassembling Zfinx with -M numeric Date: Thu, 2 Jun 2022 23:06:02 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Jun 2022 14:06:46 -0000 This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions. --- gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++ gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++ opcodes/riscv-dis.c | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d new file mode 100644 index 00000000000..ba3f62295eb --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d @@ -0,0 +1,10 @@ +#as: -march=rv64ima_zfinx +#source: zfinx-dis-numeric.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12 diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s new file mode 100644 index 00000000000..b55cbd56b21 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s @@ -0,0 +1,2 @@ +target: + feq.s a0, a1, a2 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 9ff31167775..164fd209dbd 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) /* If arch has ZFINX flags, use gpr for disassemble. */ if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names_abi; + riscv_fpr_names = riscv_gpr_names; for (; op->name; op++) { -- 2.34.1