From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp23.cstnet.cn [159.226.251.23]) by sourceware.org (Postfix) with ESMTP id 8FE283858C53 for ; Tue, 12 Jul 2022 08:38:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8FE283858C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [192.168.2.196] (unknown [180.102.239.252]) by APP-03 (Coremail) with SMTP id rQCowAD3F73vMs1ipI5ADA--.20565S3; Tue, 12 Jul 2022 16:38:08 +0800 (CST) Message-ID: Date: Tue, 12 Jul 2022 16:38:07 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 To: research_trasio@irq.a4lg.com References: <35cfcc212b8742ebb0733f4f7b4c058f75e35d2a.1657351137.git.research_trasio@irq.a4lg.com> Subject: Re: [PATCH 1/3] RISC-V: Add 'M' extension testcases From: =?UTF-8?B?5buW5LuV5Y2O?= Cc: binutils@sourceware.org In-Reply-To: <35cfcc212b8742ebb0733f4f7b4c058f75e35d2a.1657351137.git.research_trasio@irq.a4lg.com> X-CM-TRANSID: rQCowAD3F73vMs1ipI5ADA--.20565S3 X-Coremail-Antispam: 1UD129KBjvJXoWxZr4rWFyUAr4rCF4DCFWkXrb_yoWruw4Upr WUGF1akrZ5GFnrJrZxKryUWF4DXF48urn09w1SvF1IkFWftFW0y3s5tws29F48tr4xCwsa va18ArW5ur15GFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkSb7Iv0xC_Zr1lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4 vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAv7VC0I7IY x2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Cr0_Gr1UMcvjeVCFs4IE7xkEbVWUJVW8Jw ACjcxG0xvEwIxGrwCjr7xvwVCIw2I0I7xG6c02F41lc7I2V7IY0VAS07AlzVAYIcxG8wCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r106r 1rMI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr 1lIxAIcVCF04k26cxKx2IYs7xG6rW3Jr0E3s1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAI cVC2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxUFuc_UUUUU X-Originating-IP: [180.102.239.252] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAwQFEWKY1kQMHAAAsr X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, NICE_REPLY_A, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jul 2022 08:38:17 -0000 > This commit adds basic 'M' (multiply/divide) extension testcases. > > gas/ChangeLog: > > * testsuite/gas/riscv/m-ext.s: New test. > * testsuite/gas/riscv/m-ext-32.d: New test (RV32). > * testsuite/gas/riscv/m-ext-64.d: New test (RV64). > * testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure > by using RV64-only instructions in RV32). > * testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise. > --- > gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++++ > gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++++++ > gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 ++++ > gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++ > gas/testsuite/gas/riscv/m-ext.s | 21 ++++++++++++++++++ > 5 files changed, 72 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d > create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l > create mode 100644 gas/testsuite/gas/riscv/m-ext.s > > diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d > new file mode 100644 > index 00000000000..fe2ef9af54b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/m-ext-32.d > @@ -0,0 +1,18 @@ > +#as: -march=rv32im > +#source: m-ext.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5c533[ ]+div[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5d533[ ]+divu[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5e533[ ]+rem[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5f533[ ]+remu[ ]+a0,a1,a2 > diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d > new file mode 100644 > index 00000000000..6f1c3cd445b > --- /dev/null > +++ b/gas/testsuite/gas/riscv/m-ext-64.d > @@ -0,0 +1,23 @@ > +#as: -march=rv64im -defsym __64_bit__=1 > +#source: m-ext.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5c533[ ]+div[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5d533[ ]+divu[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5e533[ ]+rem[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5f533[ ]+remu[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5853b[ ]+mulw[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5c53b[ ]+divw[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5d53b[ ]+divuw[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5e53b[ ]+remw[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+02c5f53b[ ]+remuw[ ]+a0,a1,a2 > diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d > new file mode 100644 > index 00000000000..cf254cbc476 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d > @@ -0,0 +1,4 @@ > +#as: -march=rv32im -defsym __64_bit__=1 > +#source: m-ext.s > +#objdump: -d > +#error_output: m-ext-fail-xlen-32.l > diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l > new file mode 100644 > index 00000000000..d65ca4980e6 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l > @@ -0,0 +1,6 @@ > +.*Assembler messages: > +.*: Error: unrecognized opcode `mulw a0,a1,a2' > +.*: Error: unrecognized opcode `divw a0,a1,a2' > +.*: Error: unrecognized opcode `divuw a0,a1,a2' > +.*: Error: unrecognized opcode `remw a0,a1,a2' > +.*: Error: unrecognized opcode `remuw a0,a1,a2' > diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s > new file mode 100644 > index 00000000000..c62317d5a62 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/m-ext.s > @@ -0,0 +1,21 @@ > +target: > + mul a0, a1, a2 > + mulh a0, a1, a2 > + mulhsu a0, a1, a2 > + mulhu a0, a1, a2 > +.ifndef __zmmul__ When gcc use -march=rv*_zmmul, "/*__riscv_zmmul */" will be generated. So, I think use "/*ifndf __riscv_zmmul */" is better > + div a0, a1, a2 > + divu a0, a1, a2 > + rem a0, a1, a2 > + remu a0, a1, a2 > +.endif > + > +.ifdef __64_bit__ Similarly, use "/*__riscv_xlen == 64*/ " would better. > + mulw a0, a1, a2 > +.ifndef __zmmul__ > + divw a0, a1, a2 > + divuw a0, a1, a2 > + remw a0, a1, a2 > + remuw a0, a1, a2 > +.endif > +.endif > -- > 2.34.1