From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id EE1123858D38 for ; Mon, 31 Jul 2023 02:56:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EE1123858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id E477F300089; Mon, 31 Jul 2023 02:56:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1690772198; bh=UhWCWY2Y6GD+cEPbKTUkroB8ZcA8ZqBbRXB18YaGYRE=; h=Message-ID:Date:Mime-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=F2kS6/EM4IaICwmnrtBCUGaXaWatnfO5qBLp9/Lpo89v9emdANQlZwWBDqFUY7UQI Kycdw/akR0MPdq2sV4JW/AFaHZ5E9/a1c5TJiU1l7panY/3YMph8LGh4/4nquNaCLX 8Ryjx8dW9XZkxCZkWVBRi5F1kc9IAtAv8rBl7uIc= Message-ID: Date: Mon, 31 Jul 2023 11:56:36 +0900 Mime-Version: 1.0 Subject: Re: [PATCH v4 1/1] RISC-V: Add platform property/capability extensions Content-Language: en-US To: Palmer Dabbelt Cc: binutils@sourceware.org References: From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Again, I'm not strongly object this decision but I'll note a background before I forget again (and in July, before the thread tree in the Binutils Archives website breaks). My initial patch set (in 2022-11) is approved by Nelson once. But I decided not to commit it because I felt something in the RISC-V Profiles specification will likely change (despite it being frozen; and it did, 'Ssptead' was renamed to 'Svade' and 'Sscounterenw' was added). I'm **not** going through using this approval since it's too old. But I will appreciate if you consider this a little. As I replied earlier, I can wait until RISC-V Profiles through "-march" is supported. Thanks, Tsukasa On 2023/07/26 9:47, Palmer Dabbelt wrote: > On Tue, 25 Jul 2023 17:05:53 PDT (-0700), research_trasio@irq.a4lg.com > wrote: >> From: Tsukasa OI >> >> RISC-V Profiles document defines number of "extensions" that indicate >> certain platform properties/capabilities just like 'Zkt' extension >> from the >> RISC-V cryptography extensions. >> >> This commit defines 20 platform property/capability extensions as defined >> in the RISC-V Profiles documentation. >> >> The only exception: 'Ssstateen' extension is defined separately >> because it >> defines a subset (supervisor/hypervisor view) of the 'Smstateen' >> extension. >> >> This is based on the ratified version of RISC-V Profiles: >> >> >> [Definition] >> >> "Main memory regions": >>     Main memory regions (in contrast to I/O or vacant memory regions) >> with >>     both the cacheability and coherence PMAs. >> >> [New Unprivileged Extensions] >> >> 1.  'Ziccif' >>     "Main memory regions" support instruction fetch and any instruction >>     fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) >>     are atomic. >> 2.  'Ziccrse' >>     "Main memory regions" provide the eventual success guarantee for >>     LR/SC sequence (RsrvEventual). >> 3.  'Ziccamoa' >>     "Main memory regions" support all currently-defined AMO operations >>     including swap, logical and arithmetic operations (AMOArithmetic). >> 4.  'Za64rs' >>     For LR/SC instructions, reservation sets are contiguous, naturally >>     aligned and at most 64-bytes in size. >> 5.  'Za128rs' >>     Likewise, but reservation sets are at most 128-bytes in size. >> 6.  'Zicclsm' >>     Misaligned loads / stores to "main memory regions" are supported. >>     Those include both regular scalar and vector accesses but does not >>     include AMOs and other specialized forms of memory accesses. >> 7.  'Zic64b' >>     Cache blocks are (exactly) 64-bytes in size and naturally aligned. > > IMO we want to stay away from these extensions that are just defined by > a single phrase in the spec.  We're still digging out from the first > rounds of changed specs, trying to start supporting stuff that's not > even been defined is going to just make for another round of headaches. > >> [New Privileged Extensions] >> >> 1.  'Svbare' >>     "satp" mode Bare is supported. >> 2.  'Svade' >>     Page-fault exceptions are raised when a page is accessed when A >> bit is >>     clear, or written when D bit is clear. >> 3.  'Ssccptr' >>     "Main memory regions" support hardware page-table reads. >> 4.  'Sstvecd' >>     "stvec" mode Direct is supported.  When "stvec" mode is Direct, >>     "stvec.BASE" is capable of holding any valid 4-byte aligned address. >> 5.  'Sstvala' >>     "stval" is always written with a nonzero value whenever possible as >>     specified in the Privileged Architecture documentation >>     (version 20211203: see section 4.1.9). >> 6.  'Sscounterenw' >>     For any "hpmcounter" that is not read-only zero, the corresponding >> bit >>     in "scounteren" is writable. >> 7.  'Ssu64xl' >>     "sstatus.UXL" is capable of holding the value 0b10 >>     (UXLEN==64 is supported). >> 8.  'Shcounterenw' >>     Similar to 'Sscounterenw' but the same rule applies to "hcounteren". >> 9.  'Shvstvala' >>     Similar to 'Sstvala' but the same rule applies to "vstval". >> 10. 'Shtvala' >>     "htval" is written with the faulting guest physical address as >> long as >>     permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). >> 11. 'Shvstvecd' >>     Similar to 'Sstvecd' but the same rule applies to "vstvec". >> 12. 'Shvsatpa' >>     All translation modes supported in "satp" are also supported in >> "vsatp". >> 13. 'Shgatpa' >>     For each supported virtual memory scheme SvNN supported in "satp", >> the >>     corresponding "hgatp" SvNNx4 mode is supported.  The "hgatp" mode >> Bare >>     is also supported. >> >> [Implications] >> >> (Due to reservation set size constraints) >> -   'Za64rs' -> 'Za128rs' >> >> (Due to the fact that a privileged "extension" directly refers a CSR) >> -   'Svbare'       -> 'Zicsr' >> -   'Sstvecd'      -> 'Zicsr' >> -   'Sstvala'      -> 'Zicsr' >> -   'Sscounterenw' -> 'Zicsr' >> -   'Ssu64xl'      -> 'Zicsr' >> >> (Due to the fact that a privileged "extension" indirectly depends on >> CSRs) >> -   'Svade' -> 'Zicsr' >> >> (Due to the fact that a privileged "extension" is a hypervisor property) >> -   'Shcounterenw' -> 'H' >> -   'Shvstvala'    -> 'H' >> -   'Shtvala'      -> 'H' >> -   'Shvstvecd'    -> 'H' >> -   'Shvsatpa'     -> 'H' >> -   'Shgatpa'      -> 'H' >> >> bfd/ChangeLog: >> >>     * elfxx-riscv.c >>     (riscv_implicit_subsets): Add 13 implication rules. >>     Reorder 'H' for new 'Sh*' extensions. >>     (riscv_supported_std_z_ext) Add 7 property/capability extensions. >>     (riscv_supported_std_s_ext) Add 13 property/capability extensions. >> --- >>  bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- >>  1 file changed, 34 insertions(+), 1 deletion(-) >> >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c >> index b43d2cfa0fab..47dede91e064 100644 >> --- a/bfd/elfxx-riscv.c >> +++ b/bfd/elfxx-riscv.c >> @@ -1105,7 +1105,6 @@ static struct riscv_implicit_subset >> riscv_implicit_subsets[] = >>    {"g", "zicsr",    check_implicit_always}, >>    {"g", "zifencei",    check_implicit_always}, >>    {"m", "zmmul",    check_implicit_always}, >> -  {"h", "zicsr",    check_implicit_always}, >>    {"q", "d",        check_implicit_always}, >>    {"v", "d",        check_implicit_always}, >>    {"v", "zve64d",    check_implicit_always}, >> @@ -1144,6 +1143,7 @@ static struct riscv_implicit_subset >> riscv_implicit_subsets[] = >>    {"zhinx", "zhinxmin",    check_implicit_always}, >>    {"zhinxmin", "zfinx",    check_implicit_always}, >>    {"zfinx", "zicsr",    check_implicit_always}, >> +  {"za64rs", "za128rs",    check_implicit_always}, >>    {"zk", "zkn",        check_implicit_always}, >>    {"zk", "zkr",        check_implicit_always}, >>    {"zk", "zkt",        check_implicit_always}, >> @@ -1179,10 +1179,23 @@ static struct riscv_implicit_subset >> riscv_implicit_subsets[] = >>    {"smaia", "ssaia",        check_implicit_always}, >>    {"smstateen", "ssstateen",    check_implicit_always}, >>    {"smepmp", "zicsr",        check_implicit_always}, >> +  {"shcounterenw", "h",        check_implicit_always}, >> +  {"shgatpa", "h",        check_implicit_always}, >> +  {"shtvala", "h",        check_implicit_always}, >> +  {"shvsatpa", "h",        check_implicit_always}, >> +  {"shvstvala", "h",        check_implicit_always}, >> +  {"shvstvecd", "h",        check_implicit_always}, >> +  {"h", "zicsr",        check_implicit_always}, >>    {"ssaia", "zicsr",        check_implicit_always}, >>    {"sscofpmf", "zicsr",        check_implicit_always}, >> +  {"sscounterenw", "zicsr",    check_implicit_always}, >>    {"ssstateen", "zicsr",    check_implicit_always}, >>    {"sstc", "zicsr",        check_implicit_always}, >> +  {"sstvala", "zicsr",        check_implicit_always}, >> +  {"sstvecd", "zicsr",        check_implicit_always}, >> +  {"ssu64xl", "zicsr",        check_implicit_always}, >> +  {"svade", "zicsr",        check_implicit_always}, >> +  {"svbare", "zicsr",        check_implicit_always}, >>    {NULL, NULL, NULL} >>  }; >> >> @@ -1240,6 +1253,11 @@ static struct riscv_supported_ext >> riscv_supported_std_ext[] = >> >>  static struct riscv_supported_ext riscv_supported_std_z_ext[] = >>  { >> +  {"zic64b",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> +  {"ziccamoa",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> +  {"ziccif",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> +  {"zicclsm",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> +  {"ziccrse",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >>    {"zicbom",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >>    {"zicbop",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >>    {"zicboz",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> @@ -1250,6 +1268,8 @@ static struct riscv_supported_ext >> riscv_supported_std_z_ext[] = >>    {"zifencei",        ISA_SPEC_CLASS_20190608,    2, 0,  0 }, >>    {"zihintpause",    ISA_SPEC_CLASS_DRAFT,        2, 0,  0 }, >>    {"zmmul",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> +  {"za64rs",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> +  {"za128rs",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >>    {"zawrs",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >>    {"zfa",        ISA_SPEC_CLASS_DRAFT,        0, 1,  0 }, >>    {"zfh",        ISA_SPEC_CLASS_DRAFT,        1, 0,  0 }, >> @@ -1318,13 +1338,26 @@ static struct riscv_supported_ext >> riscv_supported_std_z_ext[] = >> >>  static struct riscv_supported_ext riscv_supported_std_s_ext[] = >>  { >> +  {"shcounterenw",    ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"shgatpa",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"shtvala",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"shvsatpa",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"shvstvala",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"shvstvecd",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"smaia",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"smepmp",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"smstateen",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"ssaia",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"ssccptr",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"sscofpmf",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"sscounterenw",    ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"ssstateen",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"sstc",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"sstvala",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"sstvecd",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"ssu64xl",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"svade",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >> +  {"svbare",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"svinval",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"svnapot",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >>    {"svpbmt",        ISA_SPEC_CLASS_DRAFT,        1, 0, 0 }, >