From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 2/2] RISC-V: remove "b" operand type from disassembler
Date: Sun, 7 Aug 2022 17:00:22 +0900 [thread overview]
Message-ID: <a51ff0c42f1a753a93ba00941cf216c2794e8968.1659859212.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1659859212.git.research_trasio@irq.a4lg.com>
There are a few operand types not used by any RISC-V instructions.
- Cx
- Vf
- Ve
- [
- ]
- b
But most of them has a reasoning to keep them:
- Cx : Same as "Ct" except it has a constraint to have rd == rs2
(similar to "Cw"). Although it hasn't used, its role is clear
enough to implement a new instruction with this operand type.
- Vf, Ve : Used by vector AMO instructions (not ratified and real
instructions are not upstreamed yet).
- [, ] : Unused tokenization symbols. Reserving them is not harmful
and a vendor may use this symbol for special purposes.
... except "b". I could not have found any reference to this operand type
except it works like the "s" operand type. Historically, it seems... it's
just unused from the beginning. Its role is not clear either.
On such cases, we should vacate this room for the new operand type with
much clearer roles.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Remove 'b' operand type.
---
opcodes/riscv-dis.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 164fd209dbd..66276368118 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -394,7 +394,6 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_immediate, "0");
break;
- case 'b':
case 's':
if ((l & MASK_JALR) == MATCH_JALR)
maybe_print_address (pd, rs1, 0, 0);
--
2.34.1
prev parent reply other threads:[~2022-08-07 8:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-07 8:00 [PATCH 0/2] RISC-V: Opcode Tidying - Operands (batch 1) Tsukasa OI
2022-08-07 8:00 ` [PATCH 1/2] RISC-V: Add macro-only operands to validate_riscv_insn Tsukasa OI
2022-08-07 8:00 ` Tsukasa OI [this message]
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