From: Jan Beulich <jbeulich@suse.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: hongjiu.lu@intel.com, binutils@sourceware.org
Subject: Re: [PATCH 0/7] [RFC] Support Intel APX EGPR
Date: Tue, 19 Sep 2023 15:16:49 +0200 [thread overview]
Message-ID: <a5712d13-e123-e449-68c9-05db081794c6@suse.com> (raw)
In-Reply-To: <20230919125633.491660-1-lili.cui@intel.com>
On 19.09.2023 14:56, Cui, Lili wrote:
> Intel Advanced performance extension (APX) has been released in
> https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
> It contains several extensions such as
> 1. Support APX GPR32 with rex2 prefix (For MAP0 an MAP1 legacy instructions).
> 2. Support APX GPR32 with extend evex prefix(legacy, VEX and EVEX extend to EVEX prefix to support GPR32).
> 3. Support APX NDD (non-destructive destination) and it's optimized encoding.
> 4. Support APX Push2/Pop2
> 5. Support APX NF
> 6. Support APX JMPABS
> 7. Linker support for APX encoded instructions.
> 8. Support APX ZU
> 9. Support APX CCMP and CTEST
>
> Here is an introduction to the implementation of the first two patches in Binutils
>
> 1. APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. Only adding the No_egpr flag to the instructions (legacy map0/map1) don't support EGPR (unsupported instructions are less). For map2/map3(legacy), VEX and EVEX, we use gi386-gen.c to add No_egpr.
>
> 2. we created new entries in i386-opc.tbl for instructions promoted from the legacy space and VEX.
> The extended EVEX prefix is based on the current 4-byte EVEX prefix with the semantics of several payload bits re-defined.
> EVEX extension of legacy instructions:
> All promoted legacy instructions are placed in EVEX map 4, which is
> currently reserved.
> EVEX extension of EVEX instructions:
> All existing EVEX instructions are extended by APX using the extended
> EVEX prefix, so that they can access all 32 GPRs.
> EVEX extension of VEX instructions:
> Promoting a VEX instruction into the EVEX space does not change the map
> id, the opcode, or the operand encoding of the VEX instruction.
All such information belongs in the respective patches, as descriptions.
ChangeLogs alone don't really help understanding _why_ certain things are
done the way they are done, yet that information can be crucial when later
some kind of issue needs sorting out (i.e. it needs to be in git, not just
on a mailing list thread).
> To do list:
> 1. For REX2, All opcodes listed map0 0x4*/0x7*/0xa* and map0 0x3*/0x8* are reserved under REX2 and triggers #UD when prefixed with REX2. It should be belong to first rex2 patch, I will creat another patch to add it.
> 2. Support APX ZU -- In progress
> 3. Support APX CCMP and CTEST -- In progress
> 4. We haven’t disabled EGPR for 3DNOW instructions. We can disable them if AMD guys requires.
Nothing should allow use of the extended registers that isn't positively
known to support them.
> This RFC focused on EGPR implementation in binutils. It may still have potential issues or bugs and requires futher optimization. Any comments are very appreciated.
>
>
> Cui, Lili (1):
> Support APX NF
>
> Hu, Lin1 (2):
> Support APX NDD optimized encoding.
> Support APX JMPABS
>
> Mo, Zewei (1):
> Support APX Push2/Pop2
>
> konglin1 (3):
> Support APX GPR32 with rex2 prefix
> Support APX GPR32 with extend evex prefix
> Support APX NDD
>
> gas/NEWS | 3 +
With work not finished, this file shouldn't be updated just yet.
> gas/config/tc-i386.c | 455 +-
> gas/doc/c-i386.texi | 3 +-
> gas/testsuite/gas/i386/apx-jmpabs-inval.l | 3 +
> gas/testsuite/gas/i386/apx-jmpabs-inval.s | 6 +
> gas/testsuite/gas/i386/apx-mov-inval.l | 2 +
> gas/testsuite/gas/i386/apx-push2pop2-inval.l | 5 +
> gas/testsuite/gas/i386/apx-push2pop2-inval.s | 9 +
> gas/testsuite/gas/i386/i386.exp | 2 +
> .../i386/ilp32/x86-64-opcode-inval-intel.d | 4 +-
> .../gas/i386/ilp32/x86-64-opcode-inval.d | 4 +-
> .../gas/i386/x86-64-apx-egpr-inval.l | 212 +
> .../gas/i386/x86-64-apx-egpr-inval.s | 210 +
> .../gas/i386/x86-64-apx-egpr-promote-inval.l | 17 +
> .../gas/i386/x86-64-apx-egpr-promote-inval.s | 18 +
> gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d | 22 +
> gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s | 25 +
> .../gas/i386/x86-64-apx-evex-promoted-intel.d | 740 +
> .../gas/i386/x86-64-apx-evex-promoted.d | 740 +
> .../gas/i386/x86-64-apx-evex-promoted.s | 1464 ++
> .../gas/i386/x86-64-apx-jmpabs-intel.d | 14 +
> .../gas/i386/x86-64-apx-jmpabs-inval.d | 55 +
> .../gas/i386/x86-64-apx-jmpabs-inval.s | 18 +
> gas/testsuite/gas/i386/x86-64-apx-jmpabs.d | 14 +
> gas/testsuite/gas/i386/x86-64-apx-jmpabs.s | 10 +
> gas/testsuite/gas/i386/x86-64-apx-mov-inval.l | 2 +
> gas/testsuite/gas/i386/x86-64-apx-mov-inval.s | 5 +
> .../gas/i386/x86-64-apx-ndd-optimize.d | 120 +
> .../gas/i386/x86-64-apx-ndd-optimize.s | 115 +
> gas/testsuite/gas/i386/x86-64-apx-ndd.d | 165 +
> gas/testsuite/gas/i386/x86-64-apx-ndd.s | 156 +
> gas/testsuite/gas/i386/x86-64-apx-nf-intel.d | 633 +
> gas/testsuite/gas/i386/x86-64-apx-nf.d | 633 +
> gas/testsuite/gas/i386/x86-64-apx-nf.s | 1256 +
> .../i386/x86-64-apx-push2pop2-decode-inval.d | 29 +
> .../i386/x86-64-apx-push2pop2-decode-inval.s | 19 +
> .../gas/i386/x86-64-apx-push2pop2-intel.d | 42 +
> .../gas/i386/x86-64-apx-push2pop2-inval.l | 9 +
> .../gas/i386/x86-64-apx-push2pop2-inval.s | 13 +
> gas/testsuite/gas/i386/x86-64-apx-push2pop2.d | 42 +
> gas/testsuite/gas/i386/x86-64-apx-push2pop2.s | 39 +
> .../gas/i386/x86-64-apx-rex2-inval.d | 29 +
> .../gas/i386/x86-64-apx-rex2-inval.s | 25 +
> gas/testsuite/gas/i386/x86-64-apx-rex2.d | 148 +
> gas/testsuite/gas/i386/x86-64-apx-rex2.s | 175 +
> gas/testsuite/gas/i386/x86-64-evex.d | 2 +-
> gas/testsuite/gas/i386/x86-64-inval-movbe.l | 31 +-
> gas/testsuite/gas/i386/x86-64-inval-movbe.s | 1 +
> gas/testsuite/gas/i386/x86-64-inval-pseudo.l | 12 +
> gas/testsuite/gas/i386/x86-64-inval-pseudo.s | 8 +
> .../gas/i386/x86-64-opcode-inval-intel.d | 4 +-
> gas/testsuite/gas/i386/x86-64-opcode-inval.d | 4 +-
> gas/testsuite/gas/i386/x86-64-pseudos.d | 62 +
> gas/testsuite/gas/i386/x86-64-pseudos.s | 64 +
> gas/testsuite/gas/i386/x86-64.exp | 19 +
> include/opcode/i386.h | 2 +
> opcodes/i386-dis-evex-len.h | 20 +
> opcodes/i386-dis-evex-mod.h | 60 +
> opcodes/i386-dis-evex-prefix.h | 91 +
> opcodes/i386-dis-evex-reg.h | 155 +
> opcodes/i386-dis-evex-w.h | 10 +
> opcodes/i386-dis-evex-x86.h | 150 +
> opcodes/i386-dis-evex.h | 638 +-
> opcodes/i386-dis.c | 437 +-
> opcodes/i386-gen.c | 14 +
> opcodes/i386-init.h | 514 +-
> opcodes/i386-mnem.h | 3921 +--
> opcodes/i386-opc.h | 26 +-
> opcodes/i386-opc.tbl | 271 +-
> opcodes/i386-reg.tbl | 64 +
> opcodes/i386-tbl.h | 20205 +++++++++-------
> 71 files changed, 23477 insertions(+), 11018 deletions(-)
Please can you avoid sending out diff-s of generated files. Without that
the patches are going to be quite a bit smaller and easier to handle.
Jan
prev parent reply other threads:[~2023-09-19 13:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-19 12:56 Cui, Lili
2023-09-19 12:56 ` [PATCH 1/7] Support APX GPR32 with rex2 prefix Cui, Lili
2023-09-19 12:56 ` [PATCH 2/7] Support APX GPR32 with extend evex prefix Cui, Lili
2023-09-19 12:56 ` [PATCH 3/7] Support APX NDD Cui, Lili
2023-09-19 12:56 ` [PATCH 4/7] Support APX NDD optimized encoding Cui, Lili
2023-09-19 12:56 ` [PATCH 5/7] Support APX Push2/Pop2 Cui, Lili
2023-09-19 12:56 ` [PATCH 6/7] Support APX NF Cui, Lili
2023-09-19 12:56 ` [PATCH 7/7] Support APX JMPABS Cui, Lili
2023-09-19 13:16 ` Jan Beulich [this message]
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