* [PATCH v3 00/10] x86: operand size handling improvements
@ 2019-12-27 9:13 Jan Beulich
2019-12-27 9:18 ` [PATCH v3 05/10] x86-64: also support MOVSXD with 16-bit destination Jan Beulich
` (9 more replies)
0 siblings, 10 replies; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:13 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
Not the least in order to make sure the main change here is fine
for both Linux and gcc, but also because of the need / desire to
have sufficient testsuite coverage (which by itself has pointed
out further issues addressed by this series), it has taken me
several years to finally get this set of changes ready. The main
goal is better consistency in the handling of insn operands, i.e.
in particular less unexpected behavior when deducing how things
would behave from observations with one (set of) insn(s) or
operand(s) towards other constructs.
1: x86: improve handling of insns with ambiguous operand sizes
2: x86: replace adhoc ambiguous operand checking for CRC32
3: x86: move certain MOVSX/MOVZX tests
4: x86: replace adhoc ambiguous operand checking for MOVSX/MOVZX
5: x86-64: also support MOVSXD with 16-bit destination
6: x86: correct VFPCLASSP{S,D} operand size handling
7: x86: drop further pointless/bogus DefaultSize
8: x86-64: also diagnose far returns / IRET with ambiguous operand size
9: x86-64: honor vendor specifics for near RET
10: x86-64: Intel64 adjustments for insns dealing with far pointers
v3 addresses prior comments and adds 4 new patches.
If in doubt this goes on top of previously submitted, still
un-approved patches:
https://sourceware.org/ml/binutils/2019-11/msg00349.html
https://sourceware.org/ml/binutils/2019-12/msg00247.html
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 05/10] x86-64: also support MOVSXD with 16-bit destination
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
@ 2019-12-27 9:18 ` Jan Beulich
2019-12-27 9:18 ` [PATCH v3 04/10] x86: replace adhoc ambiguous operand checking for MOVSX/MOVZX Jan Beulich
` (8 subsequent siblings)
9 siblings, 0 replies; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:18 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
While not very useful, both Intel's and AMD's documentation mention the
case. Unfortunately the behavior differs in how wide of a source
(memory) operand is read. Therefore introduce two respective templates.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-amd64.s,
testsuite/gas/i386/x86-64-amd64.d: New.
testsuite/gas/i386/i386.exp: Run new test.
* testsuite/gas/i386/x86-64-intel64.s: Add movsxd tests.
* testsuite/gas/i386/movx64.l,
testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movsxd): New patterns with 16-bit destination.
* i386-tbl.h: Re-generate.
---
v3: Re-base.
v2: New.
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -669,6 +669,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-addr32"
run_dump_test "x86-64-addr32-intel"
run_dump_test "x86-64-opcode"
+ run_dump_test "x86-64-amd64"
run_dump_test "x86-64-intel64"
if { ! [istarget "*-*-*cygwin*"] && ![istarget "*-*-mingw*"] } then {
run_dump_test "x86-64-pcrel"
--- a/gas/testsuite/gas/i386/movx64.l
+++ b/gas/testsuite/gas/i386/movx64.l
@@ -88,7 +88,7 @@
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxd %al, %cx
[ ]*[1-9][0-9]*[ ]+movsxd %ax, %cx
-[ ]*[1-9][0-9]*[ ]+movsxd %eax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 6663C8[ ]+movsxd %eax, %cx
[ ]*[1-9][0-9]*[ ]+movsxd %rax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxd %al, %ecx
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amd64.d
@@ -0,0 +1,12 @@
+#as: -mamd64
+#objdump: -dw
+#name: x86-64 AMD64
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]+66 63 c8[ ]+movslq %eax,%cx
+[ ]*[a-f0-9]+:[ ]+66 63 08[ ]+movslq \(%rax\),%cx
+[ ]*[a-f0-9]+:[ ]+66 63 08[ ]+movslq \(%rax\),%cx
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amd64.s
@@ -0,0 +1,8 @@
+# Check AMD64
+
+ .text
+_start:
+ .intel_syntax noprefix
+ movsxd cx, eax
+ movsxd cx, [rax]
+ movsxd cx, dword ptr [rax]
--- a/gas/testsuite/gas/i386/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/x86-64-intel64.d
@@ -21,4 +21,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b5 0a lgs \(%rdx\),%rcx
[ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx
[ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx
+[ ]*[a-f0-9]+: 66 63 c8 movslq %eax,%cx
+[ ]*[a-f0-9]+: 66 63 08 movslq \(%rax\),%cx
+[ ]*[a-f0-9]+: 66 63 08 movslq \(%rax\),%cx
#pass
--- a/gas/testsuite/gas/i386/x86-64-intel64.s
+++ b/gas/testsuite/gas/i386/x86-64-intel64.s
@@ -21,3 +21,7 @@ _start:
lgs rcx, tbyte ptr [rdx]
lss rdx, [rbx]
lss rdx, tbyte ptr [rbx]
+
+ movsxd cx, ax
+ movsxd cx, [rax]
+ movsxd cx, word ptr [rax]
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -128,10 +128,13 @@ movswl, 2, 0xfbf, None, 2, Cpu386, Modrm
movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 }
movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
-// Intel Syntax next 3 insns
+// Intel Syntax next 5 insns (the two 16-bit variants at the end aren't
+// particularly useful, but the specifications mention them)
movsx, 2, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
+movsxd, 2, 0x63, None, 1, Cpu64, AMD64|Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
+movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
// Move with zero extend.
movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 04/10] x86: replace adhoc ambiguous operand checking for MOVSX/MOVZX
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
2019-12-27 9:18 ` [PATCH v3 05/10] x86-64: also support MOVSXD with 16-bit destination Jan Beulich
@ 2019-12-27 9:18 ` Jan Beulich
2019-12-27 9:19 ` [PATCH v3 02/10] x86: replace adhoc ambiguous operand checking for CRC32 Jan Beulich
` (7 subsequent siblings)
9 siblings, 0 replies; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:18 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
For these to get treatment consistent with other operand size checking
the special logic shouldn't live in md_assemble(), but process_suffix().
And there's more logic involved than simply zapping the suffix, in
particular to enforce the general "suffix trumps register size" rule in
AT&T mode. The cases where behavior is being corrected can be seen from
the testcase adjustments (as mentioned in the commit introducing these
tests some cases had wrong expectations at that point, but it seemed
better to separate testcase introduction from actual code changes).
Note however that MOVS* and MOVZ* still aren't fully consistent, due to
the objection to fold MOVS* templates just like was done for MOVZ* in
c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb").
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Move movsx/movzx special
casing ...
(process_suffix): ... here. Consider just the first operand
initially.
* testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.l,
testsuite/gas/i386/movx64.l, testsuite/gas/i386/noreg16.l,
testsuite/gas/i386/noreg32.l, testsuite/gas/i386/noreg64.l:
Adjust expectations.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
destination for Cpu64-only variant.
(movsxd): Also allow Reg32 as destination. Drop Rex64.
(movzx): Fold patterns.
* i386-tbl.h: Re-generate.
---
v3: Re-base.
v2: Undo No_lSuf addition to MOVSXD template. Drop bogus / pointless
!i.tm.opcode_modifier.rex64 part of conditional in md_assemble().
Re-base over changes earlier in the series.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4378,22 +4378,6 @@ md_assemble (char *line)
: as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
}
- /* Zap movzx and movsx suffix. The suffix has been set from
- "word ptr" or "byte ptr" on the source operand in Intel syntax
- or extracted from mnemonic in AT&T syntax. But we'll use
- the destination register to choose the suffix for encoding. */
- if ((i.tm.base_opcode & ~9) == 0x0fb6)
- {
- /* In Intel syntax, there must be a suffix. In AT&T syntax, if
- there is no suffix, the default will be byte extension. */
- if (i.reg_operands != 2
- && !i.suffix
- && intel_syntax)
- as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
-
- i.suffix = 0;
- }
-
if (i.tm.opcode_modifier.fwait)
if (!add_prefix (FWAIT_OPCODE))
return;
@@ -6299,6 +6283,15 @@ process_suffix (void)
else if (i.reg_operands
&& (i.operands > 1 || i.types[0].bitfield.class == Reg))
{
+ unsigned int numop = i.operands;
+
+ /* movsx/movzx want only their source operand considered here, for the
+ ambiguity checking below. The suffix will be replaced afterwards
+ to represent the destination (register). */
+ if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w)
+ || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64))
+ --i.operands;
+
/* If there's no instruction mnemonic suffix we try to invent one
based on GPR operands. */
if (!i.suffix)
@@ -6327,6 +6320,13 @@ process_suffix (void)
continue;
break;
}
+
+ /* As an exception, movsx/movzx with a word register destination
+ silently default to a byte source in AT&T mode, as their word
+ memory source case isn't really useful. */
+ if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w
+ && !i.suffix && !intel_syntax && i.types[1].bitfield.word)
+ i.suffix = BYTE_MNEM_SUFFIX;
}
else if (i.suffix == BYTE_MNEM_SUFFIX)
{
@@ -6373,6 +6373,9 @@ process_suffix (void)
;
else
abort ();
+
+ /* Undo the movsx/movzx change done above. */
+ i.operands = numop;
}
else if (i.tm.opcode_modifier.defaultsize
&& !i.suffix
@@ -6464,6 +6467,8 @@ process_suffix (void)
if (i.tm.opcode_modifier.floatmf)
i.suffix = SHORT_MNEM_SUFFIX;
+ else if ((i.tm.base_opcode | 8) == 0xfbe || i.tm.base_opcode == 0x63)
+ /* handled below */;
else if (flag_code == CODE_16BIT)
i.suffix = WORD_MNEM_SUFFIX;
else if (!i.tm.opcode_modifier.no_lsuf)
@@ -6473,6 +6478,31 @@ process_suffix (void)
}
}
+ if ((i.tm.base_opcode | 8) == 0xfbe || i.tm.base_opcode == 0x63)
+ {
+ /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
+ In AT&T syntax, if there is no suffix (warned about above), the default
+ will be byte extension. */
+ if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
+ i.tm.base_opcode |= 1;
+
+ /* For further processing, the suffix should represent the destination
+ (register). This is already the case when one was used with
+ mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
+ no suffix to begin with. */
+ if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix)
+ {
+ if (i.types[1].bitfield.word)
+ i.suffix = WORD_MNEM_SUFFIX;
+ else if (i.types[1].bitfield.qword)
+ i.suffix = QWORD_MNEM_SUFFIX;
+ else
+ i.suffix = LONG_MNEM_SUFFIX;
+
+ i.tm.opcode_modifier.w = 0;
+ }
+ }
+
/* Change the opcode based on the operand size given by i.suffix. */
switch (i.suffix)
{
--- a/gas/testsuite/gas/i386/movx16.l
+++ b/gas/testsuite/gas/i386/movx16.l
@@ -6,7 +6,7 @@
[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %cx
[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %ecx
@@ -18,11 +18,13 @@
[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %ax, %cx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %ecx
-[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %ax, %ecx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl
@@ -30,7 +32,7 @@
[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsxw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx
@@ -103,7 +105,7 @@
[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzx %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %ecx
@@ -115,11 +117,13 @@
[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %ax, %cx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %ecx
-[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %ax, %ecx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl
@@ -127,7 +131,7 @@
[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzxw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx
@@ -154,7 +158,8 @@
[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx
+.* Warning: using `%cx' instead of `%ecx' due to `w' suffix
[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx
[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx
[ ]*[1-9][0-9]*[ ]*
@@ -162,7 +167,8 @@
[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx
+.* Warning: using `%ecx' instead of `%cx' due to `l' suffix
[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx
[ ]*[1-9][0-9]*[ ]*
--- a/gas/testsuite/gas/i386/movx32.l
+++ b/gas/testsuite/gas/i386/movx32.l
@@ -6,7 +6,7 @@
[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsx %ax, %cx
[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx
@@ -18,11 +18,13 @@
[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %ax, %cx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %ecx
-[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %ax, %ecx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl
@@ -30,7 +32,7 @@
[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsxw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx
@@ -103,7 +105,7 @@
[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzx %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %ecx
@@ -115,11 +117,13 @@
[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %ax, %cx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %ecx
-[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %ax, %ecx
+.* Warning: using `%al' instead of `%ax' due to `b' suffix
[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl
@@ -127,7 +131,7 @@
[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzxw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx
@@ -154,7 +158,8 @@
[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %ecx
+.* Warning: using `%cx' instead of `%ecx' due to `w' suffix
[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx
[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx
[ ]*[1-9][0-9]*[ ]*
@@ -162,7 +167,8 @@
[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %cx
+.* Warning: using `%ecx' instead of `%cx' due to `l' suffix
[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx
[ ]*[1-9][0-9]*[ ]*
--- a/gas/testsuite/gas/i386/movx64.l
+++ b/gas/testsuite/gas/i386/movx64.l
@@ -7,13 +7,13 @@
[ ]*[1-9][0-9]*[ ]+movsx %rax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsx %ax, %cx
[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx
[ ]*[1-9][0-9]*[ ]+movsx %rax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx
[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %ecx
-[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 63C8[ ]+movsx %eax, %ecx
[ ]*[1-9][0-9]*[ ]+movsx %rax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsx %al, %rcx
@@ -47,7 +47,7 @@
[ ]*[1-9][0-9]*[ ]+movsxw %rax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx
-[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsxw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx
[ ]*[1-9][0-9]*[ ]+movsxw %rax, %cx
[ ]*[1-9][0-9]*[ ]*
@@ -73,7 +73,7 @@
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxl %al, %ecx
[ ]*[1-9][0-9]*[ ]+movsxl %ax, %ecx
-[ ]*[1-9][0-9]*[ ]+movsxl %eax, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 63C8[ ]+movsxl %eax, %ecx
[ ]*[1-9][0-9]*[ ]+movsxl %rax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxl %al, %rcx
@@ -93,7 +93,7 @@
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxd %al, %ecx
[ ]*[1-9][0-9]*[ ]+movsxd %ax, %ecx
-[ ]*[1-9][0-9]*[ ]+movsxd %eax, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 63C8[ ]+movsxd %eax, %ecx
[ ]*[1-9][0-9]*[ ]+movsxd %rax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxd %al, %rcx
@@ -248,7 +248,7 @@
[ ]*[1-9][0-9]*[ ]+movzx %rax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzx %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx
[ ]*[1-9][0-9]*[ ]+movzx %rax, %cx
[ ]*[1-9][0-9]*[ ]*
@@ -288,7 +288,7 @@
[ ]*[1-9][0-9]*[ ]+movzxw %rax, %cl
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx
-[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzxw %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx
[ ]*[1-9][0-9]*[ ]+movzxw %rax, %cx
[ ]*[1-9][0-9]*[ ]*
@@ -372,12 +372,12 @@
[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx
[ ]*[1-9][0-9]*[ ]+movzbw %rax, %cx
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %al, %ecx
[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx
[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx
[ ]*[1-9][0-9]*[ ]+movzbw %rax, %ecx
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbw %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbw %al, %rcx
[ ]*[1-9][0-9]*[ ]+movzbw %ax, %rcx
[ ]*[1-9][0-9]*[ ]+movzbw %eax, %rcx
[ ]*[1-9][0-9]*[ ]+movzbw %rax, %rcx
@@ -387,7 +387,7 @@
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl
[ ]*[1-9][0-9]*[ ]+movzbl %rax, %cl
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %al, %cx
[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx
[ ]*[1-9][0-9]*[ ]+movzbl %rax, %cx
@@ -397,7 +397,7 @@
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx
[ ]*[1-9][0-9]*[ ]+movzbl %rax, %ecx
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbl %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbl %al, %rcx
[ ]*[1-9][0-9]*[ ]+movzbl %ax, %rcx
[ ]*[1-9][0-9]*[ ]+movzbl %eax, %rcx
[ ]*[1-9][0-9]*[ ]+movzbl %rax, %rcx
@@ -407,12 +407,12 @@
[ ]*[1-9][0-9]*[ ]+movzbq %eax, %cl
[ ]*[1-9][0-9]*[ ]+movzbq %rax, %cl
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbq %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbq %al, %cx
[ ]*[1-9][0-9]*[ ]+movzbq %ax, %cx
[ ]*[1-9][0-9]*[ ]+movzbq %eax, %cx
[ ]*[1-9][0-9]*[ ]+movzbq %rax, %cx
[ ]*[1-9][0-9]*[ ]*
-[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbq %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbq %al, %ecx
[ ]*[1-9][0-9]*[ ]+movzbq %ax, %ecx
[ ]*[1-9][0-9]*[ ]+movzbq %eax, %ecx
[ ]*[1-9][0-9]*[ ]+movzbq %rax, %ecx
@@ -458,7 +458,7 @@
[ ]*[1-9][0-9]*[ ]+movzwl %rax, %ecx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzwl %al, %rcx
-[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzwl %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzwl %ax, %rcx
[ ]*[1-9][0-9]*[ ]+movzwl %eax, %rcx
[ ]*[1-9][0-9]*[ ]+movzwl %rax, %rcx
[ ]*[1-9][0-9]*[ ]*
@@ -473,7 +473,7 @@
[ ]*[1-9][0-9]*[ ]+movzwq %rax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movzwq %al, %ecx
-[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwq %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzwq %ax, %ecx
[ ]*[1-9][0-9]*[ ]+movzwq %eax, %ecx
[ ]*[1-9][0-9]*[ ]+movzwq %rax, %ecx
[ ]*[1-9][0-9]*[ ]*
--- a/gas/testsuite/gas/i386/noreg16.l
+++ b/gas/testsuite/gas/i386/noreg16.l
@@ -56,6 +56,8 @@
.*:[1-9][0-9]*: Warning: .* `mov'
.*:[1-9][0-9]*: Warning: .* `movs'
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movsx'
+.*:[1-9][0-9]*: Warning: .* `movzx'
.*:[1-9][0-9]*: Warning: .* `mul'
.*:[1-9][0-9]*: Warning: .* `neg'
.*:[1-9][0-9]*: Warning: .* `nop'
--- a/gas/testsuite/gas/i386/noreg32.l
+++ b/gas/testsuite/gas/i386/noreg32.l
@@ -61,6 +61,8 @@
.*:[1-9][0-9]*: Warning: .* `mov'
.*:[1-9][0-9]*: Warning: .* `movs'
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movsx'
+.*:[1-9][0-9]*: Warning: .* `movzx'
.*:[1-9][0-9]*: Warning: .* `mul'
.*:[1-9][0-9]*: Warning: .* `neg'
.*:[1-9][0-9]*: Warning: .* `nop'
--- a/gas/testsuite/gas/i386/noreg64.l
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -64,6 +64,10 @@
.*:[1-9][0-9]*: Warning: .* `mov'
.*:[1-9][0-9]*: Warning: .* `movs'
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movsx'
+.*:[1-9][0-9]*: Warning: .* `movsx'
+.*:[1-9][0-9]*: Warning: .* `movzx'
+.*:[1-9][0-9]*: Warning: .* `movzx'
.*:[1-9][0-9]*: Warning: .* `mul'
.*:[1-9][0-9]*: Warning: .* `neg'
.*:[1-9][0-9]*: Warning: .* `nop'
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -129,23 +129,16 @@ movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|
movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
// Intel Syntax next 3 insns
-movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
-movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex, Reg64 }
-movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 }
-movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 }
-movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex, Reg64 }
-movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
+movsx, 2, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
+movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
// Move with zero extend.
movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
-// Intel Syntax next 2 insns (the 64-bit variants are not particulary
+// Intel Syntax next insn (the 64-bit variant is not particulary
// useful since the zero extend 32->64 is implicit, but we can encode them).
-movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
-movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex, Reg16|Reg32|Reg64 }
-movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 }
+movzx, 2, 0xfb6, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Push instructions.
push, 1, 0x50, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 02/10] x86: replace adhoc ambiguous operand checking for CRC32
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
2019-12-27 9:18 ` [PATCH v3 05/10] x86-64: also support MOVSXD with 16-bit destination Jan Beulich
2019-12-27 9:18 ` [PATCH v3 04/10] x86: replace adhoc ambiguous operand checking for MOVSX/MOVZX Jan Beulich
@ 2019-12-27 9:19 ` Jan Beulich
2020-01-13 17:27 ` H.J. Lu
2019-12-27 9:20 ` [PATCH v3 07/10] x86: drop further pointless/bogus DefaultSize Jan Beulich
` (6 subsequent siblings)
9 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:19 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
There's no need (anymore?) to heavily special case this - just make
generic logic consider only its first operand, and deal with the case
of an 'l' suffix not being allowed in a pattern.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Merge CRC32 handling into
generic code path. Deal with No_lSuf being set in a template.
* testsuite/gas/i386/inval-crc32.l,
testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
instead of error(s) when operand size is ambiguous.
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: Add CRC32 tests.
* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
Adjust expectations.
---
v3: Re-base.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6307,50 +6307,26 @@ process_suffix (void)
Destination register type is more significant than source
register type. crc32 in SSE4.2 prefers source register
type. */
- if (i.tm.base_opcode == 0xf20f38f0
- && i.types[0].bitfield.class == Reg)
- {
- if (i.types[0].bitfield.byte)
- i.suffix = BYTE_MNEM_SUFFIX;
- else if (i.types[0].bitfield.word)
- i.suffix = WORD_MNEM_SUFFIX;
- else if (i.types[0].bitfield.dword)
- i.suffix = LONG_MNEM_SUFFIX;
- else if (i.types[0].bitfield.qword)
- i.suffix = QWORD_MNEM_SUFFIX;
- }
-
- if (!i.suffix)
- {
- int op;
+ unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
- if (i.tm.base_opcode == 0xf20f38f0)
- {
- /* We have to know the operand size for crc32. */
- as_bad (_("ambiguous memory operand size for `%s`"),
- i.tm.name);
- return 0;
- }
-
- for (op = i.operands; --op >= 0;)
- if (i.tm.operand_types[op].bitfield.instance == InstanceNone
- || i.tm.operand_types[op].bitfield.instance == Accum)
- {
- if (i.types[op].bitfield.class != Reg)
- continue;
- if (i.types[op].bitfield.byte)
- i.suffix = BYTE_MNEM_SUFFIX;
- else if (i.types[op].bitfield.word)
- i.suffix = WORD_MNEM_SUFFIX;
- else if (i.types[op].bitfield.dword)
- i.suffix = LONG_MNEM_SUFFIX;
- else if (i.types[op].bitfield.qword)
- i.suffix = QWORD_MNEM_SUFFIX;
- else
- continue;
- break;
- }
- }
+ while (op--)
+ if (i.tm.operand_types[op].bitfield.instance == InstanceNone
+ || i.tm.operand_types[op].bitfield.instance == Accum)
+ {
+ if (i.types[op].bitfield.class != Reg)
+ continue;
+ if (i.types[op].bitfield.byte)
+ i.suffix = BYTE_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.word)
+ i.suffix = WORD_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.dword)
+ i.suffix = LONG_MNEM_SUFFIX;
+ else if (i.types[op].bitfield.qword)
+ i.suffix = QWORD_MNEM_SUFFIX;
+ else
+ continue;
+ break;
+ }
}
else if (i.suffix == BYTE_MNEM_SUFFIX)
{
@@ -6490,8 +6466,10 @@ process_suffix (void)
i.suffix = SHORT_MNEM_SUFFIX;
else if (flag_code == CODE_16BIT)
i.suffix = WORD_MNEM_SUFFIX;
- else
+ else if (!i.tm.opcode_modifier.no_lsuf)
i.suffix = LONG_MNEM_SUFFIX;
+ else
+ i.suffix = QWORD_MNEM_SUFFIX;
}
}
--- a/gas/testsuite/gas/i386/inval-crc32.l
+++ b/gas/testsuite/gas/i386/inval-crc32.l
@@ -3,7 +3,7 @@
.*:7: Error: .*
.*:8: Error: .*
.*:9: Error: .*
-.*:10: Error: .*
+.*:10: Warning: .*
.*:11: Error: .*
.*:12: Error: .*
.*:13: Error: .*
@@ -27,7 +27,9 @@ GAS LISTING .*
[ ]*7[ ]+crc32w \(%esi\), %ax
[ ]*8[ ]+crc32 \(%esi\), %al
[ ]*9[ ]+crc32 \(%esi\), %ax
-[ ]*10[ ]+crc32 \(%esi\), %eax
+[ ]*10[ ]+\?\?\?\? F20F38F1[ ]+crc32 \(%esi\), %eax
+\*\*\*\* Warning: .* `crc32'
+[ ]*10[ ]+06
[ ]*11[ ]+crc32 %al, %al
[ ]*12[ ]+crc32b %al, %al
[ ]*13[ ]+crc32 %ax, %ax
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -26,6 +26,7 @@ Disassembly of section .text:
*[a-f0-9]+: 81 3f 34 12 cmpw \$0x1234,\(%bx\)
*[a-f0-9]+: a7 cmpsw %es:\(%di\),%ds:\(%si\)
*[a-f0-9]+: 67 a7 cmpsw %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+: f2 0f 38 f1 07 crc32w \(%bx\),%eax
*[a-f0-9]+: f2 0f 2a 07 cvtsi2sdl \(%bx\),%xmm0
*[a-f0-9]+: f3 0f 2a 07 cvtsi2ssl \(%bx\),%xmm0
*[a-f0-9]+: ff 0f decw \(%bx\)
--- a/gas/testsuite/gas/i386/noreg16.l
+++ b/gas/testsuite/gas/i386/noreg16.l
@@ -17,6 +17,7 @@
.*:[1-9][0-9]*: Warning: .* `cmp'
.*:[1-9][0-9]*: Warning: .* `cmps'
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
.*:[1-9][0-9]*: Warning: .* `dec'
.*:[1-9][0-9]*: Warning: .* `div'
.*:[1-9][0-9]*: Warning: .* `fadd'
--- a/gas/testsuite/gas/i386/noreg16.s
+++ b/gas/testsuite/gas/i386/noreg16.s
@@ -20,6 +20,7 @@ noreg:
cmp $0x1234, (%bx)
cmps
cmps %es:(%edi), (%esi)
+ crc32 (%bx), %eax
cvtsi2sd (%bx), %xmm0
cvtsi2ss (%bx), %xmm0
dec (%bx)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -30,6 +30,7 @@ Disassembly of section .text:
*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%eax\)
*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%eax\),%eax
*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%eax\),%xmm0
*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%eax\),%xmm0
*[a-f0-9]+: ff 08 decl \(%eax\)
--- a/gas/testsuite/gas/i386/noreg32.l
+++ b/gas/testsuite/gas/i386/noreg32.l
@@ -21,6 +21,7 @@
.*:[1-9][0-9]*: Warning: .* `cmp'
.*:[1-9][0-9]*: Warning: .* `cmps'
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
.*:[1-9][0-9]*: Warning: .* `dec'
.*:[1-9][0-9]*: Warning: .* `div'
.*:[1-9][0-9]*: Warning: .* `fadd'
--- a/gas/testsuite/gas/i386/noreg32.s
+++ b/gas/testsuite/gas/i386/noreg32.s
@@ -23,6 +23,7 @@ noreg:
cmp $0x12345678, (%eax)
cmps
cmps %es:(%edi), (%esi)
+ crc32 (%eax), %eax
cvtsi2sd (%eax), %xmm0
cvtsi2ss (%eax), %xmm0
dec (%eax)
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -30,6 +30,8 @@ Disassembly of section .text:
*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%rax\)
*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
+ *[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%rax\),%eax
+ *[a-f0-9]+: f2 48 0f 38 f1 00 crc32q \(%rax\),%rax
*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
*[a-f0-9]+: ff 08 decl \(%rax\)
--- a/gas/testsuite/gas/i386/noreg64.l
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -21,6 +21,8 @@
.*:[1-9][0-9]*: Warning: .* `cmp'
.*:[1-9][0-9]*: Warning: .* `cmps'
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Warning: .* `crc32'
.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
.*:[1-9][0-9]*: Warning: .* `dec'
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -23,6 +23,8 @@ noreg:
cmp $0x12345678, (%rax)
cmps
cmps %es:(%rdi), (%rsi)
+ crc32 (%rax), %eax
+ crc32 (%rax), %rax
cvtsi2sd (%rax), %xmm0
cvtsi2ss (%rax), %xmm0
dec (%rax)
--- a/gas/testsuite/gas/i386/x86-64-inval-crc32.l
+++ b/gas/testsuite/gas/i386/x86-64-inval-crc32.l
@@ -3,8 +3,8 @@
.*:7: Error: .*
.*:8: Error: .*
.*:9: Error: .*
-.*:10: Error: .*
-.*:11: Error: .*
+.*:10: Warning: .*
+.*:11: Warning: .*
.*:12: Error: .*
.*:13: Error: .*
.*:14: Error: .*
@@ -38,8 +38,12 @@ GAS LISTING .*
[ ]*7[ ]+crc32w \(%rsi\), %ax
[ ]*8[ ]+crc32 \(%rsi\), %al
[ ]*9[ ]+crc32 \(%rsi\), %ax
-[ ]*10[ ]+crc32 \(%rsi\), %eax
-[ ]*11[ ]+crc32 \(%rsi\), %rax
+[ ]*10[ ]+\?\?\?\? F20F38F1[ ]+crc32 \(%rsi\), %eax
+\*\*\*\* Warning: .* `crc32'
+[ ]*10[ ]+06
+[ ]*11[ ]+\?\?\?\? F2480F38[ ]+crc32 \(%rsi\), %rax
+\*\*\*\* Warning: .* `crc32'
+[ ]*11[ ]+F106
[ ]*12[ ]+crc32 %al, %al
[ ]*13[ ]+crc32b %al, %al
[ ]*14[ ]+crc32 %ax, %ax
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 08/10] x86-64: also diagnose far returns / IRET with ambiguous operand size
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
` (4 preceding siblings ...)
2019-12-27 9:20 ` [PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich
@ 2019-12-27 9:20 ` Jan Beulich
2020-01-13 17:38 ` H.J. Lu
2019-12-27 9:21 ` [PATCH v3 09/10] x86-64: honor vendor specifics for near RET Jan Beulich
` (3 subsequent siblings)
9 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:20 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
Other than near returns these default to 32-bit operand size, and hence
it isn't really unlikely that 64-bit forms are meant. Hence these should
have disambiguating suffixes. In Intel mode, however, don't error in
these cases unconditionally - MASM accepts these without suffix _and_
without warning.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): .
testsuite/gas/i386/noreg64.s: Add IRET and LRET cases.
testsuite/gas/i386/x86-64-opcode.s: Add suffix to IRET and LRET.
Add LRETQ case.
testsuite/gas/i386/x86-64-suffix.s: Drop IRET case without
suffix.
testsuite/gas/i386/x86_64.s: Add RETF cases.
* testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l,
testsuite/gas/i386/x86-64-opcode.d,
testsuite/gas/i386/x86-64-suffix-intel.d,
testsuite/gas/i386/x86-64-suffix.d,
testsuite/gas/i386/x86_64-intel.d
testsuite/gas/i386/x86_64.d: Adjust expectations.
* testsuite/gas/i386/x86-64-suffix.e,
testsuite/gas/i386/x86_64.e: New.
---
v3: New.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6427,7 +6427,11 @@ process_suffix (void)
}
if (!i.suffix
- && !i.tm.opcode_modifier.defaultsize
+ && (!i.tm.opcode_modifier.defaultsize
+ /* Also cover lret/retf/iret in 64-bit mode. */
+ || (flag_code == CODE_64BIT
+ && !i.tm.opcode_modifier.no_lsuf
+ && !i.tm.opcode_modifier.no_qsuf))
&& !i.tm.opcode_modifier.ignoresize
/* Accept FLDENV et al without suffix. */
&& (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
@@ -6499,7 +6503,9 @@ process_suffix (void)
/* Are multiple suffixes / operand sizes allowed? */
if (suffixes & (suffixes - 1))
{
- if (intel_syntax)
+ if (intel_syntax
+ && (!i.tm.opcode_modifier.defaultsize
+ || operand_check == check_error))
{
as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
return 0;
@@ -6511,9 +6517,12 @@ process_suffix (void)
return 0;
}
if (operand_check == check_warning)
- as_warn (_("no instruction mnemonic suffix given and "
- "no register operands; using default for `%s'"),
- i.tm.name);
+ as_warn (_("%s; using default for `%s'"),
+ intel_syntax
+ ? _("ambiguous operand size")
+ : _("no instruction mnemonic suffix given and "
+ "no register operands"),
+ i.tm.name);
if (i.tm.opcode_modifier.floatmf)
i.suffix = SHORT_MNEM_SUFFIX;
--- a/gas/testsuite/gas/i386/k1om.d
+++ b/gas/testsuite/gas/i386/k1om.d
@@ -2,6 +2,7 @@
#as: -J -march=k1om
#objdump: -dw
#name: k1om
+#warning_output: x86_64.e
#notarget: *-*-nacl*
.*: +file format elf64-k1om.*
@@ -54,7 +55,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 41 03 00 add \(%r8\),%eax
[ ]*[a-f0-9]+: 45 03 00 add \(%r8\),%r8d
[ ]*[a-f0-9]+: 49 03 00 add \(%r8\),%rax
-[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 222222c7 <foo\+0x222220c4>
+[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 03 45 00 add 0x0\(%rbp\),%eax
[ ]*[a-f0-9]+: 03 04 25 22 22 22 22 add 0x22222222,%eax
[ ]*[a-f0-9]+: 41 03 45 00 add 0x0\(%r13\),%eax
@@ -86,10 +87,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 83 04 81 11 addl \$0x11,\(%rcx,%rax,4\)
[ ]*[a-f0-9]+: 41 83 04 81 11 addl \$0x11,\(%r9,%rax,4\)
[ ]*[a-f0-9]+: 42 83 04 81 11 addl \$0x11,\(%rcx,%r8,4\)
-[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 22222342 <foo\+0x2222213f>
-[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222234a <foo\+0x22222147>
-[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 22222354 <foo\+0x22222151>
-[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222235f <foo\+0x2222215c>
+[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 83 04 c5 22 22 22 22 33 addl \$0x33,0x22222222\(,%rax,8\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
@@ -106,8 +107,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 63 c0 movslq %eax,%rax
[ ]*[a-f0-9]+: 48 0f bf c0 movswq %ax,%rax
[ ]*[a-f0-9]+: 48 0f be c0 movsbq %al,%rax
+[ ]*[a-f0-9]+: cb lret *
+[ ]*[a-f0-9]+: ca 10 00 lret \$0x10
+[ ]*[a-f0-9]+: 66 cb lretw *
+[ ]*[a-f0-9]+: 66 ca 02 00 lretw \$0x2
+[ ]*[a-f0-9]+: cb lret *
+[ ]*[a-f0-9]+: ca 04 00 lret \$0x4
+[ ]*[a-f0-9]+: 48 cb lretq *
+[ ]*[a-f0-9]+: 48 ca 08 00 lretq \$0x8
-0+1a7 <bar>:
+[0-9a-f]+ <bar>:
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
@@ -115,7 +124,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1d5 <bar\+0x2e>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # [0-9a-f]+ <bar\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
@@ -123,9 +132,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 203 <foo>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # [0-9a-f]+ <foo>
-0+203 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%al
[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%ax
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%eax
--- a/gas/testsuite/gas/i386/l1om.d
+++ b/gas/testsuite/gas/i386/l1om.d
@@ -2,6 +2,7 @@
#as: -J -march=l1om
#objdump: -dw --insn-width=7
#name: l1om
+#warning_output: x86_64.e
#notarget: *-*-nacl*
.*: +file format elf64-l1om.*
@@ -54,7 +55,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 41 03 00 add \(%r8\),%eax
[ ]*[a-f0-9]+: 45 03 00 add \(%r8\),%r8d
[ ]*[a-f0-9]+: 49 03 00 add \(%r8\),%rax
-[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 222222c7 <foo\+0x222220c4>
+[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 03 45 00 add 0x0\(%rbp\),%eax
[ ]*[a-f0-9]+: 03 04 25 22 22 22 22 add 0x22222222,%eax
[ ]*[a-f0-9]+: 41 03 45 00 add 0x0\(%r13\),%eax
@@ -86,10 +87,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 83 04 81 11 addl \$0x11,\(%rcx,%rax,4\)
[ ]*[a-f0-9]+: 41 83 04 81 11 addl \$0x11,\(%r9,%rax,4\)
[ ]*[a-f0-9]+: 42 83 04 81 11 addl \$0x11,\(%rcx,%r8,4\)
-[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 22222342 <foo\+0x2222213f>
-[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222234a <foo\+0x22222147>
-[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 22222354 <foo\+0x22222151>
-[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222235f <foo\+0x2222215c>
+[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 83 04 c5 22 22 22 22 33 addl \$0x33,0x22222222\(,%rax,8\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
@@ -106,8 +107,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 63 c0 movslq %eax,%rax
[ ]*[a-f0-9]+: 48 0f bf c0 movswq %ax,%rax
[ ]*[a-f0-9]+: 48 0f be c0 movsbq %al,%rax
+[ ]*[a-f0-9]+: cb lret *
+[ ]*[a-f0-9]+: ca 10 00 lret \$0x10
+[ ]*[a-f0-9]+: 66 cb lretw *
+[ ]*[a-f0-9]+: 66 ca 02 00 lretw \$0x2
+[ ]*[a-f0-9]+: cb lret *
+[ ]*[a-f0-9]+: ca 04 00 lret \$0x4
+[ ]*[a-f0-9]+: 48 cb lretq *
+[ ]*[a-f0-9]+: 48 ca 08 00 lretq \$0x8
-0+1a7 <bar>:
+[0-9a-f]+ <bar>:
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
@@ -115,7 +124,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1d5 <bar\+0x2e>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # [0-9a-f]+ <bar\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
@@ -123,9 +132,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 203 <foo>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # [0-9a-f]+ <foo>
-0+203 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%al
[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%ax
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%eax
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -66,6 +66,7 @@ Disassembly of section .text:
*[a-f0-9]+: ff 00 incl \(%rax\)
*[a-f0-9]+: 6d insl \(%dx\),%es:\(%rdi\)
*[a-f0-9]+: 6d insl \(%dx\),%es:\(%rdi\)
+ *[a-f0-9]+: cf iret *
*[a-f0-9]+: ff 20 jmpq \*\(%rax\)
*[a-f0-9]+: 0f 01 10 lgdt \(%rax\)
*[a-f0-9]+: 0f 01 18 lidt \(%rax\)
@@ -73,6 +74,8 @@ Disassembly of section .text:
*[a-f0-9]+: 0f 01 30 lmsw \(%rax\)
*[a-f0-9]+: ad lods %ds:\(%rsi\),%eax
*[a-f0-9]+: ad lods %ds:\(%rsi\),%eax
+ *[a-f0-9]+: cb lret *
+ *[a-f0-9]+: ca 04 00 lret \$0x4
*[a-f0-9]+: 0f 00 18 ltr \(%rax\)
*[a-f0-9]+: c7 00 12 00 00 00 movl \$0x12,\(%rax\)
*[a-f0-9]+: c7 00 34 12 00 00 movl \$0x1234,\(%rax\)
--- a/gas/testsuite/gas/i386/noreg64.l
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -57,8 +57,11 @@
.*:[1-9][0-9]*: Warning: .* `inc'
.*:[1-9][0-9]*: Warning: .* `ins'
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `iret'
.*:[1-9][0-9]*: Warning: .* `lods'
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lret'
+.*:[1-9][0-9]*: Warning: .* `lret'
.*:[1-9][0-9]*: Warning: .* `mov'
.*:[1-9][0-9]*: Warning: .* `mov'
.*:[1-9][0-9]*: Warning: .* `mov'
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -59,6 +59,7 @@ noreg:
inc (%rax)
ins
ins %dx, %es:(%rdi)
+ iret
jmp *(%rax)
lgdt (%rax)
lidt (%rax)
@@ -66,6 +67,8 @@ noreg:
lmsw (%rax)
lods
lods (%rsi)
+ lret
+ lret $4
ltr (%rax)
mov $0x12, (%rax)
mov $0x1234, (%rax)
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -12,6 +12,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 41 ff 10 callq \*\(%r8\)
[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\)
[ ]*[a-f0-9]+: cb lret
+[ ]*[a-f0-9]+: 48 cb lretq *
[ ]*[a-f0-9]+: c3 retq
[ ]*[a-f0-9]+: cf iret
[ ]*[a-f0-9]+: 66 cf iretw
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -9,11 +9,12 @@
CALLq *(%rax) # -- -- -- -- FF 10
# RET
- lret # -- -- -- -- CB
+ lretl # -- -- -- -- CB
+ lretq # -- -- -- 48 CB
retq # -- -- -- -- C3
# IRET
- IRET # -- -- -- -- CF ; 32-bit operand size
+ IRETL # -- -- -- -- CF ; 32-bit operand size
IRETW # 66 -- -- -- CF ; O16 for 16-bit operand size
IRETQ # -- -- -- 48 CF ; REX for 64-bit operand size
--- a/gas/testsuite/gas/i386/x86-64-suffix-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-suffix-intel.d
@@ -1,6 +1,7 @@
#source: x86-64-suffix.s
#objdump: -dw -Msuffix,intel
#name: x86-64 suffix (Intel mode)
+#warning_output: x86-64-suffix.e
.*: +file format .*
@@ -15,7 +16,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
[ ]*[a-f0-9]+: 66 cf iretw
[ ]*[a-f0-9]+: cf iretd
-[ ]*[a-f0-9]+: cf iretd
[ ]*[a-f0-9]+: 48 cf iretq
[ ]*[a-f0-9]+: 0f 07 sysretd
[ ]*[a-f0-9]+: 48 0f 07 sysretq
--- a/gas/testsuite/gas/i386/x86-64-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-suffix.d
@@ -1,5 +1,6 @@
#objdump: -dwMsuffix
#name: x86-64 suffix (AT&T mode)
+#warning_output: x86-64-suffix.e
.*: +file format .*
@@ -14,7 +15,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
[ ]*[a-f0-9]+: 66 cf iretw
[ ]*[a-f0-9]+: cf iretl
-[ ]*[a-f0-9]+: cf iretl
[ ]*[a-f0-9]+: 48 cf iretq
[ ]*[a-f0-9]+: 0f 07 sysretl
[ ]*[a-f0-9]+: 48 0f 07 sysretq
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-suffix.e
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `iret'
--- a/gas/testsuite/gas/i386/x86-64-suffix.s
+++ b/gas/testsuite/gas/i386/x86-64-suffix.s
@@ -12,7 +12,6 @@ foo:
iretw
iretl
- iret
iretq
sysretl
sysretq
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -2,6 +2,7 @@
#as: -J
#objdump: -dw -Mintel
#name: x86-64 (Intel mode)
+#warning_output: x86_64.e
.*: +file format .*
@@ -52,7 +53,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 41 03 00 add eax,DWORD PTR \[r8\]
[ ]*[a-f0-9]+: 45 03 00 add r8d,DWORD PTR \[r8\]
[ ]*[a-f0-9]+: 49 03 00 add rax,QWORD PTR \[r8\]
-[ ]*[a-f0-9]+: 03 05 22 22 22 22 add eax,DWORD PTR \[rip\+0x22222222\] # 222222c7 <foo\+0x222220c4>
+[ ]*[a-f0-9]+: 03 05 22 22 22 22 add eax,DWORD PTR \[rip\+0x22222222\] # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 03 45 00 add eax,DWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: 03 04 25 22 22 22 22 add eax,DWORD PTR ds:0x22222222
[ ]*[a-f0-9]+: 41 03 45 00 add eax,DWORD PTR \[r13\+0x0\]
@@ -84,10 +85,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 83 04 81 11 add DWORD PTR \[rcx\+rax\*4\],0x11
[ ]*[a-f0-9]+: 41 83 04 81 11 add DWORD PTR \[r9\+rax\*4\],0x11
[ ]*[a-f0-9]+: 42 83 04 81 11 add DWORD PTR \[rcx\+r8\*4\],0x11
-[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 add DWORD PTR \[rip\+0x22222222\],0x33 # 22222342 <foo\+0x2222213f>
-[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 add QWORD PTR \[rip\+0x22222222\],0x33 # 2222234a <foo\+0x22222147>
-[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 add DWORD PTR \[rip\+0x22222222\],0x33333333 # 22222354 <foo\+0x22222151>
-[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 add QWORD PTR \[rip\+0x22222222\],0x33333333 # 2222235f <foo\+0x2222215c>
+[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 add DWORD PTR \[rip\+0x22222222\],0x33 # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 add QWORD PTR \[rip\+0x22222222\],0x33 # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 add DWORD PTR \[rip\+0x22222222\],0x33333333 # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 add QWORD PTR \[rip\+0x22222222\],0x33333333 # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 83 04 c5 22 22 22 22 33 add DWORD PTR \[rax\*8\+0x22222222\],0x33
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 add DWORD PTR \[rax\+0x22222222\],0x33
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 add DWORD PTR \[rax\+0x22222222\],0x33
@@ -104,8 +105,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 63 c0 movsxd rax,eax
[ ]*[a-f0-9]+: 48 0f bf c0 movsx rax,ax
[ ]*[a-f0-9]+: 48 0f be c0 movsx rax,al
+[ ]*[a-f0-9]+: cb retf *
+[ ]*[a-f0-9]+: ca 10 00 retf 0x10
+[ ]*[a-f0-9]+: 66 cb retfw *
+[ ]*[a-f0-9]+: 66 ca 02 00 retfw 0x2
+[ ]*[a-f0-9]+: cb retf *
+[ ]*[a-f0-9]+: ca 04 00 retf 0x4
+[ ]*[a-f0-9]+: 48 cb rex\.W retf *
+[ ]*[a-f0-9]+: 48 ca 08 00 rex\.W retf 0x8
-0+1a7 <bar>:
+[0-9a-f]+ <bar>:
[ ]*[a-f0-9]+: b0 00 mov al,0x0
[ ]*[a-f0-9]+: 66 b8 00 00 mov ax,0x0
[ ]*[a-f0-9]+: b8 00 00 00 00 mov eax,0x0
@@ -113,7 +122,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs eax,ds:0x0
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov eax,DWORD PTR ds:0x0
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov eax,DWORD PTR \[rax\+0x0\]
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov eax,DWORD PTR \[rip\+0x0\] # 1d5 <bar\+0x2e>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov eax,DWORD PTR \[rip\+0x0\] # [0-9a-f]+ <bar\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: b0 00 mov al,0x0
[ ]*[a-f0-9]+: 66 b8 00 00 mov ax,0x0
[ ]*[a-f0-9]+: b8 00 00 00 00 mov eax,0x0
@@ -121,9 +130,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs eax,ds:0x0
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov eax,DWORD PTR ds:0x0
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov eax,DWORD PTR \[rax\+0x0\]
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov eax,DWORD PTR \[rip\+0x0\] # 203 <foo>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov eax,DWORD PTR \[rip\+0x0\] # [0-9a-f]+ <foo>
-0+203 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 movabs al,ds:0x8877665544332211
[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 movabs ax,ds:0x8877665544332211
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 movabs eax,ds:0x8877665544332211
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -1,6 +1,8 @@
#as: -J
#objdump: -dw
#name: x86_64
+#warning_output: x86_64.e
+
.*: +file format .*
Disassembly of section .text:
@@ -51,7 +53,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 41 03 00 add \(%r8\),%eax
[ ]*[a-f0-9]+: 45 03 00 add \(%r8\),%r8d
[ ]*[a-f0-9]+: 49 03 00 add \(%r8\),%rax
-[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 222222c7 <foo\+0x222220c4>
+[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 03 45 00 add 0x0\(%rbp\),%eax
[ ]*[a-f0-9]+: 03 04 25 22 22 22 22 add 0x22222222,%eax
[ ]*[a-f0-9]+: 41 03 45 00 add 0x0\(%r13\),%eax
@@ -83,10 +85,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 83 04 81 11 addl \$0x11,\(%rcx,%rax,4\)
[ ]*[a-f0-9]+: 41 83 04 81 11 addl \$0x11,\(%r9,%rax,4\)
[ ]*[a-f0-9]+: 42 83 04 81 11 addl \$0x11,\(%rcx,%r8,4\)
-[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 22222342 <foo\+0x2222213f>
-[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222234a <foo\+0x22222147>
-[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 22222354 <foo\+0x22222151>
-[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222235f <foo\+0x2222215c>
+[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
+[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222[0-9a-f]* <foo\+0x2222[0-9a-f]*>
[ ]*[a-f0-9]+: 83 04 c5 22 22 22 22 33 addl \$0x33,0x22222222\(,%rax,8\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
@@ -103,8 +105,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 63 c0 movslq %eax,%rax
[ ]*[a-f0-9]+: 48 0f bf c0 movswq %ax,%rax
[ ]*[a-f0-9]+: 48 0f be c0 movsbq %al,%rax
+[ ]*[a-f0-9]+: cb lret *
+[ ]*[a-f0-9]+: ca 10 00 lret \$0x10
+[ ]*[a-f0-9]+: 66 cb lretw *
+[ ]*[a-f0-9]+: 66 ca 02 00 lretw \$0x2
+[ ]*[a-f0-9]+: cb lret *
+[ ]*[a-f0-9]+: ca 04 00 lret \$0x4
+[ ]*[a-f0-9]+: 48 cb lretq *
+[ ]*[a-f0-9]+: 48 ca 08 00 lretq \$0x8
-0+1a7 <bar>:
+[0-9a-f]+ <bar>:
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
@@ -112,7 +122,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1d5 <bar\+0x2e>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # [0-9a-f]+ <bar\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
@@ -120,9 +130,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 203 <foo>
+[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # [0-9a-f]+ <foo>
-0+203 <foo>:
+[0-9a-f]+ <foo>:
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%al
[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%ax
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%eax
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86_64.e
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `retf'
+.*:[1-9][0-9]*: Warning: .* `retf'
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -99,6 +99,14 @@ cdqe
movsx rax, eax
movsx rax, ax
movsx rax, al
+retf
+retf 16
+retfw
+retfw 2
+retfd
+retfd 4
+retfq
+retfq 8
bar:
.att_syntax
#testcase for symbol references.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
` (3 preceding siblings ...)
2019-12-27 9:20 ` [PATCH v3 07/10] x86: drop further pointless/bogus DefaultSize Jan Beulich
@ 2019-12-27 9:20 ` Jan Beulich
2020-01-13 17:36 ` H.J. Lu
2019-12-27 9:20 ` [PATCH v3 08/10] x86-64: also diagnose far returns / IRET with ambiguous operand size Jan Beulich
` (4 subsequent siblings)
9 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:20 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
With AVX512VL disabled (e.g. when writing code for the Knights family
of processors) these insns aren't ambiguous when used with a memory
source, and hence should be accepted without suffix or operand size
specifier. When AVX512VL is enabled, to be consistent with this as
well as other ambiguous operand size handling it seems better to just
warn about the ambiguity in AT&T mode, and still default to 512-bit
operands (on the assumption that the code may have been written without
AVX512VL in mind yet).
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (avx512): New (at file scope), moved from
(check_VecOperands): ... here.
(process_suffix): Add [XYZ]MMword operand size handling.
* testsuite/gas/i386/noavx512-2.s, testsuite/gas/i386/noreg16.s,
testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s: Add
VFPCLASS tests.
* testsuite/gas/i386/noavx512-2.l, testsuite/gas/i386/noreg16.d,
testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.d,
testsuite/gas/i386/noreg32.l, testsuite/gas/i386/noreg64.d,
testsuite/gas/i386/noreg64.l: Adjust expectations.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vfpclasspd, vfpclassps): Add Unspecified.
* i386-tbl.h: Re-generate.
---
v3: Re-base.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1839,6 +1839,8 @@ cpu_flags_and_not (i386_cpu_flags x, i38
return x;
}
+static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
+
#define CPU_FLAGS_ARCH_MATCH 0x1
#define CPU_FLAGS_64BIT_MATCH 0x2
@@ -5352,7 +5354,6 @@ check_VecOperands (const insn_template *
{
unsigned int op;
i386_cpu_flags cpu;
- static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
/* Templates allowing for ZMMword as well as YMMword and/or XMMword for
any one operand are implicity requiring AVX512VL support if the actual
@@ -6432,7 +6433,8 @@ process_suffix (void)
&& !i.tm.opcode_modifier.defaultsize
&& !i.tm.opcode_modifier.ignoresize)
{
- unsigned int suffixes;
+ unsigned int suffixes, evex = 0;
+ i386_cpu_flags cpu;
suffixes = !i.tm.opcode_modifier.no_bsuf;
if (!i.tm.opcode_modifier.no_wsuf)
@@ -6446,7 +6448,56 @@ process_suffix (void)
if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
suffixes |= 1 << 5;
- /* Are multiple suffixes allowed? */
+ /* For [XYZ]MMWORD operands inspect operand sizes. */
+ cpu = cpu_flags_and (i.tm.cpu_flags, avx512);
+ if (!cpu_flags_all_zero (&cpu)
+ && !i.broadcast)
+ {
+ unsigned int op;
+
+ for (op = 0; op < i.tm.operands; ++op)
+ {
+ if (!cpu_arch_flags.bitfield.cpuavx512vl)
+ {
+ if (i.tm.operand_types[op].bitfield.ymmword)
+ i.tm.operand_types[op].bitfield.xmmword = 0;
+ if (i.tm.operand_types[op].bitfield.zmmword)
+ i.tm.operand_types[op].bitfield.ymmword = 0;
+ if (!i.tm.opcode_modifier.evex
+ || i.tm.opcode_modifier.evex == EVEXDYN)
+ i.tm.opcode_modifier.evex = EVEX512;
+ }
+
+ if (i.tm.operand_types[op].bitfield.xmmword
+ + i.tm.operand_types[op].bitfield.ymmword
+ + i.tm.operand_types[op].bitfield.zmmword < 2)
+ continue;
+
+ /* Any properly sized operand disambiguates the insn. */
+ if (i.types[op].bitfield.xmmword
+ || i.types[op].bitfield.ymmword
+ || i.types[op].bitfield.zmmword)
+ {
+ suffixes &= ~(7 << 6);
+ evex = 0;
+ break;
+ }
+
+ if ((i.flags[op] & Operand_Mem)
+ && i.tm.operand_types[op].bitfield.unspecified)
+ {
+ if (i.tm.operand_types[op].bitfield.xmmword)
+ suffixes |= 1 << 6;
+ if (i.tm.operand_types[op].bitfield.ymmword)
+ suffixes |= 1 << 7;
+ if (i.tm.operand_types[op].bitfield.zmmword)
+ suffixes |= 1 << 8;
+ evex = EVEX512;
+ }
+ }
+ }
+
+ /* Are multiple suffixes / operand sizes allowed? */
if (suffixes & (suffixes - 1))
{
if (intel_syntax)
@@ -6469,6 +6520,8 @@ process_suffix (void)
i.suffix = SHORT_MNEM_SUFFIX;
else if ((i.tm.base_opcode | 8) == 0xfbe || i.tm.base_opcode == 0x63)
/* handled below */;
+ else if (evex)
+ i.tm.opcode_modifier.evex = evex;
else if (flag_code == CODE_16BIT)
i.suffix = WORD_MNEM_SUFFIX;
else if (!i.tm.opcode_modifier.no_lsuf)
--- a/gas/testsuite/gas/i386/noavx512-2.l
+++ b/gas/testsuite/gas/i386/noavx512-2.l
@@ -101,5 +101,10 @@ GAS LISTING .*
[ ]*50[ ]+F5
[ ]*51[ ]+\?\?\?\? 660F58F4 addpd %xmm4, %xmm6
[ ]*52[ ]+
-[ ]*53[ ]+\?\?\?\? 0F1F00 \.p2align 4
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F3FD48 vfpclasspd \$0, \(%eax\), %k0
+[ ]*[1-9][0-9]*[ ]+660000
+[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F37D48 vfpclassps \$0, \(%eax\), %k0
+[ ]*[1-9][0-9]*[ ]+660000
+[ ]*[1-9][0-9]*[ ]+
+[ ]*[1-9][0-9]*[ ].*\.p2align 4
#pass
--- a/gas/testsuite/gas/i386/noavx512-2.s
+++ b/gas/testsuite/gas/i386/noavx512-2.s
@@ -50,4 +50,7 @@
pabsb %xmm5, %xmm6
addpd %xmm4, %xmm6
+ vfpclasspd $0, (%eax), %k0
+ vfpclassps $0, (%eax), %k0
+
.p2align 4
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -145,6 +145,8 @@ Disassembly of section .text:
*[a-f0-9]+: 62 f1 7e 08 2a 07 vcvtsi2ssl \(%bx\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7f 08 7b 07 vcvtusi2sdl \(%bx\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7e 08 7b 07 vcvtusi2ssl \(%bx\),%xmm0,%xmm0
+ *[a-f0-9]+: 62 f3 fd 48 66 07 00 vfpclasspdz \$0x0,\(%bx\),%k0
+ *[a-f0-9]+: 62 f3 7d 48 66 07 00 vfpclasspsz \$0x0,\(%bx\),%k0
*[a-f0-9]+: 83 37 01 xorw \$0x1,\(%bx\)
*[a-f0-9]+: 81 37 89 00 xorw \$0x89,\(%bx\)
*[a-f0-9]+: 81 37 34 12 xorw \$0x1234,\(%bx\)
--- a/gas/testsuite/gas/i386/noreg16.l
+++ b/gas/testsuite/gas/i386/noreg16.l
@@ -113,6 +113,8 @@
.*:[1-9][0-9]*: Warning: .* `sub'
.*:[1-9][0-9]*: Warning: .* `test'
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `vfpclasspd'
+.*:[1-9][0-9]*: Warning: .* `vfpclassps'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg16.s
+++ b/gas/testsuite/gas/i386/noreg16.s
@@ -139,6 +139,8 @@ noreg:
{evex} vcvtsi2ss (%bx), %xmm0, %xmm0
vcvtusi2sd (%bx), %xmm0, %xmm0
vcvtusi2ss (%bx), %xmm0, %xmm0
+ vfpclasspd $0, (%bx), %k0
+ vfpclassps $0, (%bx), %k0
xor $1, (%bx)
xor $0x89, (%bx)
xor $0x1234, (%bx)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -154,6 +154,8 @@ Disassembly of section .text:
*[a-f0-9]+: 62 f1 7e 08 2a 00 vcvtsi2ssl \(%eax\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sdl \(%eax\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ssl \(%eax\),%xmm0,%xmm0
+ *[a-f0-9]+: 62 f3 fd 48 66 00 00 vfpclasspdz \$0x0,\(%eax\),%k0
+ *[a-f0-9]+: 62 f3 7d 48 66 00 00 vfpclasspsz \$0x0,\(%eax\),%k0
*[a-f0-9]+: 83 30 01 xorl \$0x1,\(%eax\)
*[a-f0-9]+: 81 30 89 00 00 00 xorl \$0x89,\(%eax\)
*[a-f0-9]+: 81 30 34 12 00 00 xorl \$0x1234,\(%eax\)
--- a/gas/testsuite/gas/i386/noreg32.l
+++ b/gas/testsuite/gas/i386/noreg32.l
@@ -122,6 +122,8 @@
.*:[1-9][0-9]*: Warning: .* `test'
.*:[1-9][0-9]*: Warning: .* `test'
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `vfpclasspd'
+.*:[1-9][0-9]*: Warning: .* `vfpclassps'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg32.s
+++ b/gas/testsuite/gas/i386/noreg32.s
@@ -147,6 +147,8 @@ noreg:
{evex} vcvtsi2ss (%eax), %xmm0, %xmm0
vcvtusi2sd (%eax), %xmm0, %xmm0
vcvtusi2ss (%eax), %xmm0, %xmm0
+ vfpclasspd $0, (%eax), %k0
+ vfpclassps $0, (%eax), %k0
xor $1, (%eax)
xor $0x89, (%eax)
xor $0x1234, (%eax)
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -158,6 +158,8 @@ Disassembly of section .text:
*[a-f0-9]+: 62 61 7e 08 2a 38 vcvtsi2ssl \(%rax\),%xmm0,%xmm31
*[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sdl \(%rax\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ssl \(%rax\),%xmm0,%xmm0
+ *[a-f0-9]+: 62 f3 fd 48 66 00 00 vfpclasspdz \$0x0,\(%rax\),%k0
+ *[a-f0-9]+: 62 f3 7d 48 66 00 00 vfpclasspsz \$0x0,\(%rax\),%k0
*[a-f0-9]+: 83 30 01 xorl \$0x1,\(%rax\)
*[a-f0-9]+: 81 30 89 00 00 00 xorl \$0x89,\(%rax\)
*[a-f0-9]+: 81 30 34 12 00 00 xorl \$0x1234,\(%rax\)
--- a/gas/testsuite/gas/i386/noreg64.l
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -135,6 +135,8 @@
.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
.*:[1-9][0-9]*: Warning: .* `vcvtusi2sd'
.*:[1-9][0-9]*: Warning: .* `vcvtusi2ss'
+.*:[1-9][0-9]*: Warning: .* `vfpclasspd'
+.*:[1-9][0-9]*: Warning: .* `vfpclassps'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -151,6 +151,8 @@ noreg:
vcvtsi2ss (%rax), %xmm0, %xmm31
vcvtusi2sd (%rax), %xmm0, %xmm0
vcvtusi2ss (%rax), %xmm0, %xmm0
+ vfpclasspd $0, (%rax), %k0
+ vfpclassps $0, (%rax), %k0
xor $1, (%rax)
xor $0x89, (%rax)
xor $0x1234, (%rax)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4500,12 +4500,12 @@ vextracti64x2, 3, 0x6639, None, 1, CpuAV
vinsertf64x2, 4, 0x6618, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
vinserti64x2, 4, 0x6638, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
-vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask }
+vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegMask }
vfpclasspdz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|Unspecified|BaseIndex, RegMask }
vfpclasspdx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask }
vfpclasspdy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|Unspecified|BaseIndex, RegMask }
-vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask }
+vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegMask }
vfpclasspsz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Dword|Unspecified|BaseIndex, RegMask }
vfpclasspsx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask }
vfpclasspsy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|Unspecified|BaseIndex, RegMask }
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 07/10] x86: drop further pointless/bogus DefaultSize
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
` (2 preceding siblings ...)
2019-12-27 9:19 ` [PATCH v3 02/10] x86: replace adhoc ambiguous operand checking for CRC32 Jan Beulich
@ 2019-12-27 9:20 ` Jan Beulich
2020-01-13 17:37 ` H.J. Lu
2019-12-27 9:20 ` [PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich
` (5 subsequent siblings)
9 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:20 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
- 64-bit CALL permitting just a single operand size doesn't need it.
- FLDENV et al should never have had it.
It remains suspicious that a number of 64-bit only insns continue to
have the attribute, despite this being intended for .code16gcc handling
only.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Redo and move FLDENV et al
special case.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
forms.
(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
DefaultSize.
* i386-tbl.h: Re-generate.
---
v3: New.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6378,10 +6378,7 @@ process_suffix (void)
/* Undo the movsx/movzx change done above. */
i.operands = numop;
}
- else if (i.tm.opcode_modifier.defaultsize
- && !i.suffix
- /* exclude fldenv/frstor/fsave/fstenv */
- && i.tm.opcode_modifier.no_ssuf)
+ else if (i.tm.opcode_modifier.defaultsize && !i.suffix)
{
i.suffix = stackop_size;
if (stackop_size == LONG_MNEM_SUFFIX)
@@ -6431,7 +6428,9 @@ process_suffix (void)
if (!i.suffix
&& !i.tm.opcode_modifier.defaultsize
- && !i.tm.opcode_modifier.ignoresize)
+ && !i.tm.opcode_modifier.ignoresize
+ /* Accept FLDENV et al without suffix. */
+ && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
{
unsigned int suffixes, evex = 0;
i386_cpu_flags cpu;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -368,10 +368,10 @@ shrd, 2, 0xfad, None, 2, Cpu386, Modrm|C
// Control transfer instructions.
call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 }
call, 1, 0xe8, None, 1, Cpu64, AMD64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
-call, 1, 0xe8, None, 1, Cpu64, Intel64|JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
+call, 1, 0xe8, None, 1, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
call, 1, 0xff, 0x2, 1, Cpu64, AMD64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
-call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
+call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
// Intel Syntax
call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
// Intel Syntax
@@ -789,13 +789,13 @@ fstsw, 1, 0xdd, 0x7, 1, CpuFP, Modrm|Ign
fstsw, 0, 0xdfe0, None, 2, Cpu287|Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 }
fnclex, 0, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
fclex, 0, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 }
-// Short forms of fldenv, fstenv use data size prefix.
-fnstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
-fstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
-fldenv, 1, 0xd9, 0x4, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
-fnsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
-fsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
-frstor, 1, 0xdd, 0x4, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+// Short forms of fldenv, fstenv, fsave, and frstor use data size prefix.
+fnstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+fstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
+fldenv, 1, 0xd9, 0x4, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+fnsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+fsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
+frstor, 1, 0xdd, 0x4, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
// 8087 only
fneni, 0, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
feni, 0, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 }
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 09/10] x86-64: honor vendor specifics for near RET
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
` (5 preceding siblings ...)
2019-12-27 9:20 ` [PATCH v3 08/10] x86-64: also diagnose far returns / IRET with ambiguous operand size Jan Beulich
@ 2019-12-27 9:21 ` Jan Beulich
2020-01-13 17:40 ` H.J. Lu
2019-12-27 9:22 ` [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes Jan Beulich
` (2 subsequent siblings)
9 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:21 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
While vendors agree about default operand size (64 bits) and hence
unavilability of a 32-bit form, AMD honors a 16-bit operand size
override (0x66) while Intel doesn't.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-branch-2.s,
testsuite/gas/i386/x86-64-branch-4.s,
testsuite/gas/i386/x86-64-branch.s: Add RETW cases.
* testsuite/gas/i386/ilp32/x86-64-branch.d,
testsuite/gas/i386/x86-64-branch-2.d,
testsuite/gas/i386/x86-64-branch-4.l,
testsuite/gas/i386/x86-64-branch.d: Adjust expectations.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
(dis386): Use them to replace C2/C3 table entries.
(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
ones. Use Size64 instead of DefaultSize on Intel64 ones.
* i386-tbl.h: Re-generate.
---
v3: New.
--- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
@@ -23,6 +23,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq 0x2a 26: R_X86_64_PLT32 foo-0x4
[ ]*[a-f0-9]+: 66 e9 00 00 00 00 data16 jmpq 0x30 2c: R_X86_64_PLT32 foo-0x4
[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb 0x37 33: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 66 c3 data16 retq *
+[ ]*[a-f0-9]+: 66 c2 08 00 data16 retq \$0x8
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
@@ -33,6 +35,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
-[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x56 52: R_X86_64_PC32 \*ABS\*\+0x10003c
-[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x5b 57: R_X86_64_PC32 \*ABS\*\+0x10003c
+[ ]*[a-f0-9]+: e8 00 00 00 00 callq 0x[0-9a-f]* [0-9a-f]*: R_X86_64_PC32 \*ABS\*\+0x10003c
+[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x[0-9a-f]* [0-9a-f]*: R_X86_64_PC32 \*ABS\*\+0x10003c
+[ ]*[a-f0-9]+: 66 c3 data16 retq *
+[ ]*[a-f0-9]+: 66 c2 08 00 data16 retq \$0x8
#pass
--- a/gas/testsuite/gas/i386/x86-64-branch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.d
@@ -14,4 +14,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 89 c3 mov %eax,%ebx
[ ]*[a-f0-9]+: 66 e8 00 00 callw 11 <bar\+0x6> f: R_X86_64_PC16 foo-0x2
[ ]*[a-f0-9]+: 66 48 e8 00 00 00 00 data16 callq 18 <bar\+0xd> 14: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 66 c3 retw *
+[ ]*[a-f0-9]+: 66 c2 08 00 retw \$0x8
#pass
--- a/gas/testsuite/gas/i386/x86-64-branch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.s
@@ -7,3 +7,6 @@ bar:
data16 call foo
data16 rex.w call foo
+
+ retw
+ retw $8
--- a/gas/testsuite/gas/i386/x86-64-branch-4.l
+++ b/gas/testsuite/gas/i386/x86-64-branch-4.l
@@ -4,14 +4,18 @@
.*:4: Error: operand type mismatch for `jmp'
.*:5: Error: invalid instruction suffix for `jmp'
.*:6: Error: invalid instruction suffix for `jmp'
-.*:9: Error: operand type mismatch for `call'
-.*:10: Error: invalid instruction suffix for `call'
-.*:11: Error: invalid instruction suffix for `call'
-.*:12: Error: operand size mismatch for `call'
-.*:13: Error: operand type mismatch for `jmp'
-.*:14: Error: invalid instruction suffix for `jmp'
-.*:15: Error: invalid instruction suffix for `jmp'
-.*:16: Error: operand size mismatch for `jmp'
+.*:7: Error: invalid instruction suffix for `ret'
+.*:8: Error: invalid instruction suffix for `ret'
+.*:11: Error: operand type mismatch for `call'
+.*:12: Error: invalid instruction suffix for `call'
+.*:13: Error: invalid instruction suffix for `call'
+.*:14: Error: operand size mismatch for `call'
+.*:15: Error: operand type mismatch for `jmp'
+.*:16: Error: invalid instruction suffix for `jmp'
+.*:17: Error: invalid instruction suffix for `jmp'
+.*:18: Error: operand size mismatch for `jmp'
+.*:19: Error: invalid instruction suffix for `ret'
+.*:20: Error: invalid instruction suffix for `ret'
GAS LISTING .*
#...
[ ]*1[ ]+\.text
@@ -20,14 +24,18 @@ GAS LISTING .*
[ ]*4[ ]+jmp \*%ax
[ ]*5[ ]+jmpw \*%ax
[ ]*6[ ]+jmpw \*\(%rax\)
-[ ]*7[ ]+
-[ ]*8[ ]+\.intel_syntax noprefix
-[ ]*9[ ]+call ax
-[ ]*10[ ]+callw ax
-[ ]*11[ ]+callw \[rax\]
-[ ]*12[ ]+call WORD PTR \[rax\]
-[ ]*13[ ]+jmp ax
-[ ]*14[ ]+jmpw ax
-[ ]*15[ ]+jmpw \[rax\]
-[ ]*16[ ]+jmp WORD PTR \[rax\]
+[ ]*7[ ]+retw
+[ ]*8[ ]+retw \$8
+[ ]*9[ ]+
+[ ]*10[ ]+\.intel_syntax noprefix
+[ ]*11[ ]+call ax
+[ ]*12[ ]+callw ax
+[ ]*13[ ]+callw \[rax\]
+[ ]*14[ ]+call WORD PTR \[rax\]
+[ ]*15[ ]+jmp ax
+[ ]*16[ ]+jmpw ax
+[ ]*17[ ]+jmpw \[rax\]
+[ ]*18[ ]+jmp WORD PTR \[rax\]
+[ ]*19[ ]+retw
+[ ]*20[ ]+retw 8
#pass
--- a/gas/testsuite/gas/i386/x86-64-branch-4.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-4.s
@@ -4,6 +4,8 @@
jmp *%ax
jmpw *%ax
jmpw *(%rax)
+ retw
+ retw $8
.intel_syntax noprefix
call ax
@@ -14,3 +16,5 @@
jmpw ax
jmpw [rax]
jmp WORD PTR [rax]
+ retw
+ retw 8
--- a/gas/testsuite/gas/i386/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -22,6 +22,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq (0x2a|2a <.text\+0x2a>)
[ ]*[a-f0-9]+: 66 e9 00 00 00 00 data16 jmpq (0x30|30 <.text\+0x30>)
[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb (0x37|37 <.text\+0x37>)
+[ ]*[a-f0-9]+: 66 c3 data16 retq *
+[ ]*[a-f0-9]+: 66 c2 08 00 data16 retq \$0x8
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: ff d0 callq \*%rax
[ ]*[a-f0-9]+: 66 ff d0 data16 callq \*%rax
@@ -32,6 +34,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
[ ]*[a-f0-9]+: 66 ff e0 data16 jmpq \*%rax
[ ]*[a-f0-9]+: 66 ff 20 data16 jmpq \*\(%rax\)
-[ ]*[a-f0-9]+: e8 (00|92) 00 (00|10) 00 callq (0x56|1000e8 <.text\+0x1000e8>)
-[ ]*[a-f0-9]+: e9 (00|97) 00 (00|10) 00 jmpq (0x5b|1000f2 <.text\+0x1000f2>)
+[ ]*[a-f0-9]+: e8 .. 00 (00|10) 00 callq (0x[0-9a-f]*|100[0-9a-f]* <.text\+0x100[0-9a-f]*>)
+[ ]*[a-f0-9]+: e9 .. 00 (00|10) 00 jmpq (0x[0-9a-f]*|100[0-9a-f]* <.text\+0x100[0-9a-f]*>)
+[ ]*[a-f0-9]+: 66 c3 data16 retq *
+[ ]*[a-f0-9]+: 66 c2 08 00 data16 retq \$0x8
#pass
--- a/gas/testsuite/gas/i386/x86-64-branch.s
+++ b/gas/testsuite/gas/i386/x86-64-branch.s
@@ -19,6 +19,9 @@
.byte 0x66
jb foo
+ retw
+ retw $8
+
.intel_syntax noprefix
call rax
callq rax
@@ -32,3 +35,5 @@
jmpw [rax]
call 0x100040
jmp 0x100040
+ retw
+ retw 8
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1762,6 +1762,8 @@ enum
X86_64_6F,
X86_64_82,
X86_64_9A,
+ X86_64_C2,
+ X86_64_C3,
X86_64_C4,
X86_64_C5,
X86_64_CE,
@@ -2584,8 +2586,8 @@ static const struct dis386 dis386[] = {
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
- { "retT", { Iw, BND }, 0 },
- { "retT", { BND }, 0 },
+ { X86_64_TABLE (X86_64_C2) },
+ { X86_64_TABLE (X86_64_C3) },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
@@ -6899,6 +6901,18 @@ static const struct dis386 x86_64_table[
{ "Jcall{T|}", { Ap }, 0 },
},
+ /* X86_64_C2 */
+ {
+ { "retP", { Iw, BND }, 0 },
+ { "ret@", { Iw, BND }, 0 },
+ },
+
+ /* X86_64_C3 */
+ {
+ { "retP", { BND }, 0 },
+ { "ret@", { BND }, 0 },
+ },
+
/* X86_64_C4 */
{
{ MOD_TABLE (MOD_C4_32BIT) },
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -394,8 +394,10 @@ ljmp, 1, 0xff, 0x5, 1, 0, Modrm|JumpAbso
ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 }
ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0, 0xc3, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
-ret, 1, 0xc2, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0, 0xc3, None, 1, Cpu64, AMD64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
+ret, 1, 0xc2, None, 1, Cpu64, AMD64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0, 0xc3, None, 1, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { 0 }
+ret, 1, 0xc2, None, 1, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
lret, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
lret, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
// Intel Syntax.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
` (6 preceding siblings ...)
2019-12-27 9:21 ` [PATCH v3 09/10] x86-64: honor vendor specifics for near RET Jan Beulich
@ 2019-12-27 9:22 ` Jan Beulich
2020-01-03 8:32 ` Jan Beulich
2020-01-09 22:36 ` H.J. Lu
2019-12-27 9:24 ` [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests Jan Beulich
2019-12-27 9:27 ` [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich
9 siblings, 2 replies; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:22 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Drop SYSRET special case
and an intel_syntax check. Re-write lack-of-suffix processing
logic.
* doc/c-i386.texi: Document operand size defaults for suffix-
less AT&T syntax insns.
* testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
testsuite/gas/i386/x86-64-avx-scalar.s,
testsuite/gas/i386/x86-64-avx.s,
testsuite/gas/i386/x86-64-bundle.s,
testsuite/gas/i386/x86-64-intel64.s,
testsuite/gas/i386/x86-64-lock-1.s,
testsuite/gas/i386/x86-64-opcode.s,
testsuite/gas/i386/x86-64-sse2avx.s,
testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
* testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
testsuite/gas/i386/x86-64-nops.s,
testsuite/gas/i386/x86-64-ptwrite.s,
testsuite/gas/i386/x86-64-simd.s,
testsuite/gas/i386/x86-64-sse-noavx.s,
testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
insns.
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: Add further tests.
* testsuite/gas/i386/ilp32/x86-64-nops.d,
testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
testsuite/gas/i386/sse-noavx.d,
testsuite/gas/i386/x86-64-intel64.d,
testsuite/gas/i386/x86-64-nops.d,
testsuite/gas/i386/x86-64-opcode.d,
testsuite/gas/i386/x86-64-ptwrite-intel.d,
testsuite/gas/i386/x86-64-ptwrite.d,
testsuite/gas/i386/x86-64-simd-intel.d,
testsuite/gas/i386/x86-64-simd-suffix.d,
testsuite/gas/i386/x86-64-simd.d,
testsuite/gas/i386/x86-64-sse-noavx.d
testsuite/gas/i386/x86-64-suffix.d,
testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
* testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
testsuite/gas/i386/noreg64.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (sysret): Drop DefaultSize.
* i386-tbl.h: Re-generate.
---
v3: Don't add any new DefaultSize. Also diagnose SYSRET in 64-bit mode.
Re-base.
v2: Re-base over NOP addition to testcases modified here. Add IN/OUT
tests. Add shift/rotate insn single operand tests. Extend
"Instruction Naming" doc section to spell out defaults.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6401,9 +6401,7 @@ process_suffix (void)
else if (i.tm.opcode_modifier.defaultsize
&& !i.suffix
/* exclude fldenv/frstor/fsave/fstenv */
- && i.tm.opcode_modifier.no_ssuf
- /* exclude sysret */
- && i.tm.base_opcode != 0x0f07)
+ && i.tm.opcode_modifier.no_ssuf)
{
i.suffix = stackop_size;
if (stackop_size == LONG_MNEM_SUFFIX)
@@ -6424,8 +6422,7 @@ process_suffix (void)
i.tm.name);
}
}
- else if (intel_syntax
- && !i.suffix
+ else if (!i.suffix
&& (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
|| i.tm.opcode_modifier.jump == JUMP_BYTE
|| i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
@@ -6452,42 +6449,49 @@ process_suffix (void)
}
}
- if (!i.suffix)
+ if (!i.suffix
+ && !i.tm.opcode_modifier.defaultsize
+ && !i.tm.opcode_modifier.ignoresize)
{
- if (!intel_syntax)
+ unsigned int suffixes;
+
+ suffixes = !i.tm.opcode_modifier.no_bsuf;
+ if (!i.tm.opcode_modifier.no_wsuf)
+ suffixes |= 1 << 1;
+ if (!i.tm.opcode_modifier.no_lsuf)
+ suffixes |= 1 << 2;
+ if (!i.tm.opcode_modifier.no_ldsuf)
+ suffixes |= 1 << 3;
+ if (!i.tm.opcode_modifier.no_ssuf)
+ suffixes |= 1 << 4;
+ if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
+ suffixes |= 1 << 5;
+
+ /* Are multiple suffixes allowed? */
+ if (suffixes & (suffixes - 1))
{
- if (i.tm.opcode_modifier.w)
+ if (intel_syntax)
{
- as_bad (_("no instruction mnemonic suffix given and "
- "no register operands; can't size instruction"));
+ as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
return 0;
}
- }
- else
- {
- unsigned int suffixes;
-
- suffixes = !i.tm.opcode_modifier.no_bsuf;
- if (!i.tm.opcode_modifier.no_wsuf)
- suffixes |= 1 << 1;
- if (!i.tm.opcode_modifier.no_lsuf)
- suffixes |= 1 << 2;
- if (!i.tm.opcode_modifier.no_ldsuf)
- suffixes |= 1 << 3;
- if (!i.tm.opcode_modifier.no_ssuf)
- suffixes |= 1 << 4;
- if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
- suffixes |= 1 << 5;
-
- /* There are more than suffix matches. */
- if (i.tm.opcode_modifier.w
- || ((suffixes & (suffixes - 1))
- && !i.tm.opcode_modifier.defaultsize
- && !i.tm.opcode_modifier.ignoresize))
+ if (operand_check == check_error)
{
- as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+ as_bad (_("no instruction mnemonic suffix given and "
+ "no register operands; can't size `%s'"), i.tm.name);
return 0;
}
+ if (operand_check == check_warning)
+ as_warn (_("no instruction mnemonic suffix given and "
+ "no register operands; using default for `%s'"),
+ i.tm.name);
+
+ if (i.tm.opcode_modifier.floatmf)
+ i.suffix = SHORT_MNEM_SUFFIX;
+ else if (flag_code == CODE_16BIT)
+ i.suffix = WORD_MNEM_SUFFIX;
+ else
+ i.suffix = LONG_MNEM_SUFFIX;
}
}
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -723,6 +723,31 @@ assembler which assumes that a missing m
operand size. (This incompatibility does not affect compiler output
since compilers always explicitly specify the mnemonic suffix.)
+When there is no sizing suffix and no (suitable) register operands to
+deduce the size of memory operands, with a few exceptions and where long
+operand size is possible in the first place, operand size will default
+to long in 32- and 64-bit modes. Similarly it will default to short in
+16-bit mode. Noteworthy exceptions are
+
+@itemize @bullet
+@item
+Instructions with an implicit on-stack operand as well as branches,
+which default to quad in 64-bit mode.
+
+@item
+Sign- and zero-extending moves, which default to byte size source
+operands.
+
+@item
+Floating point insns with integer operands, which default to short (for
+perhaps historical reasons).
+
+@item
+CRC32 with a 64-bit destination, which defaults to a quad source
+operand.
+
+@end itemize
+
Almost all instructions have the same names in AT&T and Intel format.
There are a few exceptions. The sign extend and zero extend
instructions need two sizes to specify them. They need a size to
--- a/gas/testsuite/gas/i386/bundle.s
+++ b/gas/testsuite/gas/i386/bundle.s
@@ -58,7 +58,7 @@
and $3,%eax
.endm
.macro test_4
- lock and $3,(%eax)
+ lock andl $3,(%eax)
.endm
.macro test_5
mov $0xaabbccdd,%eax
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -129,7 +129,9 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "nops-6"
run_dump_test "nops-7"
run_dump_test "noreg16"
+ run_list_test "noreg16"
run_dump_test "noreg32"
+ run_list_test "noreg32"
run_dump_test "addr16"
run_dump_test "addr32"
run_dump_test "code16"
@@ -729,6 +731,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-sysenter-amd"
run_list_test "x86-64-sysenter-amd"
run_dump_test "noreg64"
+ run_list_test "noreg64"
run_list_test "cvtsi2sX"
run_dump_test "x86-64-sse4_1"
run_dump_test "x86-64-sse4_1-intel"
--- a/gas/testsuite/gas/i386/ilp32/x86-64-nops.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops.d
@@ -42,7 +42,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1d 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1e 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1f 04 59 nopl \(%rcx,%rbx,2\)
-[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
[ ]*[a-f0-9]+: 48 0f 1f c0 nop %rax
[ ]*[a-f0-9]+: 0f 1f c0 nop %eax
[ ]*[a-f0-9]+: 66 0f 1f c0 nop %ax
@@ -52,7 +51,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f 1f c0 nop %rax
[ ]*[a-f0-9]+: 0f 1f c0 nop %eax
[ ]*[a-f0-9]+: 66 0f 1f c0 nop %ax
-[ ]*[a-f0-9]+: 41 0f 1f 02 nopl \(%r10\)
[ ]*[a-f0-9]+: 49 0f 1f c2 nop %r10
[ ]*[a-f0-9]+: 41 0f 1f c2 nop %r10d
[ ]*[a-f0-9]+: 66 41 0f 1f c2 nop %r10w
--- a/gas/testsuite/gas/i386/lock-1.s
+++ b/gas/testsuite/gas/i386/lock-1.s
@@ -3,17 +3,17 @@
.text
foo:
lock add %eax, (%ebx)
- lock add $0x64, (%ebx)
+ lock addl $0x64, (%ebx)
lock adc %eax, (%ebx)
- lock adc $0x64, (%ebx)
+ lock adcl $0x64, (%ebx)
lock and %eax, (%ebx)
- lock and $0x64, (%ebx)
+ lock andl $0x64, (%ebx)
lock btc %eax, (%ebx)
- lock btc $0x64, (%ebx)
+ lock btcl $0x64, (%ebx)
lock btr %eax, (%ebx)
- lock btr $0x64, (%ebx)
+ lock btrl $0x64, (%ebx)
lock bts %eax, (%ebx)
- lock bts $0x64, (%ebx)
+ lock btsl $0x64, (%ebx)
lock cmpxchg %eax,(%ebx)
lock cmpxchg8b (%ebx)
lock decl (%ebx)
@@ -21,16 +21,16 @@ foo:
lock negl (%ebx)
lock notl (%ebx)
lock or %eax, (%ebx)
- lock or $0x64, (%ebx)
+ lock orl $0x64, (%ebx)
lock sbb %eax, (%ebx)
- lock sbb $0x64, (%ebx)
+ lock sbbl $0x64, (%ebx)
lock sub %eax, (%ebx)
- lock sub $0x64, (%ebx)
+ lock subl $0x64, (%ebx)
lock xadd %eax, (%ebx)
lock xchg (%ebx), %eax
lock xchg %eax, (%ebx)
lock xor %eax, (%ebx)
- lock xor $0x64, (%ebx)
+ lock xorl $0x64, (%ebx)
.intel_syntax noprefix
lock add DWORD PTR [ebx],eax
--- a/gas/testsuite/gas/i386/nops.d
+++ b/gas/testsuite/gas/i386/nops.d
@@ -41,7 +41,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1d 04 59 nopl \(%ecx,%ebx,2\)
[ ]*[a-f0-9]+: 0f 1e 04 59 nopl \(%ecx,%ebx,2\)
[ ]*[a-f0-9]+: 0f 1f 04 59 nopl \(%ecx,%ebx,2\)
-[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
[ ]*[a-f0-9]+: 0f 1f c0 nop %eax
[ ]*[a-f0-9]+: 66 0f 1f c0 nop %ax
[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
--- a/gas/testsuite/gas/i386/nops.s
+++ b/gas/testsuite/gas/i386/nops.s
@@ -44,7 +44,6 @@
.byte 0x0f, 0x1e, 0x04, 0x59
.byte 0x0f, 0x1f, 0x04, 0x59
- nop (%eax)
nop %eax
nop %ax
nopl (%eax)
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -1,3 +1,4 @@
+#as: -moperand-check=none
#objdump: -dwMi8086
#name: 16-bit insns not sizeable through register operands
@@ -7,16 +8,28 @@ Disassembly of section .text:
0+ <noreg>:
*[a-f0-9]+: 83 17 01 adcw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 17 89 00 adcw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 17 34 12 adcw \$0x1234,\(%bx\)
*[a-f0-9]+: 83 07 01 addw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 07 89 00 addw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 07 34 12 addw \$0x1234,\(%bx\)
*[a-f0-9]+: 83 27 01 andw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 27 89 00 andw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 27 34 12 andw \$0x1234,\(%bx\)
*[a-f0-9]+: 0f ba 27 01 btw \$0x1,\(%bx\)
*[a-f0-9]+: 0f ba 3f 01 btcw \$0x1,\(%bx\)
*[a-f0-9]+: 0f ba 37 01 btrw \$0x1,\(%bx\)
*[a-f0-9]+: 0f ba 2f 01 btsw \$0x1,\(%bx\)
*[a-f0-9]+: ff 17 call \*\(%bx\)
*[a-f0-9]+: 83 3f 01 cmpw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 3f 89 00 cmpw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 3f 34 12 cmpw \$0x1234,\(%bx\)
+ *[a-f0-9]+: a7 cmpsw %es:\(%di\),%ds:\(%si\)
+ *[a-f0-9]+: 67 a7 cmpsw %es:\(%edi\),%ds:\(%esi\)
*[a-f0-9]+: f2 0f 2a 07 cvtsi2sdl \(%bx\),%xmm0
*[a-f0-9]+: f3 0f 2a 07 cvtsi2ssl \(%bx\),%xmm0
+ *[a-f0-9]+: ff 0f decw \(%bx\)
+ *[a-f0-9]+: f7 37 divw \(%bx\)
*[a-f0-9]+: d8 07 fadds \(%bx\)
*[a-f0-9]+: d8 17 fcoms \(%bx\)
*[a-f0-9]+: d8 1f fcomps \(%bx\)
@@ -40,23 +53,87 @@ Disassembly of section .text:
*[a-f0-9]+: d9 1f fstps \(%bx\)
*[a-f0-9]+: d8 27 fsubs \(%bx\)
*[a-f0-9]+: d8 2f fsubrs \(%bx\)
+ *[a-f0-9]+: f7 3f idivw \(%bx\)
+ *[a-f0-9]+: f7 2f imulw \(%bx\)
+ *[a-f0-9]+: e5 00 in \$0x0,%ax
+ *[a-f0-9]+: ed in \(%dx\),%ax
+ *[a-f0-9]+: ff 07 incw \(%bx\)
+ *[a-f0-9]+: 6d insw \(%dx\),%es:\(%di\)
+ *[a-f0-9]+: 67 6d insw \(%dx\),%es:\(%edi\)
*[a-f0-9]+: ff 27 jmp \*\(%bx\)
*[a-f0-9]+: 0f 01 17 lgdtw \(%bx\)
*[a-f0-9]+: 0f 01 1f lidtw \(%bx\)
*[a-f0-9]+: 0f 00 17 lldt \(%bx\)
*[a-f0-9]+: 0f 01 37 lmsw \(%bx\)
+ *[a-f0-9]+: ad lods %ds:\(%si\),%ax
+ *[a-f0-9]+: 67 ad lods %ds:\(%esi\),%ax
*[a-f0-9]+: 0f 00 1f ltr \(%bx\)
+ *[a-f0-9]+: c7 07 12 00 movw \$0x12,\(%bx\)
+ *[a-f0-9]+: c7 07 34 12 movw \$0x1234,\(%bx\)
*[a-f0-9]+: 8c 07 mov %es,\(%bx\)
*[a-f0-9]+: 8e 07 mov \(%bx\),%es
+ *[a-f0-9]+: a5 movsw %ds:\(%si\),%es:\(%di\)
+ *[a-f0-9]+: 67 a5 movsw %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+: f7 27 mulw \(%bx\)
+ *[a-f0-9]+: f7 1f negw \(%bx\)
*[a-f0-9]+: 0f 1f 07 nopw \(%bx\)
+ *[a-f0-9]+: f7 17 notw \(%bx\)
*[a-f0-9]+: 83 0f 01 orw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 0f 89 00 orw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 0f 34 12 orw \$0x1234,\(%bx\)
+ *[a-f0-9]+: e7 00 out %ax,\$0x0
+ *[a-f0-9]+: ef out %ax,\(%dx\)
+ *[a-f0-9]+: 6f outsw %ds:\(%si\),\(%dx\)
+ *[a-f0-9]+: 67 6f outsw %ds:\(%esi\),\(%dx\)
*[a-f0-9]+: 8f 07 popw \(%bx\)
*[a-f0-9]+: 07 pop %es
*[a-f0-9]+: f3 0f ae 27 ptwritel \(%bx\)
*[a-f0-9]+: ff 37 pushw \(%bx\)
*[a-f0-9]+: 06 push %es
+ *[a-f0-9]+: d1 17 rclw \(%bx\)
+ *[a-f0-9]+: c1 17 02 rclw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 17 rclw %cl,\(%bx\)
+ *[a-f0-9]+: d1 17 rclw \(%bx\)
+ *[a-f0-9]+: d1 1f rcrw \(%bx\)
+ *[a-f0-9]+: c1 1f 02 rcrw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 1f rcrw %cl,\(%bx\)
+ *[a-f0-9]+: d1 1f rcrw \(%bx\)
+ *[a-f0-9]+: d1 07 rolw \(%bx\)
+ *[a-f0-9]+: c1 07 02 rolw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 07 rolw %cl,\(%bx\)
+ *[a-f0-9]+: d1 07 rolw \(%bx\)
+ *[a-f0-9]+: d1 0f rorw \(%bx\)
+ *[a-f0-9]+: c1 0f 02 rorw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 0f rorw %cl,\(%bx\)
+ *[a-f0-9]+: d1 0f rorw \(%bx\)
*[a-f0-9]+: 83 1f 01 sbbw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 1f 89 00 sbbw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 1f 34 12 sbbw \$0x1234,\(%bx\)
+ *[a-f0-9]+: af scas %es:\(%di\),%ax
+ *[a-f0-9]+: 67 af scas %es:\(%edi\),%ax
+ *[a-f0-9]+: d1 27 shlw \(%bx\)
+ *[a-f0-9]+: c1 27 02 shlw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 27 shlw %cl,\(%bx\)
+ *[a-f0-9]+: d1 27 shlw \(%bx\)
+ *[a-f0-9]+: d1 3f sarw \(%bx\)
+ *[a-f0-9]+: c1 3f 02 sarw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 3f sarw %cl,\(%bx\)
+ *[a-f0-9]+: d1 3f sarw \(%bx\)
+ *[a-f0-9]+: d1 27 shlw \(%bx\)
+ *[a-f0-9]+: c1 27 02 shlw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 27 shlw %cl,\(%bx\)
+ *[a-f0-9]+: d1 27 shlw \(%bx\)
+ *[a-f0-9]+: d1 2f shrw \(%bx\)
+ *[a-f0-9]+: c1 2f 02 shrw \$0x2,\(%bx\)
+ *[a-f0-9]+: d3 2f shrw %cl,\(%bx\)
+ *[a-f0-9]+: d1 2f shrw \(%bx\)
+ *[a-f0-9]+: ab stos %ax,%es:\(%di\)
+ *[a-f0-9]+: 67 ab stos %ax,%es:\(%edi\)
*[a-f0-9]+: 83 2f 01 subw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 2f 89 00 subw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 2f 34 12 subw \$0x1234,\(%bx\)
+ *[a-f0-9]+: f7 07 89 00 testw \$0x89,\(%bx\)
+ *[a-f0-9]+: f7 07 34 12 testw \$0x1234,\(%bx\)
*[a-f0-9]+: c5 fb 2a 07 vcvtsi2sdl \(%bx\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7f 08 2a 07 vcvtsi2sdl \(%bx\),%xmm0,%xmm0
*[a-f0-9]+: c5 fa 2a 07 vcvtsi2ssl \(%bx\),%xmm0,%xmm0
@@ -64,4 +141,6 @@ Disassembly of section .text:
*[a-f0-9]+: 62 f1 7f 08 7b 07 vcvtusi2sdl \(%bx\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7e 08 7b 07 vcvtusi2ssl \(%bx\),%xmm0,%xmm0
*[a-f0-9]+: 83 37 01 xorw \$0x1,\(%bx\)
+ *[a-f0-9]+: 81 37 89 00 xorw \$0x89,\(%bx\)
+ *[a-f0-9]+: 81 37 34 12 xorw \$0x1234,\(%bx\)
#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg16.l
@@ -0,0 +1,115 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg16.s
+++ b/gas/testsuite/gas/i386/noreg16.s
@@ -2,16 +2,28 @@
.code16
noreg:
adc $1, (%bx)
+ adc $0x89, (%bx)
+ adc $0x1234, (%bx)
add $1, (%bx)
+ add $0x89, (%bx)
+ add $0x1234, (%bx)
and $1, (%bx)
+ and $0x89, (%bx)
+ and $0x1234, (%bx)
bt $1, (%bx)
btc $1, (%bx)
btr $1, (%bx)
bts $1, (%bx)
call *(%bx)
cmp $1, (%bx)
+ cmp $0x89, (%bx)
+ cmp $0x1234, (%bx)
+ cmps
+ cmps %es:(%edi), (%esi)
cvtsi2sd (%bx), %xmm0
cvtsi2ss (%bx), %xmm0
+ dec (%bx)
+ div (%bx)
fadd (%bx)
fcom (%bx)
fcomp (%bx)
@@ -35,23 +47,87 @@ noreg:
fstp (%bx)
fsub (%bx)
fsubr (%bx)
+ idiv (%bx)
+ imul (%bx)
+ in $0
+ in %dx
+ inc (%bx)
+ ins
+ ins %dx, %es:(%edi)
jmp *(%bx)
lgdt (%bx)
lidt (%bx)
lldt (%bx)
lmsw (%bx)
+ lods
+ lods (%esi)
ltr (%bx)
+ mov $0x12, (%bx)
+ mov $0x1234, (%bx)
mov %es, (%bx)
mov (%bx), %es
+ movs
+ movs (%esi), %es:(%edi)
+ mul (%bx)
+ neg (%bx)
nop (%bx)
+ not (%bx)
or $1, (%bx)
+ or $0x89, (%bx)
+ or $0x1234, (%bx)
+ out $0
+ out %dx
+ outs
+ outs (%esi), %dx
pop (%bx)
pop %es
ptwrite (%bx)
push (%bx)
push %es
+ rcl $1, (%bx)
+ rcl $2, (%bx)
+ rcl %cl, (%bx)
+ rcl (%bx)
+ rcr $1, (%bx)
+ rcr $2, (%bx)
+ rcr %cl, (%bx)
+ rcr (%bx)
+ rol $1, (%bx)
+ rol $2, (%bx)
+ rol %cl, (%bx)
+ rol (%bx)
+ ror $1, (%bx)
+ ror $2, (%bx)
+ ror %cl, (%bx)
+ ror (%bx)
sbb $1, (%bx)
+ sbb $0x89, (%bx)
+ sbb $0x1234, (%bx)
+ scas
+ scas %es:(%edi)
+ sal $1, (%bx)
+ sal $2, (%bx)
+ sal %cl, (%bx)
+ sal (%bx)
+ sar $1, (%bx)
+ sar $2, (%bx)
+ sar %cl, (%bx)
+ sar (%bx)
+ shl $1, (%bx)
+ shl $2, (%bx)
+ shl %cl, (%bx)
+ shl (%bx)
+ shr $1, (%bx)
+ shr $2, (%bx)
+ shr %cl, (%bx)
+ shr (%bx)
+ stos
+ stos %es:(%edi)
sub $1, (%bx)
+ sub $0x89, (%bx)
+ sub $0x1234, (%bx)
+ test $0x89, (%bx)
+ test $0x1234, (%bx)
vcvtsi2sd (%bx), %xmm0, %xmm0
{evex} vcvtsi2sd (%bx), %xmm0, %xmm0
vcvtsi2ss (%bx), %xmm0, %xmm0
@@ -59,3 +135,5 @@ noreg:
vcvtusi2sd (%bx), %xmm0, %xmm0
vcvtusi2ss (%bx), %xmm0, %xmm0
xor $1, (%bx)
+ xor $0x89, (%bx)
+ xor $0x1234, (%bx)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -1,3 +1,4 @@
+#as: -moperand-check=none
#objdump: -dw
#name: 32-bit insns not sizeable through register operands
@@ -7,16 +8,32 @@ Disassembly of section .text:
0+ <noreg>:
*[a-f0-9]+: 83 10 01 adcl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 10 89 00 00 00 adcl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 10 34 12 00 00 adcl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 10 78 56 34 12 adcl \$0x12345678,\(%eax\)
*[a-f0-9]+: 83 00 01 addl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 00 89 00 00 00 addl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 00 34 12 00 00 addl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 00 78 56 34 12 addl \$0x12345678,\(%eax\)
*[a-f0-9]+: 83 20 01 andl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 20 89 00 00 00 andl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 20 34 12 00 00 andl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 20 78 56 34 12 andl \$0x12345678,\(%eax\)
*[a-f0-9]+: 0f ba 20 01 btl \$0x1,\(%eax\)
*[a-f0-9]+: 0f ba 38 01 btcl \$0x1,\(%eax\)
*[a-f0-9]+: 0f ba 30 01 btrl \$0x1,\(%eax\)
*[a-f0-9]+: 0f ba 28 01 btsl \$0x1,\(%eax\)
*[a-f0-9]+: ff 10 call \*\(%eax\)
*[a-f0-9]+: 83 38 01 cmpl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 38 89 00 00 00 cmpl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 38 34 12 00 00 cmpl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%eax\)
+ *[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%eax\),%xmm0
*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%eax\),%xmm0
+ *[a-f0-9]+: ff 08 decl \(%eax\)
+ *[a-f0-9]+: f7 30 divl \(%eax\)
*[a-f0-9]+: d8 00 fadds \(%eax\)
*[a-f0-9]+: d8 10 fcoms \(%eax\)
*[a-f0-9]+: d8 18 fcomps \(%eax\)
@@ -40,23 +57,92 @@ Disassembly of section .text:
*[a-f0-9]+: d9 18 fstps \(%eax\)
*[a-f0-9]+: d8 20 fsubs \(%eax\)
*[a-f0-9]+: d8 28 fsubrs \(%eax\)
+ *[a-f0-9]+: f7 38 idivl \(%eax\)
+ *[a-f0-9]+: f7 28 imull \(%eax\)
+ *[a-f0-9]+: e5 00 in \$0x0,%eax
+ *[a-f0-9]+: ed in \(%dx\),%eax
+ *[a-f0-9]+: ff 00 incl \(%eax\)
+ *[a-f0-9]+: 6d insl \(%dx\),%es:\(%edi\)
+ *[a-f0-9]+: 6d insl \(%dx\),%es:\(%edi\)
*[a-f0-9]+: ff 20 jmp \*\(%eax\)
*[a-f0-9]+: 0f 01 10 lgdtl \(%eax\)
*[a-f0-9]+: 0f 01 18 lidtl \(%eax\)
*[a-f0-9]+: 0f 00 10 lldt \(%eax\)
*[a-f0-9]+: 0f 01 30 lmsw \(%eax\)
+ *[a-f0-9]+: ad lods %ds:\(%esi\),%eax
+ *[a-f0-9]+: ad lods %ds:\(%esi\),%eax
*[a-f0-9]+: 0f 00 18 ltr \(%eax\)
+ *[a-f0-9]+: c7 00 12 00 00 00 movl \$0x12,\(%eax\)
+ *[a-f0-9]+: c7 00 34 12 00 00 movl \$0x1234,\(%eax\)
+ *[a-f0-9]+: c7 00 78 56 34 12 movl \$0x12345678,\(%eax\)
*[a-f0-9]+: 8c 00 mov %es,\(%eax\)
*[a-f0-9]+: 8e 00 mov \(%eax\),%es
+ *[a-f0-9]+: a5 movsl %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+: a5 movsl %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+: f7 20 mull \(%eax\)
+ *[a-f0-9]+: f7 18 negl \(%eax\)
*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
+ *[a-f0-9]+: f7 10 notl \(%eax\)
*[a-f0-9]+: 83 08 01 orl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 08 89 00 00 00 orl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 08 34 12 00 00 orl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 08 78 56 34 12 orl \$0x12345678,\(%eax\)
+ *[a-f0-9]+: e7 00 out %eax,\$0x0
+ *[a-f0-9]+: ef out %eax,\(%dx\)
+ *[a-f0-9]+: 6f outsl %ds:\(%esi\),\(%dx\)
+ *[a-f0-9]+: 6f outsl %ds:\(%esi\),\(%dx\)
*[a-f0-9]+: 8f 00 popl \(%eax\)
*[a-f0-9]+: 07 pop %es
*[a-f0-9]+: f3 0f ae 20 ptwritel \(%eax\)
*[a-f0-9]+: ff 30 pushl \(%eax\)
*[a-f0-9]+: 06 push %es
+ *[a-f0-9]+: d1 10 rcll \(%eax\)
+ *[a-f0-9]+: c1 10 02 rcll \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 10 rcll %cl,\(%eax\)
+ *[a-f0-9]+: d1 10 rcll \(%eax\)
+ *[a-f0-9]+: d1 18 rcrl \(%eax\)
+ *[a-f0-9]+: c1 18 02 rcrl \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 18 rcrl %cl,\(%eax\)
+ *[a-f0-9]+: d1 18 rcrl \(%eax\)
+ *[a-f0-9]+: d1 00 roll \(%eax\)
+ *[a-f0-9]+: c1 00 02 roll \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 00 roll %cl,\(%eax\)
+ *[a-f0-9]+: d1 00 roll \(%eax\)
+ *[a-f0-9]+: d1 08 rorl \(%eax\)
+ *[a-f0-9]+: c1 08 02 rorl \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 08 rorl %cl,\(%eax\)
+ *[a-f0-9]+: d1 08 rorl \(%eax\)
*[a-f0-9]+: 83 18 01 sbbl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 18 89 00 00 00 sbbl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 18 34 12 00 00 sbbl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 18 78 56 34 12 sbbl \$0x12345678,\(%eax\)
+ *[a-f0-9]+: af scas %es:\(%edi\),%eax
+ *[a-f0-9]+: af scas %es:\(%edi\),%eax
+ *[a-f0-9]+: d1 20 shll \(%eax\)
+ *[a-f0-9]+: c1 20 02 shll \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 20 shll %cl,\(%eax\)
+ *[a-f0-9]+: d1 20 shll \(%eax\)
+ *[a-f0-9]+: d1 38 sarl \(%eax\)
+ *[a-f0-9]+: c1 38 02 sarl \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 38 sarl %cl,\(%eax\)
+ *[a-f0-9]+: d1 38 sarl \(%eax\)
+ *[a-f0-9]+: d1 20 shll \(%eax\)
+ *[a-f0-9]+: c1 20 02 shll \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 20 shll %cl,\(%eax\)
+ *[a-f0-9]+: d1 20 shll \(%eax\)
+ *[a-f0-9]+: d1 28 shrl \(%eax\)
+ *[a-f0-9]+: c1 28 02 shrl \$0x2,\(%eax\)
+ *[a-f0-9]+: d3 28 shrl %cl,\(%eax\)
+ *[a-f0-9]+: d1 28 shrl \(%eax\)
+ *[a-f0-9]+: ab stos %eax,%es:\(%edi\)
+ *[a-f0-9]+: ab stos %eax,%es:\(%edi\)
*[a-f0-9]+: 83 28 01 subl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 28 89 00 00 00 subl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 28 34 12 00 00 subl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 28 78 56 34 12 subl \$0x12345678,\(%eax\)
+ *[a-f0-9]+: f7 00 89 00 00 00 testl \$0x89,\(%eax\)
+ *[a-f0-9]+: f7 00 34 12 00 00 testl \$0x1234,\(%eax\)
+ *[a-f0-9]+: f7 00 78 56 34 12 testl \$0x12345678,\(%eax\)
*[a-f0-9]+: c5 fb 2a 00 vcvtsi2sdl \(%eax\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7f 08 2a 00 vcvtsi2sdl \(%eax\),%xmm0,%xmm0
*[a-f0-9]+: c5 fa 2a 00 vcvtsi2ssl \(%eax\),%xmm0,%xmm0
@@ -64,4 +150,7 @@ Disassembly of section .text:
*[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sdl \(%eax\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ssl \(%eax\),%xmm0,%xmm0
*[a-f0-9]+: 83 30 01 xorl \$0x1,\(%eax\)
+ *[a-f0-9]+: 81 30 89 00 00 00 xorl \$0x89,\(%eax\)
+ *[a-f0-9]+: 81 30 34 12 00 00 xorl \$0x1234,\(%eax\)
+ *[a-f0-9]+: 81 30 78 56 34 12 xorl \$0x12345678,\(%eax\)
#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg32.l
@@ -0,0 +1,125 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg32.s
+++ b/gas/testsuite/gas/i386/noreg32.s
@@ -1,16 +1,32 @@
.text
noreg:
adc $1, (%eax)
+ adc $0x89, (%eax)
+ adc $0x1234, (%eax)
+ adc $0x12345678, (%eax)
add $1, (%eax)
+ add $0x89, (%eax)
+ add $0x1234, (%eax)
+ add $0x12345678, (%eax)
and $1, (%eax)
+ and $0x89, (%eax)
+ and $0x1234, (%eax)
+ and $0x12345678, (%eax)
bt $1, (%eax)
btc $1, (%eax)
btr $1, (%eax)
bts $1, (%eax)
call *(%eax)
cmp $1, (%eax)
+ cmp $0x89, (%eax)
+ cmp $0x1234, (%eax)
+ cmp $0x12345678, (%eax)
+ cmps
+ cmps %es:(%edi), (%esi)
cvtsi2sd (%eax), %xmm0
cvtsi2ss (%eax), %xmm0
+ dec (%eax)
+ div (%eax)
fadd (%eax)
fcom (%eax)
fcomp (%eax)
@@ -34,23 +50,92 @@ noreg:
fstp (%eax)
fsub (%eax)
fsubr (%eax)
+ idiv (%eax)
+ imul (%eax)
+ in $0
+ in %dx
+ inc (%eax)
+ ins
+ ins %dx, %es:(%edi)
jmp *(%eax)
lgdt (%eax)
lidt (%eax)
lldt (%eax)
lmsw (%eax)
+ lods
+ lods (%esi)
ltr (%eax)
+ mov $0x12, (%eax)
+ mov $0x1234, (%eax)
+ mov $0x12345678, (%eax)
mov %es, (%eax)
mov (%eax), %es
+ movs
+ movs (%esi), %es:(%edi)
+ mul (%eax)
+ neg (%eax)
nop (%eax)
+ not (%eax)
or $1, (%eax)
+ or $0x89, (%eax)
+ or $0x1234, (%eax)
+ or $0x12345678, (%eax)
+ out $0
+ out %dx
+ outs
+ outs (%esi), %dx
pop (%eax)
pop %es
ptwrite (%eax)
push (%eax)
push %es
+ rcl $1, (%eax)
+ rcl $2, (%eax)
+ rcl %cl, (%eax)
+ rcl (%eax)
+ rcr $1, (%eax)
+ rcr $2, (%eax)
+ rcr %cl, (%eax)
+ rcr (%eax)
+ rol $1, (%eax)
+ rol $2, (%eax)
+ rol %cl, (%eax)
+ rol (%eax)
+ ror $1, (%eax)
+ ror $2, (%eax)
+ ror %cl, (%eax)
+ ror (%eax)
sbb $1, (%eax)
+ sbb $0x89, (%eax)
+ sbb $0x1234, (%eax)
+ sbb $0x12345678, (%eax)
+ scas
+ scas %es:(%edi)
+ sal $1, (%eax)
+ sal $2, (%eax)
+ sal %cl, (%eax)
+ sal (%eax)
+ sar $1, (%eax)
+ sar $2, (%eax)
+ sar %cl, (%eax)
+ sar (%eax)
+ shl $1, (%eax)
+ shl $2, (%eax)
+ shl %cl, (%eax)
+ shl (%eax)
+ shr $1, (%eax)
+ shr $2, (%eax)
+ shr %cl, (%eax)
+ shr (%eax)
+ stos
+ stos %es:(%edi)
sub $1, (%eax)
+ sub $0x89, (%eax)
+ sub $0x1234, (%eax)
+ sub $0x12345678, (%eax)
+ test $0x89, (%eax)
+ test $0x1234, (%eax)
+ test $0x12345678, (%eax)
vcvtsi2sd (%eax), %xmm0, %xmm0
{evex} vcvtsi2sd (%eax), %xmm0, %xmm0
vcvtsi2ss (%eax), %xmm0, %xmm0
@@ -58,3 +143,6 @@ noreg:
vcvtusi2sd (%eax), %xmm0, %xmm0
vcvtusi2ss (%eax), %xmm0, %xmm0
xor $1, (%eax)
+ xor $0x89, (%eax)
+ xor $0x1234, (%eax)
+ xor $0x12345678, (%eax)
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -1,3 +1,4 @@
+#as: -moperand-check=none
#objdump: -dw
#name: 64-bit insns not sizeable through register operands
@@ -7,16 +8,32 @@ Disassembly of section .text:
0+ <noreg>:
*[a-f0-9]+: 83 10 01 adcl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 10 89 00 00 00 adcl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 10 34 12 00 00 adcl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 10 78 56 34 12 adcl \$0x12345678,\(%rax\)
*[a-f0-9]+: 83 00 01 addl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 00 89 00 00 00 addl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 00 34 12 00 00 addl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 00 78 56 34 12 addl \$0x12345678,\(%rax\)
*[a-f0-9]+: 83 20 01 andl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 20 89 00 00 00 andl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 20 34 12 00 00 andl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 20 78 56 34 12 andl \$0x12345678,\(%rax\)
*[a-f0-9]+: 0f ba 20 01 btl \$0x1,\(%rax\)
*[a-f0-9]+: 0f ba 38 01 btcl \$0x1,\(%rax\)
*[a-f0-9]+: 0f ba 30 01 btrl \$0x1,\(%rax\)
*[a-f0-9]+: 0f ba 28 01 btsl \$0x1,\(%rax\)
*[a-f0-9]+: ff 10 callq \*\(%rax\)
*[a-f0-9]+: 83 38 01 cmpl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 38 89 00 00 00 cmpl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 38 34 12 00 00 cmpl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%rax\)
+ *[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
+ *[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
+ *[a-f0-9]+: ff 08 decl \(%rax\)
+ *[a-f0-9]+: f7 30 divl \(%rax\)
*[a-f0-9]+: d8 00 fadds \(%rax\)
*[a-f0-9]+: d8 10 fcoms \(%rax\)
*[a-f0-9]+: d8 18 fcomps \(%rax\)
@@ -40,23 +57,93 @@ Disassembly of section .text:
*[a-f0-9]+: d9 18 fstps \(%rax\)
*[a-f0-9]+: d8 20 fsubs \(%rax\)
*[a-f0-9]+: d8 28 fsubrs \(%rax\)
+ *[a-f0-9]+: f7 38 idivl \(%rax\)
+ *[a-f0-9]+: f7 28 imull \(%rax\)
+ *[a-f0-9]+: e5 00 in \$0x0,%eax
+ *[a-f0-9]+: ed in \(%dx\),%eax
+ *[a-f0-9]+: ff 00 incl \(%rax\)
+ *[a-f0-9]+: 6d insl \(%dx\),%es:\(%rdi\)
+ *[a-f0-9]+: 6d insl \(%dx\),%es:\(%rdi\)
*[a-f0-9]+: ff 20 jmpq \*\(%rax\)
*[a-f0-9]+: 0f 01 10 lgdt \(%rax\)
*[a-f0-9]+: 0f 01 18 lidt \(%rax\)
*[a-f0-9]+: 0f 00 10 lldt \(%rax\)
*[a-f0-9]+: 0f 01 30 lmsw \(%rax\)
+ *[a-f0-9]+: ad lods %ds:\(%rsi\),%eax
+ *[a-f0-9]+: ad lods %ds:\(%rsi\),%eax
*[a-f0-9]+: 0f 00 18 ltr \(%rax\)
+ *[a-f0-9]+: c7 00 12 00 00 00 movl \$0x12,\(%rax\)
+ *[a-f0-9]+: c7 00 34 12 00 00 movl \$0x1234,\(%rax\)
+ *[a-f0-9]+: c7 00 78 56 34 12 movl \$0x12345678,\(%rax\)
*[a-f0-9]+: 8c 00 mov %es,\(%rax\)
*[a-f0-9]+: 8e 00 mov \(%rax\),%es
+ *[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\)
+ *[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\)
+ *[a-f0-9]+: f7 20 mull \(%rax\)
+ *[a-f0-9]+: f7 18 negl \(%rax\)
*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
+ *[a-f0-9]+: f7 10 notl \(%rax\)
*[a-f0-9]+: 83 08 01 orl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 08 89 00 00 00 orl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 08 34 12 00 00 orl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 08 78 56 34 12 orl \$0x12345678,\(%rax\)
+ *[a-f0-9]+: e7 00 out %eax,\$0x0
+ *[a-f0-9]+: ef out %eax,\(%dx\)
+ *[a-f0-9]+: 6f outsl %ds:\(%rsi\),\(%dx\)
+ *[a-f0-9]+: 6f outsl %ds:\(%rsi\),\(%dx\)
*[a-f0-9]+: 8f 00 popq \(%rax\)
*[a-f0-9]+: 0f a1 popq %fs
*[a-f0-9]+: f3 0f ae 20 ptwritel \(%rax\)
*[a-f0-9]+: ff 30 pushq \(%rax\)
*[a-f0-9]+: 0f a0 pushq %fs
+ *[a-f0-9]+: d1 10 rcll \(%rax\)
+ *[a-f0-9]+: c1 10 02 rcll \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 10 rcll %cl,\(%rax\)
+ *[a-f0-9]+: d1 10 rcll \(%rax\)
+ *[a-f0-9]+: d1 18 rcrl \(%rax\)
+ *[a-f0-9]+: c1 18 02 rcrl \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 18 rcrl %cl,\(%rax\)
+ *[a-f0-9]+: d1 18 rcrl \(%rax\)
+ *[a-f0-9]+: d1 00 roll \(%rax\)
+ *[a-f0-9]+: c1 00 02 roll \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 00 roll %cl,\(%rax\)
+ *[a-f0-9]+: d1 00 roll \(%rax\)
+ *[a-f0-9]+: d1 08 rorl \(%rax\)
+ *[a-f0-9]+: c1 08 02 rorl \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 08 rorl %cl,\(%rax\)
+ *[a-f0-9]+: d1 08 rorl \(%rax\)
*[a-f0-9]+: 83 18 01 sbbl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 18 89 00 00 00 sbbl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 18 34 12 00 00 sbbl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 18 78 56 34 12 sbbl \$0x12345678,\(%rax\)
+ *[a-f0-9]+: af scas %es:\(%rdi\),%eax
+ *[a-f0-9]+: af scas %es:\(%rdi\),%eax
+ *[a-f0-9]+: d1 20 shll \(%rax\)
+ *[a-f0-9]+: c1 20 02 shll \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 20 shll %cl,\(%rax\)
+ *[a-f0-9]+: d1 20 shll \(%rax\)
+ *[a-f0-9]+: d1 38 sarl \(%rax\)
+ *[a-f0-9]+: c1 38 02 sarl \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 38 sarl %cl,\(%rax\)
+ *[a-f0-9]+: d1 38 sarl \(%rax\)
+ *[a-f0-9]+: d1 20 shll \(%rax\)
+ *[a-f0-9]+: c1 20 02 shll \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 20 shll %cl,\(%rax\)
+ *[a-f0-9]+: d1 20 shll \(%rax\)
+ *[a-f0-9]+: d1 28 shrl \(%rax\)
+ *[a-f0-9]+: c1 28 02 shrl \$0x2,\(%rax\)
+ *[a-f0-9]+: d3 28 shrl %cl,\(%rax\)
+ *[a-f0-9]+: d1 28 shrl \(%rax\)
+ *[a-f0-9]+: ab stos %eax,%es:\(%rdi\)
+ *[a-f0-9]+: ab stos %eax,%es:\(%rdi\)
*[a-f0-9]+: 83 28 01 subl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 28 89 00 00 00 subl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 28 34 12 00 00 subl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 28 78 56 34 12 subl \$0x12345678,\(%rax\)
+ *[a-f0-9]+: 0f 07 sysret *
+ *[a-f0-9]+: f7 00 89 00 00 00 testl \$0x89,\(%rax\)
+ *[a-f0-9]+: f7 00 34 12 00 00 testl \$0x1234,\(%rax\)
+ *[a-f0-9]+: f7 00 78 56 34 12 testl \$0x12345678,\(%rax\)
*[a-f0-9]+: c5 fb 2a 00 vcvtsi2sdl \(%rax\),%xmm0,%xmm0
*[a-f0-9]+: 62 61 7f 08 2a 38 vcvtsi2sdl \(%rax\),%xmm0,%xmm31
*[a-f0-9]+: c5 fa 2a 00 vcvtsi2ssl \(%rax\),%xmm0,%xmm0
@@ -64,4 +151,7 @@ Disassembly of section .text:
*[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sdl \(%rax\),%xmm0,%xmm0
*[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ssl \(%rax\),%xmm0,%xmm0
*[a-f0-9]+: 83 30 01 xorl \$0x1,\(%rax\)
+ *[a-f0-9]+: 81 30 89 00 00 00 xorl \$0x89,\(%rax\)
+ *[a-f0-9]+: 81 30 34 12 00 00 xorl \$0x1234,\(%rax\)
+ *[a-f0-9]+: 81 30 78 56 34 12 xorl \$0x12345678,\(%rax\)
#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -0,0 +1,135 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `ptwrite'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sysret'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `vcvtusi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtusi2ss'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -1,16 +1,32 @@
.text
noreg:
adc $1, (%rax)
+ adc $0x89, (%rax)
+ adc $0x1234, (%rax)
+ adc $0x12345678, (%rax)
add $1, (%rax)
+ add $0x89, (%rax)
+ add $0x1234, (%rax)
+ add $0x12345678, (%rax)
and $1, (%rax)
+ and $0x89, (%rax)
+ and $0x1234, (%rax)
+ and $0x12345678, (%rax)
bt $1, (%rax)
btc $1, (%rax)
btr $1, (%rax)
bts $1, (%rax)
call *(%rax)
cmp $1, (%rax)
+ cmp $0x89, (%rax)
+ cmp $0x1234, (%rax)
+ cmp $0x12345678, (%rax)
+ cmps
+ cmps %es:(%rdi), (%rsi)
cvtsi2sd (%rax), %xmm0
cvtsi2ss (%rax), %xmm0
+ dec (%rax)
+ div (%rax)
fadd (%rax)
fcom (%rax)
fcomp (%rax)
@@ -34,23 +50,93 @@ noreg:
fstp (%rax)
fsub (%rax)
fsubr (%rax)
+ idiv (%rax)
+ imul (%rax)
+ in $0
+ in %dx
+ inc (%rax)
+ ins
+ ins %dx, %es:(%rdi)
jmp *(%rax)
lgdt (%rax)
lidt (%rax)
lldt (%rax)
lmsw (%rax)
+ lods
+ lods (%rsi)
ltr (%rax)
+ mov $0x12, (%rax)
+ mov $0x1234, (%rax)
+ mov $0x12345678, (%rax)
mov %es, (%rax)
mov (%rax), %es
+ movs
+ movs (%rsi), %es:(%rdi)
+ mul (%rax)
+ neg (%rax)
nop (%rax)
+ not (%rax)
or $1, (%rax)
+ or $0x89, (%rax)
+ or $0x1234, (%rax)
+ or $0x12345678, (%rax)
+ out $0
+ out %dx
+ outs
+ outs (%rsi), %dx
pop (%rax)
pop %fs
ptwrite (%rax)
push (%rax)
push %fs
+ rcl $1, (%rax)
+ rcl $2, (%rax)
+ rcl %cl, (%rax)
+ rcl (%rax)
+ rcr $1, (%rax)
+ rcr $2, (%rax)
+ rcr %cl, (%rax)
+ rcr (%rax)
+ rol $1, (%rax)
+ rol $2, (%rax)
+ rol %cl, (%rax)
+ rol (%rax)
+ ror $1, (%rax)
+ ror $2, (%rax)
+ ror %cl, (%rax)
+ ror (%rax)
sbb $1, (%rax)
+ sbb $0x89, (%rax)
+ sbb $0x1234, (%rax)
+ sbb $0x12345678, (%rax)
+ scas
+ scas %es:(%rdi)
+ sal $1, (%rax)
+ sal $2, (%rax)
+ sal %cl, (%rax)
+ sal (%rax)
+ sar $1, (%rax)
+ sar $2, (%rax)
+ sar %cl, (%rax)
+ sar (%rax)
+ shl $1, (%rax)
+ shl $2, (%rax)
+ shl %cl, (%rax)
+ shl (%rax)
+ shr $1, (%rax)
+ shr $2, (%rax)
+ shr %cl, (%rax)
+ shr (%rax)
+ stos
+ stos %es:(%rdi)
sub $1, (%rax)
+ sub $0x89, (%rax)
+ sub $0x1234, (%rax)
+ sub $0x12345678, (%rax)
+ sysret
+ test $0x89, (%rax)
+ test $0x1234, (%rax)
+ test $0x12345678, (%rax)
vcvtsi2sd (%rax), %xmm0, %xmm0
vcvtsi2sd (%rax), %xmm0, %xmm31
vcvtsi2ss (%rax), %xmm0, %xmm0
@@ -58,3 +144,6 @@ noreg:
vcvtusi2sd (%rax), %xmm0, %xmm0
vcvtusi2ss (%rax), %xmm0, %xmm0
xor $1, (%rax)
+ xor $0x89, (%rax)
+ xor $0x1234, (%rax)
+ xor $0x12345678, (%rax)
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -211,8 +211,8 @@ foo:
fistl 0x90909090(%eax)
fcoml 0x90909090(%eax)
fstl 0x90909090(%eax)
- ficom 0x90909090(%eax)
- fist 0x90909090(%eax)
+ ficoms 0x90909090(%eax)
+ fists 0x90909090(%eax)
loopne .+2-0x70
loope .+2-0x70
loop .+2-0x70
--- a/gas/testsuite/gas/i386/sse-noavx.d
+++ b/gas/testsuite/gas/i386/sse-noavx.d
@@ -15,7 +15,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 2c dc cvttpd2pi %xmm4,%mm3
[ ]*[a-f0-9]+: 0f 2c dc cvttps2pi %xmm4,%mm3
[ ]*[a-f0-9]+: df 08 fisttps \(%eax\)
-[ ]*[a-f0-9]+: df 08 fisttps \(%eax\)
[ ]*[a-f0-9]+: db 08 fisttpl \(%eax\)
[ ]*[a-f0-9]+: dd 08 fisttpll \(%eax\)
[ ]*[a-f0-9]+: 0f ae e8 lfence
--- a/gas/testsuite/gas/i386/sse-noavx.s
+++ b/gas/testsuite/gas/i386/sse-noavx.s
@@ -9,7 +9,6 @@ _start:
cvtps2pi %xmm7,%mm6
cvttpd2pi %xmm4,%mm3
cvttps2pi %xmm4,%mm3
- fisttp (%eax)
fisttps (%eax)
fisttpl (%eax)
fisttpll (%eax)
--- a/gas/testsuite/gas/i386/sse3.s
+++ b/gas/testsuite/gas/i386/sse3.s
@@ -6,7 +6,7 @@ foo:
addsubpd %xmm2,%xmm1
addsubps (%ebx),%xmm2
addsubps %xmm4,%xmm3
- fisttp 0x90909090(%eax)
+ fisttps 0x90909090(%eax)
fisttpl 0x90909090(%eax)
fisttpll 0x90909090(%eax)
haddpd 0x0(%ebp),%xmm4
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar.s
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.s
@@ -234,9 +234,9 @@ _start:
# Tests for op regl/mem32, xmm, xmm
vcvtsi2sd %ecx,%xmm4,%xmm6
- vcvtsi2sd (%rcx),%xmm4,%xmm6
+ vcvtsi2sdl (%rcx),%xmm4,%xmm6
vcvtsi2ss %ecx,%xmm4,%xmm6
- vcvtsi2ss (%rcx),%xmm4,%xmm6
+ vcvtsi2ssl (%rcx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem32, xmm, xmm
vcmpss $7,%xmm4,%xmm6,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-avx.s
+++ b/gas/testsuite/gas/i386/x86-64-avx.s
@@ -1222,9 +1222,9 @@ _start:
# Tests for op regl/mem32, xmm, xmm
vcvtsi2sd %ecx,%xmm4,%xmm6
- vcvtsi2sd (%rcx),%xmm4,%xmm6
+ vcvtsi2sdl (%rcx),%xmm4,%xmm6
vcvtsi2ss %ecx,%xmm4,%xmm6
- vcvtsi2ss (%rcx),%xmm4,%xmm6
+ vcvtsi2ssl (%rcx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem32, xmm, xmm
vcmpss $7,%xmm4,%xmm6,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-bundle.s
+++ b/gas/testsuite/gas/i386/x86-64-bundle.s
@@ -58,7 +58,7 @@
and $3,%eax
.endm
.macro test_4
- lock and $3,(%rax)
+ lock andl $3,(%rax)
.endm
.macro test_5
mov $0x11223344,%eax
--- a/gas/testsuite/gas/i386/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/x86-64-intel64.d
@@ -14,6 +14,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b2 1a lss \(%rdx\),%rbx
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f 07 sysret
+[ ]*[a-f0-9]+: 48 0f 07 sysretq *
[ ]*[a-f0-9]+: 48 0f b4 01 lfs \(%rcx\),%rax
[ ]*[a-f0-9]+: 48 0f b4 01 lfs \(%rcx\),%rax
[ ]*[a-f0-9]+: 48 0f b5 0a lgs \(%rdx\),%rcx
--- a/gas/testsuite/gas/i386/x86-64-intel64.s
+++ b/gas/testsuite/gas/i386/x86-64-intel64.s
@@ -11,7 +11,8 @@ _start:
lssq (%rdx), %rbx
syscall
- sysret
+ sysretl
+ sysretq
.intel_syntax noprefix
lfs rax, [rcx]
--- a/gas/testsuite/gas/i386/x86-64-lock-1.s
+++ b/gas/testsuite/gas/i386/x86-64-lock-1.s
@@ -3,17 +3,17 @@
.text
foo:
lock add %eax, (%rbx)
- lock add $0x64, (%rbx)
+ lock addl $0x64, (%rbx)
lock adc %eax, (%rbx)
- lock adc $0x64, (%rbx)
+ lock adcl $0x64, (%rbx)
lock and %eax, (%rbx)
- lock and $0x64, (%rbx)
+ lock andl $0x64, (%rbx)
lock btc %eax, (%rbx)
- lock btc $0x64, (%rbx)
+ lock btcl $0x64, (%rbx)
lock btr %eax, (%rbx)
- lock btr $0x64, (%rbx)
+ lock btrl $0x64, (%rbx)
lock bts %eax, (%rbx)
- lock bts $0x64, (%rbx)
+ lock btsl $0x64, (%rbx)
lock cmpxchg %eax,(%rbx)
lock cmpxchg8b (%rbx)
lock cmpxchg16b (%rbx)
@@ -22,16 +22,16 @@ foo:
lock negl (%rbx)
lock notl (%rbx)
lock or %eax, (%rbx)
- lock or $0x64, (%rbx)
+ lock orl $0x64, (%rbx)
lock sbb %eax, (%rbx)
- lock sbb $0x64, (%rbx)
+ lock sbbl $0x64, (%rbx)
lock sub %eax, (%rbx)
- lock sub $0x64, (%rbx)
+ lock subl $0x64, (%rbx)
lock xadd %eax, (%rbx)
lock xchg (%rbx), %eax
lock xchg %eax, (%rbx)
lock xor %eax, (%rbx)
- lock xor $0x64, (%rbx)
+ lock xorl $0x64, (%rbx)
.intel_syntax noprefix
lock add DWORD PTR [rbx],eax
--- a/gas/testsuite/gas/i386/x86-64-nops.d
+++ b/gas/testsuite/gas/i386/x86-64-nops.d
@@ -41,7 +41,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1d 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1e 04 59 nopl \(%rcx,%rbx,2\)
[ ]*[a-f0-9]+: 0f 1f 04 59 nopl \(%rcx,%rbx,2\)
-[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
[ ]*[a-f0-9]+: 48 0f 1f c0 nop %rax
[ ]*[a-f0-9]+: 0f 1f c0 nop %eax
[ ]*[a-f0-9]+: 66 0f 1f c0 nop %ax
@@ -51,7 +50,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f 1f c0 nop %rax
[ ]*[a-f0-9]+: 0f 1f c0 nop %eax
[ ]*[a-f0-9]+: 66 0f 1f c0 nop %ax
-[ ]*[a-f0-9]+: 41 0f 1f 02 nopl \(%r10\)
[ ]*[a-f0-9]+: 49 0f 1f c2 nop %r10
[ ]*[a-f0-9]+: 41 0f 1f c2 nop %r10d
[ ]*[a-f0-9]+: 66 41 0f 1f c2 nop %r10w
--- a/gas/testsuite/gas/i386/x86-64-nops.s
+++ b/gas/testsuite/gas/i386/x86-64-nops.s
@@ -44,7 +44,6 @@
.byte 0x0f, 0x1e, 0x04, 0x59
.byte 0x0f, 0x1f, 0x04, 0x59
- nop (%rax)
nop %rax
nop %eax
nop %ax
@@ -54,7 +53,6 @@
nopq %rax
nopl %eax
nopw %ax
- nop (%r10)
nop %r10
nop %r10d
nop %r10w
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -321,6 +321,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 00 08 str \(%rax\)
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f 07 sysret
+[ ]*[a-f0-9]+: 48 0f 07 sysretq *
[ ]*[a-f0-9]+: 0f 01 f8 swapgs
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222
[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -189,48 +189,48 @@
CVTTSS2SIq %xmm0,%r8 # -- -- F3 4C 0f 2c c0 ; OVR 128-bit media instruction override Result is sign extended REX for 64-bit operand size REX to access upper reg.
# CVTSI2SS
- CVTSI2SS (%r8),%xmm0 # -- -- F3 41 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper reg.
- CVTSI2SS (%rax),%xmm0 # -- -- F3 -- 0f 2a 00 ; OVR 128-bit media instruction override
- CVTSI2SS (%r8),%xmm15 # -- -- F3 45 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
- CVTSI2SS (%rax),%xmm15 # -- -- F3 44 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg
- CVTSI2SS (%r8),%xmm8 # -- -- F3 45 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
- CVTSI2SS (%rax),%xmm8 # -- -- F3 44 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg
- CVTSI2SS (%r8),%xmm7 # -- -- F3 41 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper reg.
- CVTSI2SS (%rax),%xmm7 # -- -- F3 -- 0f 2a 38 ; OVR 128-bit media instruction override
+ CVTSI2SSl (%r8),%xmm0 # -- -- F3 41 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm0 # -- -- F3 -- 0f 2a 00 ; OVR 128-bit media instruction override
+ CVTSI2SSl (%r8),%xmm15 # -- -- F3 45 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm15 # -- -- F3 44 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg
+ CVTSI2SSl (%r8),%xmm8 # -- -- F3 45 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm8 # -- -- F3 44 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg
+ CVTSI2SSl (%r8),%xmm7 # -- -- F3 41 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm7 # -- -- F3 -- 0f 2a 38 ; OVR 128-bit media instruction override
CVTSI2SS %eax,%xmm0 # -- -- F3 -- 0f 2a c0 ; OVR 128-bit media instruction override
CVTSI2SS %eax,%xmm15 # -- -- F3 44 0f 2a f8 ; OVR 128-bit media instruction override REX to access upper XMM reg
CVTSI2SS %eax,%xmm8 # -- -- F3 44 0f 2a c0 ; OVR 128-bit media instruction override REX to access upper XMM reg
CVTSI2SS %eax,%xmm7 # -- -- F3 -- 0f 2a f8 ; OVR 128-bit media instruction override
- CVTSI2SS (%r8),%xmm0 # -- -- F3 41 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper reg.
- CVTSI2SS (%rax),%xmm0 # -- -- F3 -- 0f 2a 00 ; OVR 128-bit media instruction override
- CVTSI2SS (%r8),%xmm15 # -- -- F3 45 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
- CVTSI2SS (%rax),%xmm15 # -- -- F3 44 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg
- CVTSI2SS (%r8),%xmm8 # -- -- F3 45 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
- CVTSI2SS (%rax),%xmm8 # -- -- F3 44 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg
- CVTSI2SS (%r8),%xmm7 # -- -- F3 41 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper reg.
- CVTSI2SS (%rax),%xmm7 # -- -- F3 -- 0f 2a 38 ; OVR 128-bit media instruction override
+ CVTSI2SSl (%r8),%xmm0 # -- -- F3 41 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm0 # -- -- F3 -- 0f 2a 00 ; OVR 128-bit media instruction override
+ CVTSI2SSl (%r8),%xmm15 # -- -- F3 45 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm15 # -- -- F3 44 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper XMM reg
+ CVTSI2SSl (%r8),%xmm8 # -- -- F3 45 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm8 # -- -- F3 44 0f 2a 00 ; OVR 128-bit media instruction override REX to access upper XMM reg
+ CVTSI2SSl (%r8),%xmm7 # -- -- F3 41 0f 2a 38 ; OVR 128-bit media instruction override REX to access upper reg.
+ CVTSI2SSl (%rax),%xmm7 # -- -- F3 -- 0f 2a 38 ; OVR 128-bit media instruction override
# CVTSI2SD
- CVTSI2SD (%r8),%xmm0 # -- -- F2 41 0F 2A 00 ; REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm0 # -- -- F2 -- 0F 2A 00 ; OVR 128bit MMinstr.
- CVTSI2SD (%r8),%xmm15 # -- -- F2 45 0F 2A 38 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm15 # -- -- F2 44 0F 2A 38 ; REX to access upper XMM reg. OVR 128bit MMinstr.
- CVTSI2SD (%r8),%xmm8 # -- -- F2 45 0F 2A 00 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm8 # -- -- F2 44 0F 2A 00 ; REX to access upper XMM reg. OVR 128bit MMinstr.
- CVTSI2SD (%r8),%xmm7 # -- -- F2 41 0F 2A 38 ; REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm7 # -- -- F2 -- 0F 2A 38 ; OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm0 # -- -- F2 41 0F 2A 00 ; REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm0 # -- -- F2 -- 0F 2A 00 ; OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm15 # -- -- F2 45 0F 2A 38 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm15 # -- -- F2 44 0F 2A 38 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm8 # -- -- F2 45 0F 2A 00 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm8 # -- -- F2 44 0F 2A 00 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm7 # -- -- F2 41 0F 2A 38 ; REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm7 # -- -- F2 -- 0F 2A 38 ; OVR 128bit MMinstr.
CVTSI2SD %eax,%xmm0 # -- -- F2 -- 0F 2A C0 ; OVR 128bit MMinstr.
CVTSI2SD %eax,%xmm15 # -- -- F2 44 0F 2A F8 ; REX to access upper XMM reg. OVR 128bit MMinstr.
CVTSI2SD %eax,%xmm8 # -- -- F2 44 0F 2A C0 ; REX to access upper XMM reg. OVR 128bit MMinstr.
CVTSI2SD %eax,%xmm7 # -- -- F2 -- 0F 2A F8 ; OVR 128bit MMinstr.
- CVTSI2SD (%r8),%xmm0 # -- -- F2 41 0F 2A 00 ; REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm0 # -- -- F2 -- 0F 2A 00 ; OVR 128bit MMinstr.
- CVTSI2SD (%r8),%xmm15 # -- -- F2 45 0F 2A 38 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm15 # -- -- F2 44 0F 2A 38 ; REX to access upper XMM reg. OVR 128bit MMinstr.
- CVTSI2SD (%r8),%xmm8 # -- -- F2 45 0F 2A 00 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm8 # -- -- F2 44 0F 2A 00 ; REX to access upper XMM reg. OVR 128bit MMinstr.
- CVTSI2SD (%r8),%xmm7 # -- -- F2 41 0F 2A 38 ; REX to access upper reg. OVR 128bit MMinstr.
- CVTSI2SD (%rax),%xmm7 # -- -- F2 -- 0F 2A 38 ; OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm0 # -- -- F2 41 0F 2A 00 ; REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm0 # -- -- F2 -- 0F 2A 00 ; OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm15 # -- -- F2 45 0F 2A 38 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm15 # -- -- F2 44 0F 2A 38 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm8 # -- -- F2 45 0F 2A 00 ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm8 # -- -- F2 44 0F 2A 00 ; REX to access upper XMM reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%r8),%xmm7 # -- -- F2 41 0F 2A 38 ; REX to access upper reg. OVR 128bit MMinstr.
+ CVTSI2SDl (%rax),%xmm7 # -- -- F2 -- 0F 2A 38 ; OVR 128bit MMinstr.
# MOVD
MOVD (%r8),%xmm0 # -- -- 66 41 0F 6E 00 ; REX to access upper reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
@@ -446,7 +446,8 @@
str (%rax) # -- -- -- -- 0F 00 08
syscall # -- -- -- -- 0F 05
- sysret # -- -- -- -- 0F 07
+ sysretl # -- -- -- -- 0F 07
+ sysretq # -- -- -- 48 0F 07
swapgs # -- -- -- -- 0F 01 f8
--- a/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
@@ -14,7 +14,6 @@ Disassembly of section \.text:
+[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
+[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[rcx\]
- +[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[rcx\]
+[a-f0-9]+: f3 48 0f ae 21 ptwrite QWORD PTR \[rcx\]
+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
+[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
--- a/gas/testsuite/gas/i386/x86-64-ptwrite.d
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite.d
@@ -14,7 +14,6 @@ Disassembly of section \.text:
+[a-f0-9]+: f3 48 0f ae e1 ptwrite %rcx
+[a-f0-9]+: f3 48 0f ae e1 ptwrite %rcx
+[a-f0-9]+: f3 0f ae 21 ptwritel \(%rcx\)
- +[a-f0-9]+: f3 0f ae 21 ptwritel \(%rcx\)
+[a-f0-9]+: f3 48 0f ae 21 ptwriteq \(%rcx\)
+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
+[a-f0-9]+: f3 48 0f ae e1 ptwrite %rcx
--- a/gas/testsuite/gas/i386/x86-64-ptwrite.s
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite.s
@@ -6,7 +6,6 @@ _start:
ptwritel %ecx
ptwrite %rcx
ptwriteq %rcx
- ptwrite (%rcx)
ptwritel (%rcx)
ptwriteq (%rcx)
--- a/gas/testsuite/gas/i386/x86-64-simd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-intel.d
@@ -25,8 +25,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sd xmm1,rax
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[rax\]
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[rax\]
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ss xmm1,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sd xmm1,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps xmm1,XMMWORD PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
--- a/gas/testsuite/gas/i386/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
@@ -25,8 +25,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sdq %rax,%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ssq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sdq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps 0x12345678\(%rip\),%xmm1 # [0-9a-f]+ <_start\+0x[0-9a-f]+>
--- a/gas/testsuite/gas/i386/x86-64-simd.d
+++ b/gas/testsuite/gas/i386/x86-64-simd.d
@@ -24,8 +24,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sd %rax,%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ssq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sdq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps 0x12345678\(%rip\),%xmm1 # [0-9a-f]+ <_start\+0x[0-9a-f]+>
--- a/gas/testsuite/gas/i386/x86-64-simd.s
+++ b/gas/testsuite/gas/i386/x86-64-simd.s
@@ -15,8 +15,6 @@ _start:
cvtsi2sd %rax, %xmm1
cvtsi2ssq %rax, %xmm1
cvtsi2sdq %rax, %xmm1
- cvtsi2ss (%rax), %xmm1
- cvtsi2sd (%rax), %xmm1
cvtsi2ssl (%rax), %xmm1
cvtsi2sdl (%rax), %xmm1
cvtsi2ssq (%rax), %xmm1
--- a/gas/testsuite/gas/i386/x86-64-sse-noavx.d
+++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.d
@@ -16,7 +16,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 2c dc cvttpd2pi %xmm4,%mm3
[ ]*[a-f0-9]+: 0f 2c dc cvttps2pi %xmm4,%mm3
[ ]*[a-f0-9]+: df 08 fisttps \(%rax\)
-[ ]*[a-f0-9]+: df 08 fisttps \(%rax\)
[ ]*[a-f0-9]+: db 08 fisttpl \(%rax\)
[ ]*[a-f0-9]+: dd 08 fisttpll \(%rax\)
[ ]*[a-f0-9]+: 0f ae e8 lfence
--- a/gas/testsuite/gas/i386/x86-64-sse-noavx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.s
@@ -10,7 +10,6 @@ _start:
cvtps2pi %xmm7,%mm6
cvttpd2pi %xmm4,%mm3
cvttps2pi %xmm4,%mm3
- fisttp (%rax)
fisttps (%rax)
fisttpl (%rax)
fisttpll (%rax)
--- a/gas/testsuite/gas/i386/x86-64-sse2avx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx.s
@@ -720,9 +720,9 @@ _start:
# Tests for op regl/mem32, xmm[, xmm]
cvtsi2sd %ecx,%xmm4
- cvtsi2sd (%rcx),%xmm4
+ cvtsi2sdl (%rcx),%xmm4
cvtsi2ss %ecx,%xmm4
- cvtsi2ss (%rcx),%xmm4
+ cvtsi2ssl (%rcx),%xmm4
# Tests for op imm8, xmm/mem32, xmm[, xmm]
cmpss $100,%xmm4,%xmm6
--- a/gas/testsuite/gas/i386/x86-64-sse3.s
+++ b/gas/testsuite/gas/i386/x86-64-sse3.s
@@ -6,7 +6,7 @@ foo:
addsubpd %xmm2,%xmm1
addsubps (%rbx),%xmm2
addsubps %xmm4,%xmm3
- fisttp 0x909090(%rax)
+ fisttps 0x909090(%rax)
fisttpl 0x909090(%rax)
fisttpll 0x909090(%rax)
haddpd 0x0(%rbp),%xmm4
--- a/gas/testsuite/gas/i386/x86-64-suffix-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-suffix-intel.d
@@ -18,13 +18,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: cf iretd
[ ]*[a-f0-9]+: 48 cf iretq
[ ]*[a-f0-9]+: 0f 07 sysretd
-[ ]*[a-f0-9]+: 0f 07 sysretd
[ ]*[a-f0-9]+: 48 0f 07 sysretq
[ ]*[a-f0-9]+: 66 cf iretw
[ ]*[a-f0-9]+: cf iretd
[ ]*[a-f0-9]+: cf iretd
[ ]*[a-f0-9]+: 48 cf iretq
[ ]*[a-f0-9]+: 0f 07 sysretd
-[ ]*[a-f0-9]+: 0f 07 sysretd
[ ]*[a-f0-9]+: 48 0f 07 sysretq
#pass
--- a/gas/testsuite/gas/i386/x86-64-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-suffix.d
@@ -17,13 +17,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: cf iretl
[ ]*[a-f0-9]+: 48 cf iretq
[ ]*[a-f0-9]+: 0f 07 sysretl
-[ ]*[a-f0-9]+: 0f 07 sysretl
[ ]*[a-f0-9]+: 48 0f 07 sysretq
[ ]*[a-f0-9]+: 66 cf iretw
[ ]*[a-f0-9]+: cf iretl
[ ]*[a-f0-9]+: cf iretl
[ ]*[a-f0-9]+: 48 cf iretq
[ ]*[a-f0-9]+: 0f 07 sysretl
-[ ]*[a-f0-9]+: 0f 07 sysretl
[ ]*[a-f0-9]+: 48 0f 07 sysretq
#pass
--- a/gas/testsuite/gas/i386/x86-64-suffix.s
+++ b/gas/testsuite/gas/i386/x86-64-suffix.s
@@ -15,7 +15,6 @@ foo:
iret
iretq
sysretl
- sysret
sysretq
.intel_syntax noprefix
@@ -24,5 +23,4 @@ foo:
iret
iretq
sysretd
- sysret
sysretq
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2810,7 +2810,7 @@ pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Mo
// AMD extensions.
syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
+sysret, 0, 0xf07, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
` (7 preceding siblings ...)
2019-12-27 9:22 ` [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes Jan Beulich
@ 2019-12-27 9:24 ` Jan Beulich
2020-01-13 17:33 ` H.J. Lu
2019-12-27 9:27 ` [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich
9 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:24 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
Some encodings are about to gain a warning - move them from test cases
not expecting any diagnostics to the new, dedicated ones, to allow
better focus on the actual changes in the subsequent patch.
The new tests added have some wrong expectations right now, which will
be corrected by the next patch. The test is being added here to make
more visible which cases actually were wrong (and hence get changed),
besides demonstrating that in the vast majority of cases the subsequent
change doesn't alter generated code.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s,
testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size
tests ...
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: ... here.
* testsuite/gas/i386/x86_64.s: Likewise. Add further MOVSXD
cases.
* testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d
testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d,
testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d,
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d,
testsuite/gas/i386/x86_64.d: Adjust expectations.
* testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l,
testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l,
testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
---
v3: Re-base.
v2: Add new MOVSXD cases to x86_64.s testcase. Re-base over NOP addition
to testcases modified here.
--- a/gas/testsuite/gas/i386/i386-intel.d
+++ b/gas/testsuite/gas/i386/i386-intel.d
@@ -14,7 +14,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f be f0 movsx si,al
[ ]*[a-f0-9]+: 0f be f0 movsx esi,al
[ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax
-[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[eax\]
@@ -25,7 +24,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f b6 f0 movzx si,al
[ ]*[a-f0-9]+: 0f b6 f0 movzx esi,al
[ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax
-[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[eax\]
--- a/gas/testsuite/gas/i386/i386.d
+++ b/gas/testsuite/gas/i386/i386.d
@@ -13,7 +13,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
-[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
@@ -24,7 +23,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
-[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -132,6 +132,8 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_list_test "noreg16"
run_dump_test "noreg32"
run_list_test "noreg32"
+ run_list_test "movx16" "-I${srcdir}/$subdir -al"
+ run_list_test "movx32" "-al"
run_dump_test "addr16"
run_dump_test "addr32"
run_dump_test "code16"
@@ -732,6 +734,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_list_test "x86-64-sysenter-amd"
run_dump_test "noreg64"
run_list_test "noreg64"
+ run_list_test "movx64" "-al"
run_list_test "cvtsi2sX"
run_dump_test "x86-64-sse4_1"
run_dump_test "x86-64-sse4_1-intel"
--- a/gas/testsuite/gas/i386/i386.s
+++ b/gas/testsuite/gas/i386/i386.s
@@ -9,7 +9,6 @@
movsx %al, %si
movsx %al, %esi
movsx %ax, %esi
- movsx (%eax), %edx
movsx (%eax), %dx
movsxb (%eax), %dx
movsxb (%eax), %edx
@@ -21,7 +20,6 @@
movzx %al, %si
movzx %al, %esi
movzx %ax, %esi
- movzx (%eax), %edx
movzx (%eax), %dx
movzxb (%eax), %dx
movzxb (%eax), %edx
--- a/gas/testsuite/gas/i386/iamcu-1.d
+++ b/gas/testsuite/gas/i386/iamcu-1.d
@@ -10,7 +10,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
-[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
@@ -21,7 +20,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
-[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
--- a/gas/testsuite/gas/i386/iamcu-1.s
+++ b/gas/testsuite/gas/i386/iamcu-1.s
@@ -4,7 +4,6 @@
movsx %al, %si
movsx %al, %esi
movsx %ax, %esi
- movsx (%eax), %edx
movsx (%eax), %dx
movsxb (%eax), %dx
movsxb (%eax), %edx
@@ -16,7 +15,6 @@
movzx %al, %si
movzx %al, %esi
movzx %ax, %esi
- movzx (%eax), %edx
movzx (%eax), %dx
movzxb (%eax), %dx
movzxb (%eax), %edx
--- a/gas/testsuite/gas/i386/ilp32/x86-64.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64.d
@@ -162,8 +162,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
-[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -175,8 +173,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
-[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
@@ -220,8 +216,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -230,8 +224,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
--- a/gas/testsuite/gas/i386/ilp32/x86-64.s
+++ b/gas/testsuite/gas/i386/ilp32/x86-64.s
@@ -194,8 +194,6 @@ cmpxchg16b oword ptr [rax]
movsx %ax, %esi
movsx %ax, %rsi
movsx %eax, %rsi
- movsx (%rax), %edx
- movsx (%rax), %rdx
movsx (%rax), %dx
movsbl (%rax), %edx
movsbq (%rax), %rdx
@@ -208,8 +206,6 @@ cmpxchg16b oword ptr [rax]
movzx %al, %rsi
movzx %ax, %esi
movzx %ax, %rsi
- movzx (%rax), %edx
- movzx (%rax), %rdx
movzx (%rax), %dx
movzb (%rax), %edx
movzb (%rax), %rdx
@@ -263,8 +259,6 @@ cmpxchg16b oword ptr [rax]
.att_syntax
movsx (%rax),%ax
-movsx (%rax),%eax
-movsx (%rax),%rax
movsxb (%rax), %dx
movsxb (%rax), %edx
movsxb (%rax), %rdx
@@ -273,8 +267,6 @@ movsxw (%rax), %rdx
movsxl (%rax), %rdx
movsxd (%rax),%rax
movzx (%rax),%ax
-movzx (%rax),%eax
-movzx (%rax),%rax
movzxb (%rax), %dx
movzxb (%rax), %edx
movzxb (%rax), %rdx
--- a/gas/testsuite/gas/i386/k1om.d
+++ b/gas/testsuite/gas/i386/k1om.d
@@ -166,8 +166,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
-[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -179,8 +177,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
-[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
@@ -224,8 +220,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -233,9 +227,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
+[ ]*[a-f0-9]+: 48 63 08 movslq \(%rax\),%rcx
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
@@ -251,6 +244,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 00 movswq \(%rax\),%rax
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
+[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%rax\),%eax
--- a/gas/testsuite/gas/i386/l1om.d
+++ b/gas/testsuite/gas/i386/l1om.d
@@ -166,8 +166,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
-[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -179,8 +177,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
-[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
@@ -224,8 +220,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -233,9 +227,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
+[ ]*[a-f0-9]+: 48 63 08 movslq \(%rax\),%rcx
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
@@ -251,6 +244,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 00 movswq \(%rax\),%rax
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
+[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%rax\),%eax
--- /dev/null
+++ b/gas/testsuite/gas/i386/movx16.l
@@ -0,0 +1,195 @@
+.*: Assembler messages:
+#...
+[ ]*[1-9][0-9]*[ ]+movsx:
+[ ]*[1-9][0-9]*[ ]+movsx %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsx %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsx %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movsxw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsbw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsbl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movswl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movswl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FBFC8[ ]+movswl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzx:
+[ ]*[1-9][0-9]*[ ]+movzx %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzx %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzx %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzxw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzbw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzbl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 660FB7C8[ ]+movzwl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %ecx
--- /dev/null
+++ b/gas/testsuite/gas/i386/movx16.s
@@ -0,0 +1,2 @@
+ .code16
+ .include "movx32.s"
--- /dev/null
+++ b/gas/testsuite/gas/i386/movx32.l
@@ -0,0 +1,195 @@
+.*: Assembler messages:
+#...
+[ ]*[1-9][0-9]*[ ]+movsx:
+[ ]*[1-9][0-9]*[ ]+movsx %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsx %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsxw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsbw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsbl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movswl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movswl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movswl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzx:
+[ ]*[1-9][0-9]*[ ]+movzx %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzx %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzx %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzxw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzbw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzbl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %ecx
--- /dev/null
+++ b/gas/testsuite/gas/i386/movx32.s
@@ -0,0 +1,195 @@
+ .text
+ .psize 0
+movsx:
+ movsx %al, %cl
+ movsx %ax, %cl
+ movsx %eax, %cl
+
+ movsx %al, %cx
+ movsx %ax, %cx
+ movsx %eax, %cx
+
+ movsx %al, %ecx
+ movsx %ax, %ecx
+ movsx %eax, %ecx
+
+ movsxb %al, %cl
+ movsxb %ax, %cl
+ movsxb %eax, %cl
+
+ movsxb %al, %cx
+ movsxb %ax, %cx
+ movsxb %eax, %cx
+
+ movsxb %al, %ecx
+ movsxb %ax, %ecx
+ movsxb %eax, %ecx
+
+ movsxw %al, %cl
+ movsxw %ax, %cl
+ movsxw %eax, %cl
+
+ movsxw %al, %cx
+ movsxw %ax, %cx
+ movsxw %eax, %cx
+
+ movsxw %al, %ecx
+ movsxw %ax, %ecx
+ movsxw %eax, %ecx
+
+ movsb %al, %cl
+ movsb %ax, %cl
+ movsb %eax, %cl
+
+ movsb %al, %cx
+ movsb %ax, %cx
+ movsb %eax, %cx
+
+ movsb %al, %ecx
+ movsb %ax, %ecx
+ movsb %eax, %ecx
+
+ movsbw %al, %cl
+ movsbw %ax, %cl
+ movsbw %eax, %cl
+
+ movsbw %al, %cx
+ movsbw %ax, %cx
+ movsbw %eax, %cx
+
+ movsbw %al, %ecx
+ movsbw %ax, %ecx
+ movsbw %eax, %ecx
+
+ movsbl %al, %cl
+ movsbl %ax, %cl
+ movsbl %eax, %cl
+
+ movsbl %al, %cx
+ movsbl %ax, %cx
+ movsbl %eax, %cx
+
+ movsbl %al, %ecx
+ movsbl %ax, %ecx
+ movsbl %eax, %ecx
+
+ movsw %al, %cl
+ movsw %ax, %cl
+ movsw %eax, %cl
+
+ movsw %al, %cx
+ movsw %ax, %cx
+ movsw %eax, %cx
+
+ movsw %al, %ecx
+ movsw %ax, %ecx
+ movsw %eax, %ecx
+
+ movswl %al, %cl
+ movswl %ax, %cl
+ movswl %eax, %cl
+
+ movswl %al, %cx
+ movswl %ax, %cx
+ movswl %eax, %cx
+
+ movswl %al, %ecx
+ movswl %ax, %ecx
+ movswl %eax, %ecx
+
+movzx:
+ movzx %al, %cl
+ movzx %ax, %cl
+ movzx %eax, %cl
+
+ movzx %al, %cx
+ movzx %ax, %cx
+ movzx %eax, %cx
+
+ movzx %al, %ecx
+ movzx %ax, %ecx
+ movzx %eax, %ecx
+
+ movzxb %al, %cl
+ movzxb %ax, %cl
+ movzxb %eax, %cl
+
+ movzxb %al, %cx
+ movzxb %ax, %cx
+ movzxb %eax, %cx
+
+ movzxb %al, %ecx
+ movzxb %ax, %ecx
+ movzxb %eax, %ecx
+
+ movzxw %al, %cl
+ movzxw %ax, %cl
+ movzxw %eax, %cl
+
+ movzxw %al, %cx
+ movzxw %ax, %cx
+ movzxw %eax, %cx
+
+ movzxw %al, %ecx
+ movzxw %ax, %ecx
+ movzxw %eax, %ecx
+
+ movzb %al, %cl
+ movzb %ax, %cl
+ movzb %eax, %cl
+
+ movzb %al, %cx
+ movzb %ax, %cx
+ movzb %eax, %cx
+
+ movzb %al, %ecx
+ movzb %ax, %ecx
+ movzb %eax, %ecx
+
+ movzbw %al, %cl
+ movzbw %ax, %cl
+ movzbw %eax, %cl
+
+ movzbw %al, %cx
+ movzbw %ax, %cx
+ movzbw %eax, %cx
+
+ movzbw %al, %ecx
+ movzbw %ax, %ecx
+ movzbw %eax, %ecx
+
+ movzbl %al, %cl
+ movzbl %ax, %cl
+ movzbl %eax, %cl
+
+ movzbl %al, %cx
+ movzbl %ax, %cx
+ movzbl %eax, %cx
+
+ movzbl %al, %ecx
+ movzbl %ax, %ecx
+ movzbl %eax, %ecx
+
+ movzw %al, %cl
+ movzw %ax, %cl
+ movzw %eax, %cl
+
+ movzw %al, %cx
+ movzw %ax, %cx
+ movzw %eax, %cx
+
+ movzw %al, %ecx
+ movzw %ax, %ecx
+ movzw %eax, %ecx
+
+ movzwl %al, %cl
+ movzwl %ax, %cl
+ movzwl %eax, %cl
+
+ movzwl %al, %cx
+ movzwl %ax, %cx
+ movzwl %eax, %cx
+
+ movzwl %al, %ecx
+ movzwl %ax, %ecx
+ movzwl %eax, %ecx
--- /dev/null
+++ b/gas/testsuite/gas/i386/movx64.l
@@ -0,0 +1,483 @@
+.*: Assembler messages:
+#...
+[ ]*[1-9][0-9]*[ ]+movsx:
+[ ]*[1-9][0-9]*[ ]+movsx %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsx %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsx %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsx %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsx %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsx %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsx %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsx %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsx %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsx %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsx %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FBFC8[ ]+movsx %ax, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movsx %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsx %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxb %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsxb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxb %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsxb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxb %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsxb %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxb %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxb %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxb %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxw %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxw %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movsxw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxw %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxw %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FBFC8[ ]+movsxw %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxw %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxw %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxl %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxl %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxl %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxl %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxl %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxl %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxl %ax, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movsxl %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxl %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxd %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsxd %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxd %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsxd %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxd %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsxd %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxd %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsxd %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxd %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxd %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxd %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsxd %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsxd %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxd %ax, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 4863C8[ ]+movsxd %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsxd %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsb %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsb %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsb %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsb %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsb %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsb %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsb %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbw %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FBEC8[ ]+movsbw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbw %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbw %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbw %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbw %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbw %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbw %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbl %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbl %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FBEC8[ ]+movsbl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbl %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbl %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbl %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbl %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbl %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbq %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsbq %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbq %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsbq %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbq %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsbq %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbq %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsbq %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsbq %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbq %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbq %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsbq %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FBEC8[ ]+movsbq %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbq %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbq %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsbq %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movsw %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movsw %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movsw %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movsw %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movsw %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsw %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movsw %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movswl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movswl %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movswl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movswl %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FBFC8[ ]+movswl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movswl %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswl %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movswl %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movswl %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movswl %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswq %al, %cl
+[ ]*[1-9][0-9]*[ ]+movswq %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movswq %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movswq %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswq %al, %cx
+[ ]*[1-9][0-9]*[ ]+movswq %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movswq %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movswq %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswq %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movswq %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movswq %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movswq %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movswq %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FBFC8[ ]+movswq %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movswq %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movswq %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzx:
+[ ]*[1-9][0-9]*[ ]+movzx %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzx %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzx %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzx %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzx %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzx %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzx %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzx %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzx %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzx %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzx %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzx %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzx %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxb %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzxb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxb %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzxb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxb %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzxb %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxb %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxb %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxb %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxw %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxw %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzxw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxw %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxw %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzxw %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxw %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxw %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxl %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxl %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxl %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxl %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxl %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxl %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxl %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxl %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxl %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxd %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzxd %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxd %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzxd %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxd %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzxd %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxd %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzxd %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxd %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxd %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxd %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzxd %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzxd %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxd %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxd %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzxd %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzb %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzb %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzb %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzb %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzb %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzb %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzb %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzb %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzb %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzb %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzbw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbw %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbw %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbw %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbw %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbw %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbw %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbw %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbw %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzbl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbl %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbl %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbl %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbl %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbl %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbl %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbl %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbl %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzbq %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzbq %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbq %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzbq %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 660FB6C8[ ]+movzbq %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzbq %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbq %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzbq %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 0FB6C8[ ]+movzbq %al, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbq %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbq %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzbq %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]* \?\?\?\? 480FB6C8[ ]+movzbq %al, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbq %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbq %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzbq %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzw %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzw %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzw %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzw %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzw %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzw %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzw %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzw %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzw %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzw %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzwl %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzwl %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzwl %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwl %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzwl %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwl %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzwl %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzwl %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzwl %rax, %rcx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwq %al, %cl
+[ ]*[1-9][0-9]*[ ]+movzwq %ax, %cl
+[ ]*[1-9][0-9]*[ ]+movzwq %eax, %cl
+[ ]*[1-9][0-9]*[ ]+movzwq %rax, %cl
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwq %al, %cx
+[ ]*[1-9][0-9]*[ ]+movzwq %ax, %cx
+[ ]*[1-9][0-9]*[ ]+movzwq %eax, %cx
+[ ]*[1-9][0-9]*[ ]+movzwq %rax, %cx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwq %al, %ecx
+[ ]*[1-9][0-9]* \?\?\?\? 0FB7C8[ ]+movzwq %ax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzwq %eax, %ecx
+[ ]*[1-9][0-9]*[ ]+movzwq %rax, %ecx
+[ ]*[1-9][0-9]*[ ]*
+[ ]*[1-9][0-9]*[ ]+movzwq %al, %rcx
+[ ]*[1-9][0-9]* \?\?\?\? 480FB7C8[ ]+movzwq %ax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzwq %eax, %rcx
+[ ]*[1-9][0-9]*[ ]+movzwq %rax, %rcx
--- /dev/null
+++ b/gas/testsuite/gas/i386/movx64.s
@@ -0,0 +1,483 @@
+ .text
+ .psize 0
+movsx:
+ movsx %al, %cl
+ movsx %ax, %cl
+ movsx %eax, %cl
+ movsx %rax, %cl
+
+ movsx %al, %cx
+ movsx %ax, %cx
+ movsx %eax, %cx
+ movsx %rax, %cx
+
+ movsx %al, %ecx
+ movsx %ax, %ecx
+ movsx %eax, %ecx
+ movsx %rax, %ecx
+
+ movsx %al, %rcx
+ movsx %ax, %rcx
+ movsx %eax, %rcx
+ movsx %rax, %rcx
+
+ movsxb %al, %cl
+ movsxb %ax, %cl
+ movsxb %eax, %cl
+ movsxb %rax, %cl
+
+ movsxb %al, %cx
+ movsxb %ax, %cx
+ movsxb %eax, %cx
+ movsxb %rax, %cx
+
+ movsxb %al, %ecx
+ movsxb %ax, %ecx
+ movsxb %eax, %ecx
+ movsxb %rax, %ecx
+
+ movsxb %al, %rcx
+ movsxb %ax, %rcx
+ movsxb %eax, %rcx
+ movsxb %rax, %rcx
+
+ movsxw %al, %cl
+ movsxw %ax, %cl
+ movsxw %eax, %cl
+ movsxw %rax, %cl
+
+ movsxw %al, %cx
+ movsxw %ax, %cx
+ movsxw %eax, %cx
+ movsxw %rax, %cx
+
+ movsxw %al, %ecx
+ movsxw %ax, %ecx
+ movsxw %eax, %ecx
+ movsxw %rax, %ecx
+
+ movsxw %al, %rcx
+ movsxw %ax, %rcx
+ movsxw %eax, %rcx
+ movsxw %rax, %rcx
+
+ movsxl %al, %cl
+ movsxl %ax, %cl
+ movsxl %eax, %cl
+ movsxl %rax, %cl
+
+ movsxl %al, %cx
+ movsxl %ax, %cx
+ movsxl %eax, %cx
+ movsxl %rax, %cx
+
+ movsxl %al, %ecx
+ movsxl %ax, %ecx
+ movsxl %eax, %ecx
+ movsxl %rax, %ecx
+
+ movsxl %al, %rcx
+ movsxl %ax, %rcx
+ movsxl %eax, %rcx
+ movsxl %rax, %rcx
+
+ movsxd %al, %cl
+ movsxd %ax, %cl
+ movsxd %eax, %cl
+ movsxd %rax, %cl
+
+ movsxd %al, %cx
+ movsxd %ax, %cx
+ movsxd %eax, %cx
+ movsxd %rax, %cx
+
+ movsxd %al, %ecx
+ movsxd %ax, %ecx
+ movsxd %eax, %ecx
+ movsxd %rax, %ecx
+
+ movsxd %al, %rcx
+ movsxd %ax, %rcx
+ movsxd %eax, %rcx
+ movsxd %rax, %rcx
+
+ movsb %al, %cl
+ movsb %ax, %cl
+ movsb %eax, %cl
+ movsb %rax, %cl
+
+ movsb %al, %cx
+ movsb %ax, %cx
+ movsb %eax, %cx
+ movsb %rax, %cx
+
+ movsb %al, %ecx
+ movsb %ax, %ecx
+ movsb %eax, %ecx
+ movsb %rax, %ecx
+
+ movsb %al, %rcx
+ movsb %ax, %rcx
+ movsb %eax, %rcx
+ movsb %rax, %rcx
+
+ movsbw %al, %cl
+ movsbw %ax, %cl
+ movsbw %eax, %cl
+ movsbw %rax, %cl
+
+ movsbw %al, %cx
+ movsbw %ax, %cx
+ movsbw %eax, %cx
+ movsbw %rax, %cx
+
+ movsbw %al, %ecx
+ movsbw %ax, %ecx
+ movsbw %eax, %ecx
+ movsbw %rax, %ecx
+
+ movsbw %al, %rcx
+ movsbw %ax, %rcx
+ movsbw %eax, %rcx
+ movsbw %rax, %rcx
+
+ movsbl %al, %cl
+ movsbl %ax, %cl
+ movsbl %eax, %cl
+ movsbl %rax, %cl
+
+ movsbl %al, %cx
+ movsbl %ax, %cx
+ movsbl %eax, %cx
+ movsbl %rax, %cx
+
+ movsbl %al, %ecx
+ movsbl %ax, %ecx
+ movsbl %eax, %ecx
+ movsbl %rax, %ecx
+
+ movsbl %al, %rcx
+ movsbl %ax, %rcx
+ movsbl %eax, %rcx
+ movsbl %rax, %rcx
+
+ movsbq %al, %cl
+ movsbq %ax, %cl
+ movsbq %eax, %cl
+ movsbq %rax, %cl
+
+ movsbq %al, %cx
+ movsbq %ax, %cx
+ movsbq %eax, %cx
+ movsbq %rax, %cx
+
+ movsbq %al, %ecx
+ movsbq %ax, %ecx
+ movsbq %eax, %ecx
+ movsbq %rax, %ecx
+
+ movsbq %al, %rcx
+ movsbq %ax, %rcx
+ movsbq %eax, %rcx
+ movsbq %rax, %rcx
+
+ movsw %al, %cl
+ movsw %ax, %cl
+ movsw %eax, %cl
+ movsw %rax, %cl
+
+ movsw %al, %cx
+ movsw %ax, %cx
+ movsw %eax, %cx
+ movsw %rax, %cx
+
+ movsw %al, %ecx
+ movsw %ax, %ecx
+ movsw %eax, %ecx
+ movsw %rax, %ecx
+
+ movsw %al, %rcx
+ movsw %ax, %rcx
+ movsw %eax, %rcx
+ movsw %rax, %rcx
+
+ movswl %al, %cl
+ movswl %ax, %cl
+ movswl %eax, %cl
+ movswl %rax, %cl
+
+ movswl %al, %cx
+ movswl %ax, %cx
+ movswl %eax, %cx
+ movswl %rax, %cx
+
+ movswl %al, %ecx
+ movswl %ax, %ecx
+ movswl %eax, %ecx
+ movswl %rax, %ecx
+
+ movswl %al, %rcx
+ movswl %ax, %rcx
+ movswl %eax, %rcx
+ movswl %rax, %rcx
+
+ movswq %al, %cl
+ movswq %ax, %cl
+ movswq %eax, %cl
+ movswq %rax, %cl
+
+ movswq %al, %cx
+ movswq %ax, %cx
+ movswq %eax, %cx
+ movswq %rax, %cx
+
+ movswq %al, %ecx
+ movswq %ax, %ecx
+ movswq %eax, %ecx
+ movswq %rax, %ecx
+
+ movswq %al, %rcx
+ movswq %ax, %rcx
+ movswq %eax, %rcx
+ movswq %rax, %rcx
+
+movzx:
+ movzx %al, %cl
+ movzx %ax, %cl
+ movzx %eax, %cl
+ movzx %rax, %cl
+
+ movzx %al, %cx
+ movzx %ax, %cx
+ movzx %eax, %cx
+ movzx %rax, %cx
+
+ movzx %al, %ecx
+ movzx %ax, %ecx
+ movzx %eax, %ecx
+ movzx %rax, %ecx
+
+ movzx %al, %rcx
+ movzx %ax, %rcx
+ movzx %eax, %rcx
+ movzx %rax, %rcx
+
+ movzxb %al, %cl
+ movzxb %ax, %cl
+ movzxb %eax, %cl
+ movzxb %rax, %cl
+
+ movzxb %al, %cx
+ movzxb %ax, %cx
+ movzxb %eax, %cx
+ movzxb %rax, %cx
+
+ movzxb %al, %ecx
+ movzxb %ax, %ecx
+ movzxb %eax, %ecx
+ movzxb %rax, %ecx
+
+ movzxb %al, %rcx
+ movzxb %ax, %rcx
+ movzxb %eax, %rcx
+ movzxb %rax, %rcx
+
+ movzxw %al, %cl
+ movzxw %ax, %cl
+ movzxw %eax, %cl
+ movzxw %rax, %cl
+
+ movzxw %al, %cx
+ movzxw %ax, %cx
+ movzxw %eax, %cx
+ movzxw %rax, %cx
+
+ movzxw %al, %ecx
+ movzxw %ax, %ecx
+ movzxw %eax, %ecx
+ movzxw %rax, %ecx
+
+ movzxw %al, %rcx
+ movzxw %ax, %rcx
+ movzxw %eax, %rcx
+ movzxw %rax, %rcx
+
+ movzxl %al, %cl
+ movzxl %ax, %cl
+ movzxl %eax, %cl
+ movzxl %rax, %cl
+
+ movzxl %al, %cx
+ movzxl %ax, %cx
+ movzxl %eax, %cx
+ movzxl %rax, %cx
+
+ movzxl %al, %ecx
+ movzxl %ax, %ecx
+ movzxl %eax, %ecx
+ movzxl %rax, %ecx
+
+ movzxl %al, %rcx
+ movzxl %ax, %rcx
+ movzxl %eax, %rcx
+ movzxl %rax, %rcx
+
+ movzxd %al, %cl
+ movzxd %ax, %cl
+ movzxd %eax, %cl
+ movzxd %rax, %cl
+
+ movzxd %al, %cx
+ movzxd %ax, %cx
+ movzxd %eax, %cx
+ movzxd %rax, %cx
+
+ movzxd %al, %ecx
+ movzxd %ax, %ecx
+ movzxd %eax, %ecx
+ movzxd %rax, %ecx
+
+ movzxd %al, %rcx
+ movzxd %ax, %rcx
+ movzxd %eax, %rcx
+ movzxd %rax, %rcx
+
+ movzb %al, %cl
+ movzb %ax, %cl
+ movzb %eax, %cl
+ movzb %rax, %cl
+
+ movzb %al, %cx
+ movzb %ax, %cx
+ movzb %eax, %cx
+ movzb %rax, %cx
+
+ movzb %al, %ecx
+ movzb %ax, %ecx
+ movzb %eax, %ecx
+ movzb %rax, %ecx
+
+ movzb %al, %rcx
+ movzb %ax, %rcx
+ movzb %eax, %rcx
+ movzb %rax, %rcx
+
+ movzbw %al, %cl
+ movzbw %ax, %cl
+ movzbw %eax, %cl
+ movzbw %rax, %cl
+
+ movzbw %al, %cx
+ movzbw %ax, %cx
+ movzbw %eax, %cx
+ movzbw %rax, %cx
+
+ movzbw %al, %ecx
+ movzbw %ax, %ecx
+ movzbw %eax, %ecx
+ movzbw %rax, %ecx
+
+ movzbw %al, %rcx
+ movzbw %ax, %rcx
+ movzbw %eax, %rcx
+ movzbw %rax, %rcx
+
+ movzbl %al, %cl
+ movzbl %ax, %cl
+ movzbl %eax, %cl
+ movzbl %rax, %cl
+
+ movzbl %al, %cx
+ movzbl %ax, %cx
+ movzbl %eax, %cx
+ movzbl %rax, %cx
+
+ movzbl %al, %ecx
+ movzbl %ax, %ecx
+ movzbl %eax, %ecx
+ movzbl %rax, %ecx
+
+ movzbl %al, %rcx
+ movzbl %ax, %rcx
+ movzbl %eax, %rcx
+ movzbl %rax, %rcx
+
+ movzbq %al, %cl
+ movzbq %ax, %cl
+ movzbq %eax, %cl
+ movzbq %rax, %cl
+
+ movzbq %al, %cx
+ movzbq %ax, %cx
+ movzbq %eax, %cx
+ movzbq %rax, %cx
+
+ movzbq %al, %ecx
+ movzbq %ax, %ecx
+ movzbq %eax, %ecx
+ movzbq %rax, %ecx
+
+ movzbq %al, %rcx
+ movzbq %ax, %rcx
+ movzbq %eax, %rcx
+ movzbq %rax, %rcx
+
+ movzw %al, %cl
+ movzw %ax, %cl
+ movzw %eax, %cl
+ movzw %rax, %cl
+
+ movzw %al, %cx
+ movzw %ax, %cx
+ movzw %eax, %cx
+ movzw %rax, %cx
+
+ movzw %al, %ecx
+ movzw %ax, %ecx
+ movzw %eax, %ecx
+ movzw %rax, %ecx
+
+ movzw %al, %rcx
+ movzw %ax, %rcx
+ movzw %eax, %rcx
+ movzw %rax, %rcx
+
+ movzwl %al, %cl
+ movzwl %ax, %cl
+ movzwl %eax, %cl
+ movzwl %rax, %cl
+
+ movzwl %al, %cx
+ movzwl %ax, %cx
+ movzwl %eax, %cx
+ movzwl %rax, %cx
+
+ movzwl %al, %ecx
+ movzwl %ax, %ecx
+ movzwl %eax, %ecx
+ movzwl %rax, %ecx
+
+ movzwl %al, %rcx
+ movzwl %ax, %rcx
+ movzwl %eax, %rcx
+ movzwl %rax, %rcx
+
+ movzwq %al, %cl
+ movzwq %ax, %cl
+ movzwq %eax, %cl
+ movzwq %rax, %cl
+
+ movzwq %al, %cx
+ movzwq %ax, %cx
+ movzwq %eax, %cx
+ movzwq %rax, %cx
+
+ movzwq %al, %ecx
+ movzwq %ax, %ecx
+ movzwq %eax, %ecx
+ movzwq %rax, %ecx
+
+ movzwq %al, %rcx
+ movzwq %ax, %rcx
+ movzwq %eax, %rcx
+ movzwq %rax, %rcx
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -75,6 +75,10 @@ Disassembly of section .text:
*[a-f0-9]+: 8e 07 mov \(%bx\),%es
*[a-f0-9]+: a5 movsw %ds:\(%si\),%es:\(%di\)
*[a-f0-9]+: 67 a5 movsw %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+: 0f be 07 movsbw \(%bx\),%ax
+ *[a-f0-9]+: 66 0f be 07 movsbl \(%bx\),%eax
+ *[a-f0-9]+: 0f b6 07 movzbw \(%bx\),%ax
+ *[a-f0-9]+: 66 0f b6 07 movzbl \(%bx\),%eax
*[a-f0-9]+: f7 27 mulw \(%bx\)
*[a-f0-9]+: f7 1f negw \(%bx\)
*[a-f0-9]+: 0f 1f 07 nopw \(%bx\)
--- a/gas/testsuite/gas/i386/noreg16.s
+++ b/gas/testsuite/gas/i386/noreg16.s
@@ -69,6 +69,10 @@ noreg:
mov (%bx), %es
movs
movs (%esi), %es:(%edi)
+ movsx (%bx), %ax
+ movsx (%bx), %eax
+ movzx (%bx), %ax
+ movzx (%bx), %eax
mul (%bx)
neg (%bx)
nop (%bx)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -80,6 +80,10 @@ Disassembly of section .text:
*[a-f0-9]+: 8e 00 mov \(%eax\),%es
*[a-f0-9]+: a5 movsl %ds:\(%esi\),%es:\(%edi\)
*[a-f0-9]+: a5 movsl %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+: 66 0f be 00 movsbw \(%eax\),%ax
+ *[a-f0-9]+: 0f be 00 movsbl \(%eax\),%eax
+ *[a-f0-9]+: 66 0f b6 00 movzbw \(%eax\),%ax
+ *[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax
*[a-f0-9]+: f7 20 mull \(%eax\)
*[a-f0-9]+: f7 18 negl \(%eax\)
*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
--- a/gas/testsuite/gas/i386/noreg32.s
+++ b/gas/testsuite/gas/i386/noreg32.s
@@ -73,6 +73,10 @@ noreg:
mov (%eax), %es
movs
movs (%esi), %es:(%edi)
+ movsx (%eax), %ax
+ movsx (%eax), %eax
+ movzx (%eax), %ax
+ movzx (%eax), %eax
mul (%eax)
neg (%eax)
nop (%eax)
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -81,6 +81,12 @@ Disassembly of section .text:
*[a-f0-9]+: 8e 00 mov \(%rax\),%es
*[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\)
*[a-f0-9]+: a5 movsl %ds:\(%rsi\),%es:\(%rdi\)
+ *[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
+ *[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
+ *[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
+ *[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
+ *[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
+ *[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
*[a-f0-9]+: f7 20 mull \(%rax\)
*[a-f0-9]+: f7 18 negl \(%rax\)
*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -74,6 +74,12 @@ noreg:
mov (%rax), %es
movs
movs (%rsi), %es:(%rdi)
+ movsx (%rax), %ax
+ movsx (%rax), %eax
+ movsx (%rax), %rax
+ movzx (%rax), %ax
+ movzx (%rax), %eax
+ movzx (%rax), %rax
mul (%rax)
neg (%rax)
nop (%rax)
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -164,8 +164,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f bf f0 movsx esi,ax
[ ]*[a-f0-9]+: 48 0f bf f0 movsx rsi,ax
[ ]*[a-f0-9]+: 48 63 f0 movsxd rsi,eax
-[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\]
-[ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\]
@@ -177,8 +175,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b6 f0 movzx rsi,al
[ ]*[a-f0-9]+: 0f b7 f0 movzx esi,ax
[ ]*[a-f0-9]+: 48 0f b7 f0 movzx rsi,ax
-[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\]
-[ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\]
@@ -222,8 +218,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 9b df e0 fstsw ax
[ ]*[a-f0-9]+: 9b df e0 fstsw ax
[ ]*[a-f0-9]+: 66 0f be 00 movsx ax,BYTE PTR \[rax\]
-[ ]*[a-f0-9]+: 0f be 00 movsx eax,BYTE PTR \[rax\]
-[ ]*[a-f0-9]+: 48 0f be 00 movsx rax,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 66 0f be 10 movsx dx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 0f be 10 movsx edx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 48 0f be 10 movsx rdx,BYTE PTR \[rax\]
@@ -231,9 +225,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 10 movsx rdx,WORD PTR \[rax\]
[ ]*[a-f0-9]+: 48 63 10 movsxd rdx,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: 48 63 00 movsxd rax,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 48 63 08 movsxd rcx,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: 66 0f b6 00 movzx ax,BYTE PTR \[rax\]
-[ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[rax\]
-[ ]*[a-f0-9]+: 48 0f b6 00 movzx rax,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 66 0f b6 10 movzx dx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 0f b6 10 movzx edx,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 48 0f b6 10 movzx rdx,BYTE PTR \[rax\]
@@ -249,6 +242,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 00 movsx rax,WORD PTR \[rax\]
[ ]*[a-f0-9]+: 48 63 00 movsxd rax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: 48 63 00 movsxd rax,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 48 63 00 movsxd rax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: 66 0f b6 00 movzx ax,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[rax\]
[ ]*[a-f0-9]+: 0f b7 00 movzx eax,WORD PTR \[rax\]
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -163,8 +163,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
-[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -176,8 +174,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
-[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
-[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
@@ -221,8 +217,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
@@ -230,9 +224,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
+[ ]*[a-f0-9]+: 48 63 08 movslq \(%rax\),%rcx
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
-[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
-[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
@@ -248,6 +241,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f bf 00 movswq \(%rax\),%rax
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
+[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%rax\),%eax
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -200,8 +200,6 @@ cmpxchg16b oword ptr [rax]
movsx %ax, %esi
movsx %ax, %rsi
movsx %eax, %rsi
- movsx (%rax), %edx
- movsx (%rax), %rdx
movsx (%rax), %dx
movsbl (%rax), %edx
movsbq (%rax), %rdx
@@ -214,8 +212,6 @@ cmpxchg16b oword ptr [rax]
movzx %al, %rsi
movzx %ax, %esi
movzx %ax, %rsi
- movzx (%rax), %edx
- movzx (%rax), %rdx
movzx (%rax), %dx
movzb (%rax), %edx
movzb (%rax), %rdx
@@ -269,18 +265,15 @@ cmpxchg16b oword ptr [rax]
.att_syntax
movsx (%rax),%ax
-movsx (%rax),%eax
-movsx (%rax),%rax
movsxb (%rax), %dx
movsxb (%rax), %edx
movsxb (%rax), %rdx
movsxw (%rax), %edx
movsxw (%rax), %rdx
movsxl (%rax), %rdx
-movsxd (%rax),%rax
+movsxd (%rax),%rax
+movsxdl (%rax),%rcx
movzx (%rax),%ax
-movzx (%rax),%eax
-movzx (%rax),%rax
movzxb (%rax), %dx
movzxb (%rax), %edx
movzxb (%rax), %rdx
@@ -300,6 +293,7 @@ movsx eax, WORD PTR [rax]
movsx rax, WORD PTR [rax]
movsx rax, DWORD PTR [rax]
movsxd rax, [rax]
+movsxd rax, DWORD PTR [rax]
movzx ax, BYTE PTR [rax]
movzx eax, BYTE PTR [rax]
movzx eax, WORD PTR [rax]
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
` (8 preceding siblings ...)
2019-12-27 9:24 ` [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests Jan Beulich
@ 2019-12-27 9:27 ` Jan Beulich
2020-01-13 17:43 ` H.J. Lu
9 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2019-12-27 9:27 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
AMD and Intel differ in their handling of far indirect branches as well
as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
how the latter three were hybrids so far, while far branches were fully
AMD-like.)
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
PR gas/24546
* config/tc-i386.c (match_template): Apply AMD64/Intel64 check
to 64-bit code only.
* config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
O_tbyte_ptr case.
* testsuite/gas/i386/x86-64-branch-3.s,
testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
* testsuite/gas/i386/x86-64-branch-3.d,
testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
* testsuite/gas/i386/x86-64-branch-5.l,
testsuite/gas/i386/x86-64-branch-5.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
PR gas/24546
* i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
* i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
AMD64 and Intel64 templates.
(call, jmp): Likewise for far indirect variants. Dro
Unspecified.
* i386-tbl.h: Re-generate.
---
v3: New.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -694,9 +694,11 @@ i386_intel_operand (char *operand_string
if (got_a_float == 1)
suffix = LONG_DOUBLE_MNEM_SUFFIX;
else if ((current_templates->start->operand_types[0].bitfield.fword
- || current_templates->start->operand_types[0].bitfield.tbyte)
+ || current_templates->start->operand_types[0].bitfield.tbyte
+ || current_templates->start->opcode_modifier.jump == JUMP_DWORD
+ || current_templates->start->opcode_modifier.jump == JUMP)
&& flag_code == CODE_64BIT)
- suffix = QWORD_MNEM_SUFFIX; /* l[fgs]s, [ls][gi]dt */
+ suffix = QWORD_MNEM_SUFFIX; /* l[fgs]s, [ls][gi]dt, call, jmp */
else
i.types[this_operand].bitfield.byte = 1; /* cause an error */
break;
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5796,10 +5796,11 @@ match_template (char mnem_suffix)
/* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
i.error = unsupported_syntax;
- if ((intel_syntax && t->opcode_modifier.attsyntax)
- || (!intel_syntax && t->opcode_modifier.intelsyntax)
- || (intel64 && t->opcode_modifier.amd64)
- || (!intel64 && t->opcode_modifier.intel64))
+ if ((intel_syntax ? t->opcode_modifier.attsyntax
+ : t->opcode_modifier.intelsyntax)
+ || (flag_code == CODE_64BIT
+ && (intel64 ? t->opcode_modifier.amd64
+ : t->opcode_modifier.intel64)))
continue;
/* Check the suffix. */
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1133,6 +1133,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-branch-2"
run_dump_test "x86-64-branch-3"
run_list_test "x86-64-branch-4" "-al -mintel64"
+ run_list_test "x86-64-branch-5" "-al"
run_dump_test "x86-64-gotpcrel"
run_dump_test "x86-64-gotpcrel-no-relax"
--- a/gas/testsuite/gas/i386/x86-64-branch-3.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.d
@@ -16,4 +16,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 48 e8 00 00 00 00 data16 rex\.W callq 1c <bar\+0xf> 18: R_X86_64_PLT32 foo-0x4
[ ]*[a-f0-9]+: 66 c7 f8 00 00 xbeginw 21 <bar\+0x14> 1f: R_X86_64_PC16 foo-0x2
[ ]*[a-f0-9]+: 66 48 c7 f8 00 00 00 00 data16 xbeginq 29 <bar\+0x1c> 25: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 48 ff 18 lcallq \*\(%rax\)
+[ ]*[a-f0-9]+: 48 ff 29 ljmpq \*\(%rcx\)
#pass
--- a/gas/testsuite/gas/i386/x86-64-branch-3.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.s
@@ -10,3 +10,6 @@ bar:
data16 xbegin foo
data16 rex.w xbegin foo
+
+ lcallq *(%rax)
+ ljmpq *(%rcx)
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-5.l
@@ -0,0 +1,19 @@
+.*: Assembler messages:
+.*:2: Error: unsupported syntax for `lcall'
+.*:3: Error: unsupported syntax for `lfs'
+.*:4: Error: unsupported syntax for `lfs'
+.*:5: Error: unsupported syntax for `lgs'
+.*:6: Error: unsupported syntax for `lgs'
+.*:7: Error: unsupported syntax for `ljmp'
+.*:8: Error: unsupported syntax for `lss'
+.*:9: Error: unsupported syntax for `lss'
+.*:12: Error: unsupported syntax for `call'
+.*:13: Error: unsupported syntax for `lfs'
+.*:14: Error: unsupported syntax for `lfs'
+.*:15: Error: unsupported syntax for `lgs'
+.*:16: Error: unsupported syntax for `lgs'
+.*:17: Error: unsupported syntax for `jmp'
+.*:18: Error: unsupported syntax for `lss'
+.*:19: Error: unsupported syntax for `lss'
+GAS LISTING .*
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-5.s
@@ -0,0 +1,19 @@
+ .text
+ lcallq *(%rax)
+ lfs (%rax), %rax
+ lfsq (%rax), %rax
+ lgs (%rax), %rax
+ lgsq (%rax), %rax
+ ljmpq *(%rax)
+ lss (%rax), %rax
+ lssq (%rax), %rax
+
+ .intel_syntax noprefix
+ call TBYTE PTR [rax]
+ lfs rax, [rax]
+ lfs rax, TBYTE PTR [rax]
+ lgs rax, [rax]
+ lgs rax, TBYTE PTR [rax]
+ jmp TBYTE PTR [rax]
+ lss rax, [rax]
+ lss rax, TBYTE PTR [rax]
--- a/gas/testsuite/gas/i386/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/x86-64-intel64.d
@@ -12,6 +12,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b5 11 lgs \(%rcx\),%rdx
[ ]*[a-f0-9]+: 48 0f b2 1a lss \(%rdx\),%rbx
[ ]*[a-f0-9]+: 48 0f b2 1a lss \(%rdx\),%rbx
+[ ]*[a-f0-9]+: 48 ff 18 rex\.W lcall \*\(%rax\)
+[ ]*[a-f0-9]+: 48 ff 29 rex\.W ljmp \*\(%rcx\)
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f 07 sysret
[ ]*[a-f0-9]+: 48 0f 07 sysretq *
@@ -21,6 +23,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f b5 0a lgs \(%rdx\),%rcx
[ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx
[ ]*[a-f0-9]+: 48 0f b2 13 lss \(%rbx\),%rdx
+[ ]*[a-f0-9]+: 48 ff 19 rex\.W lcall \*\(%rcx\)
+[ ]*[a-f0-9]+: 48 ff 2a rex\.W ljmp \*\(%rdx\)
[ ]*[a-f0-9]+: 66 63 c8 movslq %eax,%cx
[ ]*[a-f0-9]+: 66 63 08 movslq \(%rax\),%cx
[ ]*[a-f0-9]+: 66 63 08 movslq \(%rax\),%cx
--- a/gas/testsuite/gas/i386/x86-64-intel64.s
+++ b/gas/testsuite/gas/i386/x86-64-intel64.s
@@ -10,6 +10,9 @@ _start:
lss (%rdx), %rbx
lssq (%rdx), %rbx
+ lcallq *(%rax)
+ ljmpq *(%rcx)
+
syscall
sysretl
sysretq
@@ -22,6 +25,9 @@ _start:
lss rdx, [rbx]
lss rdx, tbyte ptr [rbx]
+ call tbyte ptr [rcx]
+ jmp tbyte ptr [rdx]
+
movsxd cx, ax
movsxd cx, [rax]
movsxd cx, word ptr [rax]
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2336,8 +2336,8 @@ struct dis386 {
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
- '^' => print 'w' or 'l' depending on operand size prefix or
- suffix_always is true (lcall/ljmp).
+ '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
+ prefix or suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
'&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
@@ -13242,6 +13242,12 @@ case_S:
case '^':
if (intel_syntax)
break;
+ if (isa64 == intel64 && (rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ break;
+ }
if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
{
if (sizeflag & DFLAG)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -194,9 +194,12 @@ lea, 2, 0x8d, None, 1, 0, Modrm|Anysize|
// Load segment registers from memory.
lds, 2, 0xc5, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
les, 2, 0xc4, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lfs, 2, 0xfb4, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lgs, 2, 0xfb5, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lss, 2, 0xfb2, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lfs, 2, 0xfb4, None, 2, Cpu386, AMD64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lfs, 2, 0xfb4, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lgs, 2, 0xfb5, None, 2, Cpu386, AMD64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lgs, 2, 0xfb5, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lss, 2, 0xfb2, None, 2, Cpu386, AMD64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lss, 2, 0xfb2, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Flags register instructions.
clc, 0, 0xf8, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@@ -372,12 +375,13 @@ call, 1, 0xe8, None, 1, Cpu64, Intel64|J
call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
call, 1, 0xff, 0x2, 1, Cpu64, AMD64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
call, 1, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
-// Intel Syntax
+// Intel Syntax remaining call instances.
call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
-// Intel Syntax
-call, 1, 0xff, 0x3, 1, 0, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex }
+call, 1, 0xff, 0x3, 1, 0, AMD64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex }
+call, 1, 0xff, 0x3, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Tbyte|BaseIndex }
lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
-lcall, 1, 0xff, 0x3, 1, 0, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+lcall, 1, 0xff, 0x3, 1, 0, AMD64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+lcall, 1, 0xff, 0x3, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
jmp, 1, 0xeb, None, 1, CpuNo64, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
jmp, 1, 0xeb, None, 1, Cpu64, AMD64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32S }
@@ -385,12 +389,13 @@ jmp, 1, 0xeb, None, 1, Cpu64, Intel64|Ju
jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
jmp, 1, 0xff, 0x4, 1, Cpu64, AMD64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
jmp, 1, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
-// Intel Syntax.
+// Intel Syntax remaining jmp instances.
jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
-// Intel Syntax.
-jmp, 1, 0xff, 0x5, 1, 0, Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex }
+jmp, 1, 0xff, 0x5, 1, 0, AMD64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex }
+jmp, 1, 0xff, 0x5, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Tbyte|BaseIndex }
ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
-ljmp, 1, 0xff, 0x5, 1, 0, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+ljmp, 1, 0xff, 0x5, 1, 0, AMD64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
+ljmp, 1, 0xff, 0x5, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { 0 }
ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes
2019-12-27 9:22 ` [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes Jan Beulich
@ 2020-01-03 8:32 ` Jan Beulich
2020-01-09 22:36 ` H.J. Lu
1 sibling, 0 replies; 54+ messages in thread
From: Jan Beulich @ 2020-01-03 8:32 UTC (permalink / raw)
To: binutils; +Cc: H.J. Lu
On 27.12.2019 10:16, Jan Beulich wrote:
> Commit b76bc5d54e ("x86: don't default variable shift count insns to
> 8-bit operand size") pointed out a very bad case, but the underlying
> problem is, as mentioned on various occasions, much larger: Silently
> selecting a (nowhere documented afaict) certain default operand size
> when there's no "sizing" suffix and no suitable register operand(s) is
> simply dangerous (for the programmer to make mistakes).
>
> While in Intel syntax mode such mistakes already lead to an error (which
> is going to remain that way), AT&T syntax mode now gains warnings in
> such cases by default, which can be suppressed or promoted to an error
> if so desired by the programmer. Furthermore at least general purpose
> insns now consistently have a default applied (alongside the warning
> emission), rather than accepting some and refusing others.
>
> No warnings are (as before) to be generated for "DefaultSize" insns as
> well as ones acting on selector and other fixed-width values. For
> SYSRET, however, the DefaultSize needs to be dropped - it had been
> wrongly put there in the first place, as it's unrelated to .code16gcc
> (no stack accesses involved).
>
> As set forth as a prereq when I first mentioned this intended change a
> few years back, Linux as well as gcc have meanwhile been patched to
> avoid (emission of) ambiguous operands (and hence triggering of the new
> warning).
>
> Note that I think that in 64-bit mode IRET and far RET would better get
> a diagnostic too, as it's reasonably likely that a suffix-less instance
> really is meant to be a 64-bit one. But I guess I better make this a
> separate follow-on patch.
>
> Note further that floating point operations with integer operands are an
> exception for now: They continue to use short (16-bit) operands by
> default even in 32- and 64-bit modes.
I've added yet another note here: {,V}PCMPESTR{I,M} would generally also
fall into the "needs suffix for disambiguation" category, but their
64-bit forms aren't really very useful. So I guess keeping the status
quo (by retaining their IgnoreSize attributes) is better than demanding
people to add suffixes there.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes
2019-12-27 9:22 ` [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes Jan Beulich
2020-01-03 8:32 ` Jan Beulich
@ 2020-01-09 22:36 ` H.J. Lu
2020-01-10 8:54 ` Jan Beulich
1 sibling, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-09 22:36 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:22 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> Commit b76bc5d54e ("x86: don't default variable shift count insns to
> 8-bit operand size") pointed out a very bad case, but the underlying
> problem is, as mentioned on various occasions, much larger: Silently
> selecting a (nowhere documented afaict) certain default operand size
> when there's no "sizing" suffix and no suitable register operand(s) is
> simply dangerous (for the programmer to make mistakes).
>
> While in Intel syntax mode such mistakes already lead to an error (which
> is going to remain that way), AT&T syntax mode now gains warnings in
> such cases by default, which can be suppressed or promoted to an error
> if so desired by the programmer. Furthermore at least general purpose
> insns now consistently have a default applied (alongside the warning
> emission), rather than accepting some and refusing others.
>
> No warnings are (as before) to be generated for "DefaultSize" insns as
> well as ones acting on selector and other fixed-width values. For
> SYSRET, however, the DefaultSize needs to be dropped - it had been
> wrongly put there in the first place, as it's unrelated to .code16gcc
> (no stack accesses involved).
>
> As set forth as a prereq when I first mentioned this intended change a
> few years back, Linux as well as gcc have meanwhile been patched to
> avoid (emission of) ambiguous operands (and hence triggering of the new
> warning).
>
> Note that I think that in 64-bit mode IRET and far RET would better get
> a diagnostic too, as it's reasonably likely that a suffix-less instance
> really is meant to be a 64-bit one. But I guess I better make this a
> separate follow-on patch.
>
> Note further that floating point operations with integer operands are an
> exception for now: They continue to use short (16-bit) operands by
> default even in 32- and 64-bit modes.
>
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (process_suffix): Drop SYSRET special case
> and an intel_syntax check. Re-write lack-of-suffix processing
> logic.
> * doc/c-i386.texi: Document operand size defaults for suffix-
> less AT&T syntax insns.
> * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
> testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
> testsuite/gas/i386/x86-64-avx-scalar.s,
> testsuite/gas/i386/x86-64-avx.s,
> testsuite/gas/i386/x86-64-bundle.s,
> testsuite/gas/i386/x86-64-intel64.s,
> testsuite/gas/i386/x86-64-lock-1.s,
> testsuite/gas/i386/x86-64-opcode.s,
> testsuite/gas/i386/x86-64-sse2avx.s,
> testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
> * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
> testsuite/gas/i386/x86-64-nops.s,
> testsuite/gas/i386/x86-64-ptwrite.s,
> testsuite/gas/i386/x86-64-simd.s,
> testsuite/gas/i386/x86-64-sse-noavx.s,
> testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
> insns.
> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
> testsuite/gas/i386/noreg64.s: Add further tests.
> * testsuite/gas/i386/ilp32/x86-64-nops.d,
> testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
> testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
> testsuite/gas/i386/sse-noavx.d,
> testsuite/gas/i386/x86-64-intel64.d,
> testsuite/gas/i386/x86-64-nops.d,
> testsuite/gas/i386/x86-64-opcode.d,
> testsuite/gas/i386/x86-64-ptwrite-intel.d,
> testsuite/gas/i386/x86-64-ptwrite.d,
> testsuite/gas/i386/x86-64-simd-intel.d,
> testsuite/gas/i386/x86-64-simd-suffix.d,
> testsuite/gas/i386/x86-64-simd.d,
> testsuite/gas/i386/x86-64-sse-noavx.d
> testsuite/gas/i386/x86-64-suffix.d,
> testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
> * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
> testsuite/gas/i386/noreg64.l: New.
> * testsuite/gas/i386/i386.exp: Run new tests.
>
> opcodes/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * i386-opc.tbl (sysret): Drop DefaultSize.
> * i386-tbl.h: Re-generate.
> ---
> v3: Don't add any new DefaultSize. Also diagnose SYSRET in 64-bit mode.
> Re-base.
> v2: Re-base over NOP addition to testcases modified here. Add IN/OUT
> tests. Add shift/rotate insn single operand tests. Extend
> "Instruction Naming" doc section to spell out defaults.
Since we don't change encoding, we shouldn't drop any tests. If a warning is
a problem, we need to create new tests to silence the warning.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes
2020-01-09 22:36 ` H.J. Lu
@ 2020-01-10 8:54 ` Jan Beulich
2020-01-10 20:46 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-10 8:54 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 09.01.2020 23:35, H.J. Lu wrote:
> On Fri, Dec 27, 2019 at 1:22 AM Jan Beulich <JBeulich@suse.com> wrote:
>>
>> Commit b76bc5d54e ("x86: don't default variable shift count insns to
>> 8-bit operand size") pointed out a very bad case, but the underlying
>> problem is, as mentioned on various occasions, much larger: Silently
>> selecting a (nowhere documented afaict) certain default operand size
>> when there's no "sizing" suffix and no suitable register operand(s) is
>> simply dangerous (for the programmer to make mistakes).
>>
>> While in Intel syntax mode such mistakes already lead to an error (which
>> is going to remain that way), AT&T syntax mode now gains warnings in
>> such cases by default, which can be suppressed or promoted to an error
>> if so desired by the programmer. Furthermore at least general purpose
>> insns now consistently have a default applied (alongside the warning
>> emission), rather than accepting some and refusing others.
>>
>> No warnings are (as before) to be generated for "DefaultSize" insns as
>> well as ones acting on selector and other fixed-width values. For
>> SYSRET, however, the DefaultSize needs to be dropped - it had been
>> wrongly put there in the first place, as it's unrelated to .code16gcc
>> (no stack accesses involved).
>>
>> As set forth as a prereq when I first mentioned this intended change a
>> few years back, Linux as well as gcc have meanwhile been patched to
>> avoid (emission of) ambiguous operands (and hence triggering of the new
>> warning).
>>
>> Note that I think that in 64-bit mode IRET and far RET would better get
>> a diagnostic too, as it's reasonably likely that a suffix-less instance
>> really is meant to be a 64-bit one. But I guess I better make this a
>> separate follow-on patch.
>>
>> Note further that floating point operations with integer operands are an
>> exception for now: They continue to use short (16-bit) operands by
>> default even in 32- and 64-bit modes.
>>
>> gas/
>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>
>> * config/tc-i386.c (process_suffix): Drop SYSRET special case
>> and an intel_syntax check. Re-write lack-of-suffix processing
>> logic.
>> * doc/c-i386.texi: Document operand size defaults for suffix-
>> less AT&T syntax insns.
>> * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
>> testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
>> testsuite/gas/i386/x86-64-avx-scalar.s,
>> testsuite/gas/i386/x86-64-avx.s,
>> testsuite/gas/i386/x86-64-bundle.s,
>> testsuite/gas/i386/x86-64-intel64.s,
>> testsuite/gas/i386/x86-64-lock-1.s,
>> testsuite/gas/i386/x86-64-opcode.s,
>> testsuite/gas/i386/x86-64-sse2avx.s,
>> testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
>> * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
>> testsuite/gas/i386/x86-64-nops.s,
>> testsuite/gas/i386/x86-64-ptwrite.s,
>> testsuite/gas/i386/x86-64-simd.s,
>> testsuite/gas/i386/x86-64-sse-noavx.s,
>> testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
>> insns.
>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
>> testsuite/gas/i386/noreg64.s: Add further tests.
>> * testsuite/gas/i386/ilp32/x86-64-nops.d,
>> testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
>> testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
>> testsuite/gas/i386/sse-noavx.d,
>> testsuite/gas/i386/x86-64-intel64.d,
>> testsuite/gas/i386/x86-64-nops.d,
>> testsuite/gas/i386/x86-64-opcode.d,
>> testsuite/gas/i386/x86-64-ptwrite-intel.d,
>> testsuite/gas/i386/x86-64-ptwrite.d,
>> testsuite/gas/i386/x86-64-simd-intel.d,
>> testsuite/gas/i386/x86-64-simd-suffix.d,
>> testsuite/gas/i386/x86-64-simd.d,
>> testsuite/gas/i386/x86-64-sse-noavx.d
>> testsuite/gas/i386/x86-64-suffix.d,
>> testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
>> * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
>> testsuite/gas/i386/noreg64.l: New.
>> * testsuite/gas/i386/i386.exp: Run new tests.
>>
>> opcodes/
>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>
>> * i386-opc.tbl (sysret): Drop DefaultSize.
>> * i386-tbl.h: Re-generate.
>> ---
>> v3: Don't add any new DefaultSize. Also diagnose SYSRET in 64-bit mode.
>> Re-base.
>> v2: Re-base over NOP addition to testcases modified here. Add IN/OUT
>> tests. Add shift/rotate insn single operand tests. Extend
>> "Instruction Naming" doc section to spell out defaults.
>
> Since we don't change encoding, we shouldn't drop any tests. If a warning is
> a problem, we need to create new tests to silence the warning.
Could you give a concrete example of a truly dropped test? Some pieces
get moved, but I view this as fulfilling "create new tests to silence
the warning".
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes
2020-01-10 8:54 ` Jan Beulich
@ 2020-01-10 20:46 ` H.J. Lu
2020-01-13 12:57 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-10 20:46 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Jan 10, 2020 at 12:54 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 09.01.2020 23:35, H.J. Lu wrote:
> > On Fri, Dec 27, 2019 at 1:22 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>
> >> Commit b76bc5d54e ("x86: don't default variable shift count insns to
> >> 8-bit operand size") pointed out a very bad case, but the underlying
> >> problem is, as mentioned on various occasions, much larger: Silently
> >> selecting a (nowhere documented afaict) certain default operand size
> >> when there's no "sizing" suffix and no suitable register operand(s) is
> >> simply dangerous (for the programmer to make mistakes).
> >>
> >> While in Intel syntax mode such mistakes already lead to an error (which
> >> is going to remain that way), AT&T syntax mode now gains warnings in
> >> such cases by default, which can be suppressed or promoted to an error
> >> if so desired by the programmer. Furthermore at least general purpose
> >> insns now consistently have a default applied (alongside the warning
> >> emission), rather than accepting some and refusing others.
> >>
> >> No warnings are (as before) to be generated for "DefaultSize" insns as
> >> well as ones acting on selector and other fixed-width values. For
> >> SYSRET, however, the DefaultSize needs to be dropped - it had been
> >> wrongly put there in the first place, as it's unrelated to .code16gcc
> >> (no stack accesses involved).
> >>
> >> As set forth as a prereq when I first mentioned this intended change a
> >> few years back, Linux as well as gcc have meanwhile been patched to
> >> avoid (emission of) ambiguous operands (and hence triggering of the new
> >> warning).
> >>
> >> Note that I think that in 64-bit mode IRET and far RET would better get
> >> a diagnostic too, as it's reasonably likely that a suffix-less instance
> >> really is meant to be a 64-bit one. But I guess I better make this a
> >> separate follow-on patch.
> >>
> >> Note further that floating point operations with integer operands are an
> >> exception for now: They continue to use short (16-bit) operands by
> >> default even in 32- and 64-bit modes.
> >>
> >> gas/
> >> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>
> >> * config/tc-i386.c (process_suffix): Drop SYSRET special case
> >> and an intel_syntax check. Re-write lack-of-suffix processing
> >> logic.
> >> * doc/c-i386.texi: Document operand size defaults for suffix-
> >> less AT&T syntax insns.
> >> * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
> >> testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
> >> testsuite/gas/i386/x86-64-avx-scalar.s,
> >> testsuite/gas/i386/x86-64-avx.s,
> >> testsuite/gas/i386/x86-64-bundle.s,
> >> testsuite/gas/i386/x86-64-intel64.s,
> >> testsuite/gas/i386/x86-64-lock-1.s,
> >> testsuite/gas/i386/x86-64-opcode.s,
> >> testsuite/gas/i386/x86-64-sse2avx.s,
> >> testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
> >> * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
> >> testsuite/gas/i386/x86-64-nops.s,
> >> testsuite/gas/i386/x86-64-ptwrite.s,
> >> testsuite/gas/i386/x86-64-simd.s,
> >> testsuite/gas/i386/x86-64-sse-noavx.s,
> >> testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
> >> insns.
> >> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
> >> testsuite/gas/i386/noreg64.s: Add further tests.
> >> * testsuite/gas/i386/ilp32/x86-64-nops.d,
> >> testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
> >> testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
> >> testsuite/gas/i386/sse-noavx.d,
> >> testsuite/gas/i386/x86-64-intel64.d,
> >> testsuite/gas/i386/x86-64-nops.d,
> >> testsuite/gas/i386/x86-64-opcode.d,
> >> testsuite/gas/i386/x86-64-ptwrite-intel.d,
> >> testsuite/gas/i386/x86-64-ptwrite.d,
> >> testsuite/gas/i386/x86-64-simd-intel.d,
> >> testsuite/gas/i386/x86-64-simd-suffix.d,
> >> testsuite/gas/i386/x86-64-simd.d,
> >> testsuite/gas/i386/x86-64-sse-noavx.d
> >> testsuite/gas/i386/x86-64-suffix.d,
> >> testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
> >> * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
> >> testsuite/gas/i386/noreg64.l: New.
> >> * testsuite/gas/i386/i386.exp: Run new tests.
> >>
> >> opcodes/
> >> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>
> >> * i386-opc.tbl (sysret): Drop DefaultSize.
> >> * i386-tbl.h: Re-generate.
> >> ---
> >> v3: Don't add any new DefaultSize. Also diagnose SYSRET in 64-bit mode.
> >> Re-base.
> >> v2: Re-base over NOP addition to testcases modified here. Add IN/OUT
> >> tests. Add shift/rotate insn single operand tests. Extend
> >> "Instruction Naming" doc section to spell out defaults.
> >
> > Since we don't change encoding, we shouldn't drop any tests. If a warning is
> > a problem, we need to create new tests to silence the warning.
>
> Could you give a concrete example of a truly dropped test? Some pieces
> get moved, but I view this as fulfilling "create new tests to silence
> the warning".
>
The patch is OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes
2020-01-10 20:46 ` H.J. Lu
@ 2020-01-13 12:57 ` Jan Beulich
2020-01-13 14:45 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-13 12:57 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 10.01.2020 21:45, H.J. Lu wrote:
> On Fri, Jan 10, 2020 at 12:54 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 09.01.2020 23:35, H.J. Lu wrote:
>>> On Fri, Dec 27, 2019 at 1:22 AM Jan Beulich <JBeulich@suse.com> wrote:
>>>>
>>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to
>>>> 8-bit operand size") pointed out a very bad case, but the underlying
>>>> problem is, as mentioned on various occasions, much larger: Silently
>>>> selecting a (nowhere documented afaict) certain default operand size
>>>> when there's no "sizing" suffix and no suitable register operand(s) is
>>>> simply dangerous (for the programmer to make mistakes).
>>>>
>>>> While in Intel syntax mode such mistakes already lead to an error (which
>>>> is going to remain that way), AT&T syntax mode now gains warnings in
>>>> such cases by default, which can be suppressed or promoted to an error
>>>> if so desired by the programmer. Furthermore at least general purpose
>>>> insns now consistently have a default applied (alongside the warning
>>>> emission), rather than accepting some and refusing others.
>>>>
>>>> No warnings are (as before) to be generated for "DefaultSize" insns as
>>>> well as ones acting on selector and other fixed-width values. For
>>>> SYSRET, however, the DefaultSize needs to be dropped - it had been
>>>> wrongly put there in the first place, as it's unrelated to .code16gcc
>>>> (no stack accesses involved).
>>>>
>>>> As set forth as a prereq when I first mentioned this intended change a
>>>> few years back, Linux as well as gcc have meanwhile been patched to
>>>> avoid (emission of) ambiguous operands (and hence triggering of the new
>>>> warning).
>>>>
>>>> Note that I think that in 64-bit mode IRET and far RET would better get
>>>> a diagnostic too, as it's reasonably likely that a suffix-less instance
>>>> really is meant to be a 64-bit one. But I guess I better make this a
>>>> separate follow-on patch.
>>>>
>>>> Note further that floating point operations with integer operands are an
>>>> exception for now: They continue to use short (16-bit) operands by
>>>> default even in 32- and 64-bit modes.
>>>>
>>>> gas/
>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>>>
>>>> * config/tc-i386.c (process_suffix): Drop SYSRET special case
>>>> and an intel_syntax check. Re-write lack-of-suffix processing
>>>> logic.
>>>> * doc/c-i386.texi: Document operand size defaults for suffix-
>>>> less AT&T syntax insns.
>>>> * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
>>>> testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
>>>> testsuite/gas/i386/x86-64-avx-scalar.s,
>>>> testsuite/gas/i386/x86-64-avx.s,
>>>> testsuite/gas/i386/x86-64-bundle.s,
>>>> testsuite/gas/i386/x86-64-intel64.s,
>>>> testsuite/gas/i386/x86-64-lock-1.s,
>>>> testsuite/gas/i386/x86-64-opcode.s,
>>>> testsuite/gas/i386/x86-64-sse2avx.s,
>>>> testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
>>>> * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
>>>> testsuite/gas/i386/x86-64-nops.s,
>>>> testsuite/gas/i386/x86-64-ptwrite.s,
>>>> testsuite/gas/i386/x86-64-simd.s,
>>>> testsuite/gas/i386/x86-64-sse-noavx.s,
>>>> testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
>>>> insns.
>>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
>>>> testsuite/gas/i386/noreg64.s: Add further tests.
>>>> * testsuite/gas/i386/ilp32/x86-64-nops.d,
>>>> testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
>>>> testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
>>>> testsuite/gas/i386/sse-noavx.d,
>>>> testsuite/gas/i386/x86-64-intel64.d,
>>>> testsuite/gas/i386/x86-64-nops.d,
>>>> testsuite/gas/i386/x86-64-opcode.d,
>>>> testsuite/gas/i386/x86-64-ptwrite-intel.d,
>>>> testsuite/gas/i386/x86-64-ptwrite.d,
>>>> testsuite/gas/i386/x86-64-simd-intel.d,
>>>> testsuite/gas/i386/x86-64-simd-suffix.d,
>>>> testsuite/gas/i386/x86-64-simd.d,
>>>> testsuite/gas/i386/x86-64-sse-noavx.d
>>>> testsuite/gas/i386/x86-64-suffix.d,
>>>> testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
>>>> * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
>>>> testsuite/gas/i386/noreg64.l: New.
>>>> * testsuite/gas/i386/i386.exp: Run new tests.
>>>>
>>>> opcodes/
>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>>>
>>>> * i386-opc.tbl (sysret): Drop DefaultSize.
>>>> * i386-tbl.h: Re-generate.
>>>> ---
>>>> v3: Don't add any new DefaultSize. Also diagnose SYSRET in 64-bit mode.
>>>> Re-base.
>>>> v2: Re-base over NOP addition to testcases modified here. Add IN/OUT
>>>> tests. Add shift/rotate insn single operand tests. Extend
>>>> "Instruction Naming" doc section to spell out defaults.
>>>
>>> Since we don't change encoding, we shouldn't drop any tests. If a warning is
>>> a problem, we need to create new tests to silence the warning.
>>
>> Could you give a concrete example of a truly dropped test? Some pieces
>> get moved, but I view this as fulfilling "create new tests to silence
>> the warning".
>
> The patch is OK.
Thanks much! Considering the impending branching of 2.34, personally
I'd think it would be better for me to delay committing, such that
this pretty significant change will get some more lingering time
before actually hitting a release. What do you think? (And of course
it would also seem better if some more of this series went in closely
together with this patch.)
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes
2020-01-13 12:57 ` Jan Beulich
@ 2020-01-13 14:45 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 14:45 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Mon, Jan 13, 2020 at 4:57 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 10.01.2020 21:45, H.J. Lu wrote:
> > On Fri, Jan 10, 2020 at 12:54 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 09.01.2020 23:35, H.J. Lu wrote:
> >>> On Fri, Dec 27, 2019 at 1:22 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>>>
> >>>> Commit b76bc5d54e ("x86: don't default variable shift count insns to
> >>>> 8-bit operand size") pointed out a very bad case, but the underlying
> >>>> problem is, as mentioned on various occasions, much larger: Silently
> >>>> selecting a (nowhere documented afaict) certain default operand size
> >>>> when there's no "sizing" suffix and no suitable register operand(s) is
> >>>> simply dangerous (for the programmer to make mistakes).
> >>>>
> >>>> While in Intel syntax mode such mistakes already lead to an error (which
> >>>> is going to remain that way), AT&T syntax mode now gains warnings in
> >>>> such cases by default, which can be suppressed or promoted to an error
> >>>> if so desired by the programmer. Furthermore at least general purpose
> >>>> insns now consistently have a default applied (alongside the warning
> >>>> emission), rather than accepting some and refusing others.
> >>>>
> >>>> No warnings are (as before) to be generated for "DefaultSize" insns as
> >>>> well as ones acting on selector and other fixed-width values. For
> >>>> SYSRET, however, the DefaultSize needs to be dropped - it had been
> >>>> wrongly put there in the first place, as it's unrelated to .code16gcc
> >>>> (no stack accesses involved).
> >>>>
> >>>> As set forth as a prereq when I first mentioned this intended change a
> >>>> few years back, Linux as well as gcc have meanwhile been patched to
> >>>> avoid (emission of) ambiguous operands (and hence triggering of the new
> >>>> warning).
> >>>>
> >>>> Note that I think that in 64-bit mode IRET and far RET would better get
> >>>> a diagnostic too, as it's reasonably likely that a suffix-less instance
> >>>> really is meant to be a 64-bit one. But I guess I better make this a
> >>>> separate follow-on patch.
> >>>>
> >>>> Note further that floating point operations with integer operands are an
> >>>> exception for now: They continue to use short (16-bit) operands by
> >>>> default even in 32- and 64-bit modes.
> >>>>
> >>>> gas/
> >>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>>>
> >>>> * config/tc-i386.c (process_suffix): Drop SYSRET special case
> >>>> and an intel_syntax check. Re-write lack-of-suffix processing
> >>>> logic.
> >>>> * doc/c-i386.texi: Document operand size defaults for suffix-
> >>>> less AT&T syntax insns.
> >>>> * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
> >>>> testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
> >>>> testsuite/gas/i386/x86-64-avx-scalar.s,
> >>>> testsuite/gas/i386/x86-64-avx.s,
> >>>> testsuite/gas/i386/x86-64-bundle.s,
> >>>> testsuite/gas/i386/x86-64-intel64.s,
> >>>> testsuite/gas/i386/x86-64-lock-1.s,
> >>>> testsuite/gas/i386/x86-64-opcode.s,
> >>>> testsuite/gas/i386/x86-64-sse2avx.s,
> >>>> testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
> >>>> * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
> >>>> testsuite/gas/i386/x86-64-nops.s,
> >>>> testsuite/gas/i386/x86-64-ptwrite.s,
> >>>> testsuite/gas/i386/x86-64-simd.s,
> >>>> testsuite/gas/i386/x86-64-sse-noavx.s,
> >>>> testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
> >>>> insns.
> >>>> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
> >>>> testsuite/gas/i386/noreg64.s: Add further tests.
> >>>> * testsuite/gas/i386/ilp32/x86-64-nops.d,
> >>>> testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
> >>>> testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
> >>>> testsuite/gas/i386/sse-noavx.d,
> >>>> testsuite/gas/i386/x86-64-intel64.d,
> >>>> testsuite/gas/i386/x86-64-nops.d,
> >>>> testsuite/gas/i386/x86-64-opcode.d,
> >>>> testsuite/gas/i386/x86-64-ptwrite-intel.d,
> >>>> testsuite/gas/i386/x86-64-ptwrite.d,
> >>>> testsuite/gas/i386/x86-64-simd-intel.d,
> >>>> testsuite/gas/i386/x86-64-simd-suffix.d,
> >>>> testsuite/gas/i386/x86-64-simd.d,
> >>>> testsuite/gas/i386/x86-64-sse-noavx.d
> >>>> testsuite/gas/i386/x86-64-suffix.d,
> >>>> testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
> >>>> * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
> >>>> testsuite/gas/i386/noreg64.l: New.
> >>>> * testsuite/gas/i386/i386.exp: Run new tests.
> >>>>
> >>>> opcodes/
> >>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>>>
> >>>> * i386-opc.tbl (sysret): Drop DefaultSize.
> >>>> * i386-tbl.h: Re-generate.
> >>>> ---
> >>>> v3: Don't add any new DefaultSize. Also diagnose SYSRET in 64-bit mode.
> >>>> Re-base.
> >>>> v2: Re-base over NOP addition to testcases modified here. Add IN/OUT
> >>>> tests. Add shift/rotate insn single operand tests. Extend
> >>>> "Instruction Naming" doc section to spell out defaults.
> >>>
> >>> Since we don't change encoding, we shouldn't drop any tests. If a warning is
> >>> a problem, we need to create new tests to silence the warning.
> >>
> >> Could you give a concrete example of a truly dropped test? Some pieces
> >> get moved, but I view this as fulfilling "create new tests to silence
> >> the warning".
> >
> > The patch is OK.
>
> Thanks much! Considering the impending branching of 2.34, personally
It sounds good. I will review the rest of patch series this week.
> I'd think it would be better for me to delay committing, such that
> this pretty significant change will get some more lingering time
> before actually hitting a release. What do you think? (And of course
> it would also seem better if some more of this series went in closely
> together with this patch.)
>
> Jan
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 02/10] x86: replace adhoc ambiguous operand checking for CRC32
2019-12-27 9:19 ` [PATCH v3 02/10] x86: replace adhoc ambiguous operand checking for CRC32 Jan Beulich
@ 2020-01-13 17:27 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 17:27 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:19 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> There's no need (anymore?) to heavily special case this - just make
> generic logic consider only its first operand, and deal with the case
> of an 'l' suffix not being allowed in a pattern.
>
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (process_suffix): Merge CRC32 handling into
> generic code path. Deal with No_lSuf being set in a template.
> * testsuite/gas/i386/inval-crc32.l,
> testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
> instead of error(s) when operand size is ambiguous.
> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
> testsuite/gas/i386/noreg64.s: Add CRC32 tests.
> * testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
> testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
> Adjust expectations.
>
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2019-12-27 9:24 ` [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests Jan Beulich
@ 2020-01-13 17:33 ` H.J. Lu
2020-01-20 15:31 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 17:33 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> Some encodings are about to gain a warning - move them from test cases
> not expecting any diagnostics to the new, dedicated ones, to allow
> better focus on the actual changes in the subsequent patch.
>
> The new tests added have some wrong expectations right now, which will
> be corrected by the next patch. The test is being added here to make
> more visible which cases actually were wrong (and hence get changed),
> besides demonstrating that in the vast majority of cases the subsequent
> change doesn't alter generated code.
We can't change the encoding nor disallow it. At most, we can issue a
warning. If it is the case, calling it "wrong" isn't accurate.
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s,
> testsuite/gas/i386/ilp32/x86-64.s: Move ambiguous operand size
> tests ...
> * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
> testsuite/gas/i386/noreg64.s: ... here.
> * testsuite/gas/i386/x86_64.s: Likewise. Add further MOVSXD
> cases.
> * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d
> testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d,
> testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
> testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d,
> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/x86_64-intel.d,
> testsuite/gas/i386/x86_64.d: Adjust expectations.
> * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l,
> testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l,
> testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New.
> * testsuite/gas/i386/i386.exp: Run new tests.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling
2019-12-27 9:20 ` [PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich
@ 2020-01-13 17:36 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 17:36 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:20 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> With AVX512VL disabled (e.g. when writing code for the Knights family
> of processors) these insns aren't ambiguous when used with a memory
> source, and hence should be accepted without suffix or operand size
> specifier. When AVX512VL is enabled, to be consistent with this as
> well as other ambiguous operand size handling it seems better to just
> warn about the ambiguity in AT&T mode, and still default to 512-bit
> operands (on the assumption that the code may have been written without
> AVX512VL in mind yet).
>
>
For AT&T syntax, I don't want special treatment for AVX512VL. They
should require suffix even if AVX512VL is disabled.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 07/10] x86: drop further pointless/bogus DefaultSize
2019-12-27 9:20 ` [PATCH v3 07/10] x86: drop further pointless/bogus DefaultSize Jan Beulich
@ 2020-01-13 17:37 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 17:37 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:20 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> - 64-bit CALL permitting just a single operand size doesn't need it.
> - FLDENV et al should never have had it.
>
> It remains suspicious that a number of 64-bit only insns continue to
> have the attribute, despite this being intended for .code16gcc handling
> only.
>
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (process_suffix): Redo and move FLDENV et al
> special case.
>
> opcodes/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
> forms.
> (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
> DefaultSize.
> * i386-tbl.h: Re-generate.
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 08/10] x86-64: also diagnose far returns / IRET with ambiguous operand size
2019-12-27 9:20 ` [PATCH v3 08/10] x86-64: also diagnose far returns / IRET with ambiguous operand size Jan Beulich
@ 2020-01-13 17:38 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 17:38 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:20 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> Other than near returns these default to 32-bit operand size, and hence
> it isn't really unlikely that 64-bit forms are meant. Hence these should
> have disambiguating suffixes. In Intel mode, however, don't error in
> these cases unconditionally - MASM accepts these without suffix _and_
> without warning.
>
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (process_suffix): .
> testsuite/gas/i386/noreg64.s: Add IRET and LRET cases.
> testsuite/gas/i386/x86-64-opcode.s: Add suffix to IRET and LRET.
> Add LRETQ case.
> testsuite/gas/i386/x86-64-suffix.s: Drop IRET case without
> suffix.
> testsuite/gas/i386/x86_64.s: Add RETF cases.
> * testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
> testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l,
> testsuite/gas/i386/x86-64-opcode.d,
> testsuite/gas/i386/x86-64-suffix-intel.d,
> testsuite/gas/i386/x86-64-suffix.d,
> testsuite/gas/i386/x86_64-intel.d
> testsuite/gas/i386/x86_64.d: Adjust expectations.
> * testsuite/gas/i386/x86-64-suffix.e,
> testsuite/gas/i386/x86_64.e: New.
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 09/10] x86-64: honor vendor specifics for near RET
2019-12-27 9:21 ` [PATCH v3 09/10] x86-64: honor vendor specifics for near RET Jan Beulich
@ 2020-01-13 17:40 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 17:40 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:21 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> While vendors agree about default operand size (64 bits) and hence
> unavilability of a 32-bit form, AMD honors a 16-bit operand size
> override (0x66) while Intel doesn't.
>
OK.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2019-12-27 9:27 ` [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich
@ 2020-01-13 17:43 ` H.J. Lu
2020-01-14 15:01 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-13 17:43 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Dec 27, 2019 at 1:27 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> AMD and Intel differ in their handling of far indirect branches as well
> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
> how the latter three were hybrids so far, while far branches were fully
> AMD-like.)
>
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> PR gas/24546
> * config/tc-i386.c (match_template): Apply AMD64/Intel64 check
> to 64-bit code only.
> * config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
> O_tbyte_ptr case.
> * testsuite/gas/i386/x86-64-branch-3.s,
> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
> * testsuite/gas/i386/x86-64-branch-3.d,
> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
> * testsuite/gas/i386/x86-64-branch-5.l,
> testsuite/gas/i386/x86-64-branch-5.s: New.
> * testsuite/gas/i386/i386.exp: Run new test.
>
> opcodes/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> PR gas/24546
> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
> AMD64 and Intel64 templates.
> (call, jmp): Likewise for far indirect variants. Dro
> Unspecified.
> * i386-tbl.h: Re-generate.
>
Please add some documentations to describe how they are used in
AMD64 and Intel64 in AT&T/Intel syntax.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-13 17:43 ` H.J. Lu
@ 2020-01-14 15:01 ` Jan Beulich
2020-01-14 17:06 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-14 15:01 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 13.01.2020 18:42, H.J. Lu wrote:
> On Fri, Dec 27, 2019 at 1:27 AM Jan Beulich <JBeulich@suse.com> wrote:
>>
>> AMD and Intel differ in their handling of far indirect branches as well
>> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
>> how the latter three were hybrids so far, while far branches were fully
>> AMD-like.)
>>
>> gas/
>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>
>> PR gas/24546
>> * config/tc-i386.c (match_template): Apply AMD64/Intel64 check
>> to 64-bit code only.
>> * config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
>> O_tbyte_ptr case.
>> * testsuite/gas/i386/x86-64-branch-3.s,
>> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
>> * testsuite/gas/i386/x86-64-branch-3.d,
>> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
>> * testsuite/gas/i386/x86-64-branch-5.l,
>> testsuite/gas/i386/x86-64-branch-5.s: New.
>> * testsuite/gas/i386/i386.exp: Run new test.
>>
>> opcodes/
>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>
>> PR gas/24546
>> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
>> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
>> AMD64 and Intel64 templates.
>> (call, jmp): Likewise for far indirect variants. Dro
>> Unspecified.
>> * i386-tbl.h: Re-generate.
>
> Please add some documentations to describe how they are used in
> AMD64 and Intel64 in AT&T/Intel syntax.
There's nothing unusual or unexpected here. I wouldn't even know
where this would belong - are there descriptions like what you
ask for somewhere already for a fair set of other insns? I don't
recall any similar additions for any half way recent ISA
extensions, and there it might be better justified to supply
such than it is here. I guess I'm confused by the request ...
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-14 15:01 ` Jan Beulich
@ 2020-01-14 17:06 ` H.J. Lu
2020-01-15 7:49 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-14 17:06 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Tue, Jan 14, 2020 at 7:00 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 13.01.2020 18:42, H.J. Lu wrote:
> > On Fri, Dec 27, 2019 at 1:27 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>
> >> AMD and Intel differ in their handling of far indirect branches as well
> >> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
> >> how the latter three were hybrids so far, while far branches were fully
> >> AMD-like.)
> >>
> >> gas/
> >> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>
> >> PR gas/24546
> >> * config/tc-i386.c (match_template): Apply AMD64/Intel64 check
> >> to 64-bit code only.
> >> * config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
> >> O_tbyte_ptr case.
> >> * testsuite/gas/i386/x86-64-branch-3.s,
> >> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
> >> * testsuite/gas/i386/x86-64-branch-3.d,
> >> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
> >> * testsuite/gas/i386/x86-64-branch-5.l,
> >> testsuite/gas/i386/x86-64-branch-5.s: New.
> >> * testsuite/gas/i386/i386.exp: Run new test.
> >>
> >> opcodes/
> >> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>
> >> PR gas/24546
> >> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
> >> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
> >> AMD64 and Intel64 templates.
> >> (call, jmp): Likewise for far indirect variants. Dro
> >> Unspecified.
> >> * i386-tbl.h: Re-generate.
> >
> > Please add some documentations to describe how they are used in
> > AMD64 and Intel64 in AT&T/Intel syntax.
>
> There's nothing unusual or unexpected here. I wouldn't even know
> where this would belong - are there descriptions like what you
> ask for somewhere already for a fair set of other insns? I don't
> recall any similar additions for any half way recent ISA
> extensions, and there it might be better justified to supply
> such than it is here. I guess I'm confused by the request ...
We should document how new far pointer branches are used
in Intel and AT&T syntax.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-14 17:06 ` H.J. Lu
@ 2020-01-15 7:49 ` Jan Beulich
2020-01-15 13:29 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-15 7:49 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 14.01.2020 18:05, H.J. Lu wrote:
> On Tue, Jan 14, 2020 at 7:00 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 13.01.2020 18:42, H.J. Lu wrote:
>>> On Fri, Dec 27, 2019 at 1:27 AM Jan Beulich <JBeulich@suse.com> wrote:
>>>>
>>>> AMD and Intel differ in their handling of far indirect branches as well
>>>> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
>>>> how the latter three were hybrids so far, while far branches were fully
>>>> AMD-like.)
>>>>
>>>> gas/
>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>>>
>>>> PR gas/24546
>>>> * config/tc-i386.c (match_template): Apply AMD64/Intel64 check
>>>> to 64-bit code only.
>>>> * config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
>>>> O_tbyte_ptr case.
>>>> * testsuite/gas/i386/x86-64-branch-3.s,
>>>> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
>>>> * testsuite/gas/i386/x86-64-branch-3.d,
>>>> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
>>>> * testsuite/gas/i386/x86-64-branch-5.l,
>>>> testsuite/gas/i386/x86-64-branch-5.s: New.
>>>> * testsuite/gas/i386/i386.exp: Run new test.
>>>>
>>>> opcodes/
>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>>>
>>>> PR gas/24546
>>>> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
>>>> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
>>>> AMD64 and Intel64 templates.
>>>> (call, jmp): Likewise for far indirect variants. Dro
>>>> Unspecified.
>>>> * i386-tbl.h: Re-generate.
>>>
>>> Please add some documentations to describe how they are used in
>>> AMD64 and Intel64 in AT&T/Intel syntax.
>>
>> There's nothing unusual or unexpected here. I wouldn't even know
>> where this would belong - are there descriptions like what you
>> ask for somewhere already for a fair set of other insns? I don't
>> recall any similar additions for any half way recent ISA
>> extensions, and there it might be better justified to supply
>> such than it is here. I guess I'm confused by the request ...
>
> We should document how new far pointer branches are used
> in Intel and AT&T syntax.
I have no idea at all what you're after. Could you give me a
pointer to existing text I could use to clone or at least refer
to, which then also would give me a hint where in the docs I
should insert such a piece of information which - as said - I
don't think has a need to be there in the first place? Once
again
- usage is consistent with other insns (none of which have any
such piece of documentation afaict),
- we shouldn't duplicate SDM / PM information.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-15 7:49 ` Jan Beulich
@ 2020-01-15 13:29 ` H.J. Lu
2020-01-15 17:03 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-15 13:29 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Tue, Jan 14, 2020 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 14.01.2020 18:05, H.J. Lu wrote:
> > On Tue, Jan 14, 2020 at 7:00 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 13.01.2020 18:42, H.J. Lu wrote:
> >>> On Fri, Dec 27, 2019 at 1:27 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>>>
> >>>> AMD and Intel differ in their handling of far indirect branches as well
> >>>> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
> >>>> how the latter three were hybrids so far, while far branches were fully
> >>>> AMD-like.)
> >>>>
> >>>> gas/
> >>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>>>
> >>>> PR gas/24546
> >>>> * config/tc-i386.c (match_template): Apply AMD64/Intel64 check
> >>>> to 64-bit code only.
> >>>> * config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
> >>>> O_tbyte_ptr case.
> >>>> * testsuite/gas/i386/x86-64-branch-3.s,
> >>>> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
> >>>> * testsuite/gas/i386/x86-64-branch-3.d,
> >>>> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
> >>>> * testsuite/gas/i386/x86-64-branch-5.l,
> >>>> testsuite/gas/i386/x86-64-branch-5.s: New.
> >>>> * testsuite/gas/i386/i386.exp: Run new test.
> >>>>
> >>>> opcodes/
> >>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>>>
> >>>> PR gas/24546
> >>>> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
> >>>> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
> >>>> AMD64 and Intel64 templates.
> >>>> (call, jmp): Likewise for far indirect variants. Dro
> >>>> Unspecified.
> >>>> * i386-tbl.h: Re-generate.
> >>>
> >>> Please add some documentations to describe how they are used in
> >>> AMD64 and Intel64 in AT&T/Intel syntax.
> >>
> >> There's nothing unusual or unexpected here. I wouldn't even know
> >> where this would belong - are there descriptions like what you
> >> ask for somewhere already for a fair set of other insns? I don't
> >> recall any similar additions for any half way recent ISA
> >> extensions, and there it might be better justified to supply
> >> such than it is here. I guess I'm confused by the request ...
> >
> > We should document how new far pointer branches are used
> > in Intel and AT&T syntax.
>
> I have no idea at all what you're after. Could you give me a
> pointer to existing text I could use to clone or at least refer
> to, which then also would give me a hint where in the docs I
> should insert such a piece of information which - as said - I
> don't think has a need to be there in the first place? Once
> again
> - usage is consistent with other insns (none of which have any
> such piece of documentation afaict),
> - we shouldn't duplicate SDM / PM information.
>
The current assembler supports far pointer branches. Your change
added a new one. You should document how it differs from the
existing one.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-15 13:29 ` H.J. Lu
@ 2020-01-15 17:03 ` Jan Beulich
2020-01-15 21:59 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-15 17:03 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 15.01.2020 14:28, H.J. Lu wrote:
> On Tue, Jan 14, 2020 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 14.01.2020 18:05, H.J. Lu wrote:
>>> On Tue, Jan 14, 2020 at 7:00 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 13.01.2020 18:42, H.J. Lu wrote:
>>>>> On Fri, Dec 27, 2019 at 1:27 AM Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>
>>>>>> AMD and Intel differ in their handling of far indirect branches as well
>>>>>> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
>>>>>> how the latter three were hybrids so far, while far branches were fully
>>>>>> AMD-like.)
>>>>>>
>>>>>> gas/
>>>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>>>>>
>>>>>> PR gas/24546
>>>>>> * config/tc-i386.c (match_template): Apply AMD64/Intel64 check
>>>>>> to 64-bit code only.
>>>>>> * config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
>>>>>> O_tbyte_ptr case.
>>>>>> * testsuite/gas/i386/x86-64-branch-3.s,
>>>>>> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
>>>>>> * testsuite/gas/i386/x86-64-branch-3.d,
>>>>>> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
>>>>>> * testsuite/gas/i386/x86-64-branch-5.l,
>>>>>> testsuite/gas/i386/x86-64-branch-5.s: New.
>>>>>> * testsuite/gas/i386/i386.exp: Run new test.
>>>>>>
>>>>>> opcodes/
>>>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>>>>>>
>>>>>> PR gas/24546
>>>>>> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
>>>>>> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
>>>>>> AMD64 and Intel64 templates.
>>>>>> (call, jmp): Likewise for far indirect variants. Dro
>>>>>> Unspecified.
>>>>>> * i386-tbl.h: Re-generate.
>>>>>
>>>>> Please add some documentations to describe how they are used in
>>>>> AMD64 and Intel64 in AT&T/Intel syntax.
>>>>
>>>> There's nothing unusual or unexpected here. I wouldn't even know
>>>> where this would belong - are there descriptions like what you
>>>> ask for somewhere already for a fair set of other insns? I don't
>>>> recall any similar additions for any half way recent ISA
>>>> extensions, and there it might be better justified to supply
>>>> such than it is here. I guess I'm confused by the request ...
>>>
>>> We should document how new far pointer branches are used
>>> in Intel and AT&T syntax.
>>
>> I have no idea at all what you're after. Could you give me a
>> pointer to existing text I could use to clone or at least refer
>> to, which then also would give me a hint where in the docs I
>> should insert such a piece of information which - as said - I
>> don't think has a need to be there in the first place? Once
>> again
>> - usage is consistent with other insns (none of which have any
>> such piece of documentation afaict),
>> - we shouldn't duplicate SDM / PM information.
>>
>
> The current assembler supports far pointer branches. Your change
> added a new one. You should document how it differs from the
> existing one.
This
@cindex return instructions, i386
@cindex i386 jump, call, return
@cindex return instructions, x86-64
@cindex x86-64 jump, call, return
@item
Immediate form long jumps and calls are
@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
Intel syntax is
@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
instruction
is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
@samp{ret far @var{stack-adjust}}.
and this
@cindex jump instructions, i386
@cindex call instructions, i386
@cindex jump instructions, x86-64
@cindex call instructions, x86-64
Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
convention.
is what I've been able to find. Neither covers - for existing
forms - what you ask for, so I'm still entirely unclear what
form of documentation of what specific aspects you're after.
Sadly you didn't address my prior request to point me at
something that I could go from. I'm afraid if you want me to
do this, you'll need to be more specific. An alternative might
be for you to put together whatever you think needs documenting.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-15 17:03 ` Jan Beulich
@ 2020-01-15 21:59 ` H.J. Lu
2020-01-16 9:16 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-15 21:59 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Wed, Jan 15, 2020 at 9:03 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 15.01.2020 14:28, H.J. Lu wrote:
> > On Tue, Jan 14, 2020 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 14.01.2020 18:05, H.J. Lu wrote:
> >>> On Tue, Jan 14, 2020 at 7:00 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>
> >>>> On 13.01.2020 18:42, H.J. Lu wrote:
> >>>>> On Fri, Dec 27, 2019 at 1:27 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>>>>>
> >>>>>> AMD and Intel differ in their handling of far indirect branches as well
> >>>>>> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
> >>>>>> how the latter three were hybrids so far, while far branches were fully
> >>>>>> AMD-like.)
> >>>>>>
> >>>>>> gas/
> >>>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>>>>>
> >>>>>> PR gas/24546
> >>>>>> * config/tc-i386.c (match_template): Apply AMD64/Intel64 check
> >>>>>> to 64-bit code only.
> >>>>>> * config/tc-i386.c (i386_intel_operand): Also handle CALL/JMP in
> >>>>>> O_tbyte_ptr case.
> >>>>>> * testsuite/gas/i386/x86-64-branch-3.s,
> >>>>>> testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
> >>>>>> * testsuite/gas/i386/x86-64-branch-3.d,
> >>>>>> testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
> >>>>>> * testsuite/gas/i386/x86-64-branch-5.l,
> >>>>>> testsuite/gas/i386/x86-64-branch-5.s: New.
> >>>>>> * testsuite/gas/i386/i386.exp: Run new test.
> >>>>>>
> >>>>>> opcodes/
> >>>>>> 2020-01-XX Jan Beulich <jbeulich@suse.com>
> >>>>>>
> >>>>>> PR gas/24546
> >>>>>> * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
> >>>>>> * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
> >>>>>> AMD64 and Intel64 templates.
> >>>>>> (call, jmp): Likewise for far indirect variants. Dro
> >>>>>> Unspecified.
> >>>>>> * i386-tbl.h: Re-generate.
> >>>>>
> >>>>> Please add some documentations to describe how they are used in
> >>>>> AMD64 and Intel64 in AT&T/Intel syntax.
> >>>>
> >>>> There's nothing unusual or unexpected here. I wouldn't even know
> >>>> where this would belong - are there descriptions like what you
> >>>> ask for somewhere already for a fair set of other insns? I don't
> >>>> recall any similar additions for any half way recent ISA
> >>>> extensions, and there it might be better justified to supply
> >>>> such than it is here. I guess I'm confused by the request ...
> >>>
> >>> We should document how new far pointer branches are used
> >>> in Intel and AT&T syntax.
> >>
> >> I have no idea at all what you're after. Could you give me a
> >> pointer to existing text I could use to clone or at least refer
> >> to, which then also would give me a hint where in the docs I
> >> should insert such a piece of information which - as said - I
> >> don't think has a need to be there in the first place? Once
> >> again
> >> - usage is consistent with other insns (none of which have any
> >> such piece of documentation afaict),
> >> - we shouldn't duplicate SDM / PM information.
> >>
> >
> > The current assembler supports far pointer branches. Your change
> > added a new one. You should document how it differs from the
> > existing one.
>
> This
>
> @cindex return instructions, i386
> @cindex i386 jump, call, return
> @cindex return instructions, x86-64
> @cindex x86-64 jump, call, return
> @item
> Immediate form long jumps and calls are
> @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
> Intel syntax is
> @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
> instruction
> is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
> @samp{ret far @var{stack-adjust}}.
>
> and this
>
> @cindex jump instructions, i386
> @cindex call instructions, i386
> @cindex jump instructions, x86-64
> @cindex call instructions, x86-64
> Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
> AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
> convention.
>
> is what I've been able to find. Neither covers - for existing
> forms - what you ask for, so I'm still entirely unclear what
They do cover existing far branches, lcall and ljmp in AT&T syntax.
Since you are adding new far call and jmp, how should they be used?
> form of documentation of what specific aspects you're after.
> Sadly you didn't address my prior request to point me at
> something that I could go from. I'm afraid if you want me to
> do this, you'll need to be more specific. An alternative might
> be for you to put together whatever you think needs documenting.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-15 21:59 ` H.J. Lu
@ 2020-01-16 9:16 ` Jan Beulich
2020-01-16 14:58 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-16 9:16 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 15.01.2020 22:58, H.J. Lu wrote:
> On Wed, Jan 15, 2020 at 9:03 AM Jan Beulich <jbeulich@suse.com> wrote:
>> On 15.01.2020 14:28, H.J. Lu wrote:
>>> On Tue, Jan 14, 2020 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:
>>>> On 14.01.2020 18:05, H.J. Lu wrote:
>>>>> We should document how new far pointer branches are used
>>>>> in Intel and AT&T syntax.
>>>>
>>>> I have no idea at all what you're after. Could you give me a
>>>> pointer to existing text I could use to clone or at least refer
>>>> to, which then also would give me a hint where in the docs I
>>>> should insert such a piece of information which - as said - I
>>>> don't think has a need to be there in the first place? Once
>>>> again
>>>> - usage is consistent with other insns (none of which have any
>>>> such piece of documentation afaict),
>>>> - we shouldn't duplicate SDM / PM information.
>>>>
>>>
>>> The current assembler supports far pointer branches. Your change
>>> added a new one. You should document how it differs from the
>>> existing one.
>>
>> This
>>
>> @cindex return instructions, i386
>> @cindex i386 jump, call, return
>> @cindex return instructions, x86-64
>> @cindex x86-64 jump, call, return
>> @item
>> Immediate form long jumps and calls are
>> @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
>> Intel syntax is
>> @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
>> instruction
>> is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
>> @samp{ret far @var{stack-adjust}}.
>>
>> and this
>>
>> @cindex jump instructions, i386
>> @cindex call instructions, i386
>> @cindex jump instructions, x86-64
>> @cindex call instructions, x86-64
>> Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
>> AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
>> convention.
>>
>> is what I've been able to find. Neither covers - for existing
>> forms - what you ask for, so I'm still entirely unclear what
>
> They do cover existing far branches, lcall and ljmp in AT&T syntax.
> Since you are adding new far call and jmp, how should they be used?
I'm not adding anything new. The existing text doesn't mention
suffixed versions (e.g. lcalll or ljmpw), so I don't see how
mentioning lcallq and ljmpq would fit, and what it is that would
specifically need saying.
I'm certainly fine with extending existing documentation to
cover new (sub-)cases. I'm not fine with being asked to add
something new without it being clear why, what, how, and
where.
Jan
>> form of documentation of what specific aspects you're after.
>> Sadly you didn't address my prior request to point me at
>> something that I could go from. I'm afraid if you want me to
>> do this, you'll need to be more specific. An alternative might
>> be for you to put together whatever you think needs documenting.
>
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-16 9:16 ` Jan Beulich
@ 2020-01-16 14:58 ` H.J. Lu
2020-01-16 15:14 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-16 14:58 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Thu, Jan 16, 2020 at 1:16 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 15.01.2020 22:58, H.J. Lu wrote:
> > On Wed, Jan 15, 2020 at 9:03 AM Jan Beulich <jbeulich@suse.com> wrote:
> >> On 15.01.2020 14:28, H.J. Lu wrote:
> >>> On Tue, Jan 14, 2020 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>>> On 14.01.2020 18:05, H.J. Lu wrote:
> >>>>> We should document how new far pointer branches are used
> >>>>> in Intel and AT&T syntax.
> >>>>
> >>>> I have no idea at all what you're after. Could you give me a
> >>>> pointer to existing text I could use to clone or at least refer
> >>>> to, which then also would give me a hint where in the docs I
> >>>> should insert such a piece of information which - as said - I
> >>>> don't think has a need to be there in the first place? Once
> >>>> again
> >>>> - usage is consistent with other insns (none of which have any
> >>>> such piece of documentation afaict),
> >>>> - we shouldn't duplicate SDM / PM information.
> >>>>
> >>>
> >>> The current assembler supports far pointer branches. Your change
> >>> added a new one. You should document how it differs from the
> >>> existing one.
> >>
> >> This
> >>
> >> @cindex return instructions, i386
> >> @cindex i386 jump, call, return
> >> @cindex return instructions, x86-64
> >> @cindex x86-64 jump, call, return
> >> @item
> >> Immediate form long jumps and calls are
> >> @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
> >> Intel syntax is
> >> @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
> >> instruction
> >> is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
> >> @samp{ret far @var{stack-adjust}}.
> >>
> >> and this
> >>
> >> @cindex jump instructions, i386
> >> @cindex call instructions, i386
> >> @cindex jump instructions, x86-64
> >> @cindex call instructions, x86-64
> >> Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
> >> AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
> >> convention.
> >>
> >> is what I've been able to find. Neither covers - for existing
> >> forms - what you ask for, so I'm still entirely unclear what
> >
> > They do cover existing far branches, lcall and ljmp in AT&T syntax.
> > Since you are adding new far call and jmp, how should they be used?
>
> I'm not adding anything new. The existing text doesn't mention
> suffixed versions (e.g. lcalll or ljmpw), so I don't see how
> mentioning lcallq and ljmpq would fit, and what it is that would
> specifically need saying.
>
It should say how to use your new far branches.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-16 14:58 ` H.J. Lu
@ 2020-01-16 15:14 ` Jan Beulich
2020-01-16 20:25 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-16 15:14 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 16.01.2020 15:57, H.J. Lu wrote:
> On Thu, Jan 16, 2020 at 1:16 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 15.01.2020 22:58, H.J. Lu wrote:
>>> On Wed, Jan 15, 2020 at 9:03 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>> On 15.01.2020 14:28, H.J. Lu wrote:
>>>>> On Tue, Jan 14, 2020 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:
>>>>>> On 14.01.2020 18:05, H.J. Lu wrote:
>>>>>>> We should document how new far pointer branches are used
>>>>>>> in Intel and AT&T syntax.
>>>>>>
>>>>>> I have no idea at all what you're after. Could you give me a
>>>>>> pointer to existing text I could use to clone or at least refer
>>>>>> to, which then also would give me a hint where in the docs I
>>>>>> should insert such a piece of information which - as said - I
>>>>>> don't think has a need to be there in the first place? Once
>>>>>> again
>>>>>> - usage is consistent with other insns (none of which have any
>>>>>> such piece of documentation afaict),
>>>>>> - we shouldn't duplicate SDM / PM information.
>>>>>>
>>>>>
>>>>> The current assembler supports far pointer branches. Your change
>>>>> added a new one. You should document how it differs from the
>>>>> existing one.
>>>>
>>>> This
>>>>
>>>> @cindex return instructions, i386
>>>> @cindex i386 jump, call, return
>>>> @cindex return instructions, x86-64
>>>> @cindex x86-64 jump, call, return
>>>> @item
>>>> Immediate form long jumps and calls are
>>>> @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
>>>> Intel syntax is
>>>> @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
>>>> instruction
>>>> is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
>>>> @samp{ret far @var{stack-adjust}}.
>>>>
>>>> and this
>>>>
>>>> @cindex jump instructions, i386
>>>> @cindex call instructions, i386
>>>> @cindex jump instructions, x86-64
>>>> @cindex call instructions, x86-64
>>>> Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
>>>> AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
>>>> convention.
>>>>
>>>> is what I've been able to find. Neither covers - for existing
>>>> forms - what you ask for, so I'm still entirely unclear what
>>>
>>> They do cover existing far branches, lcall and ljmp in AT&T syntax.
>>> Since you are adding new far call and jmp, how should they be used?
>>
>> I'm not adding anything new. The existing text doesn't mention
>> suffixed versions (e.g. lcalll or ljmpw), so I don't see how
>> mentioning lcallq and ljmpq would fit, and what it is that would
>> specifically need saying.
>
> It should say how to use your new far branches.
H.J., please. You keep saying this in varying wording, without it
becoming any more clear to me what you're after. Again - can you
point me to some existing piece of documentation where such "how
to use" is already being described, for some earlier addition (or
even some basic insns)? I'm not very good at writing documentation,
and I'm doing even less good with guessing what is wanted. Hence my
request to have at least something to start from.
I've also taken a look at two somewhat similar changes of yours
(07f5af7d3c63 "Handle indirect branches for AMD64 and Intel64" and
5db04b0965e3 "Support AMD64/Intel ISAs in assembler/disassembler"),
which didn't contain any [respective] doc updates.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-16 15:14 ` Jan Beulich
@ 2020-01-16 20:25 ` H.J. Lu
2020-01-17 11:48 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-16 20:25 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Thu, Jan 16, 2020 at 7:14 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 16.01.2020 15:57, H.J. Lu wrote:
> > On Thu, Jan 16, 2020 at 1:16 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 15.01.2020 22:58, H.J. Lu wrote:
> >>> On Wed, Jan 15, 2020 at 9:03 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>> On 15.01.2020 14:28, H.J. Lu wrote:
> >>>>> On Tue, Jan 14, 2020 at 11:49 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>>> On 14.01.2020 18:05, H.J. Lu wrote:
> >>>>>>> We should document how new far pointer branches are used
> >>>>>>> in Intel and AT&T syntax.
> >>>>>>
> >>>>>> I have no idea at all what you're after. Could you give me a
> >>>>>> pointer to existing text I could use to clone or at least refer
> >>>>>> to, which then also would give me a hint where in the docs I
> >>>>>> should insert such a piece of information which - as said - I
> >>>>>> don't think has a need to be there in the first place? Once
> >>>>>> again
> >>>>>> - usage is consistent with other insns (none of which have any
> >>>>>> such piece of documentation afaict),
> >>>>>> - we shouldn't duplicate SDM / PM information.
> >>>>>>
> >>>>>
> >>>>> The current assembler supports far pointer branches. Your change
> >>>>> added a new one. You should document how it differs from the
> >>>>> existing one.
> >>>>
> >>>> This
> >>>>
> >>>> @cindex return instructions, i386
> >>>> @cindex i386 jump, call, return
> >>>> @cindex return instructions, x86-64
> >>>> @cindex x86-64 jump, call, return
> >>>> @item
> >>>> Immediate form long jumps and calls are
> >>>> @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
> >>>> Intel syntax is
> >>>> @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
> >>>> instruction
> >>>> is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
> >>>> @samp{ret far @var{stack-adjust}}.
> >>>>
> >>>> and this
> >>>>
> >>>> @cindex jump instructions, i386
> >>>> @cindex call instructions, i386
> >>>> @cindex jump instructions, x86-64
> >>>> @cindex call instructions, x86-64
> >>>> Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
> >>>> AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
> >>>> convention.
> >>>>
> >>>> is what I've been able to find. Neither covers - for existing
> >>>> forms - what you ask for, so I'm still entirely unclear what
> >>>
> >>> They do cover existing far branches, lcall and ljmp in AT&T syntax.
> >>> Since you are adding new far call and jmp, how should they be used?
> >>
> >> I'm not adding anything new. The existing text doesn't mention
> >> suffixed versions (e.g. lcalll or ljmpw), so I don't see how
> >> mentioning lcallq and ljmpq would fit, and what it is that would
> >> specifically need saying.
> >
> > It should say how to use your new far branches.
>
> H.J., please. You keep saying this in varying wording, without it
> becoming any more clear to me what you're after. Again - can you
> point me to some existing piece of documentation where such "how
> to use" is already being described, for some earlier addition (or
> even some basic insns)? I'm not very good at writing documentation,
> and I'm doing even less good with guessing what is wanted. Hence my
> request to have at least something to start from.
>
> I've also taken a look at two somewhat similar changes of yours
> (07f5af7d3c63 "Handle indirect branches for AMD64 and Intel64" and
> 5db04b0965e3 "Support AMD64/Intel ISAs in assembler/disassembler"),
> which didn't contain any [respective] doc updates.
>
We should improve gas documentation. The current far branches
work fine. Why bother to add new far branches without giving
developer a clue how to use them?
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-16 20:25 ` H.J. Lu
@ 2020-01-17 11:48 ` Jan Beulich
2020-01-17 18:06 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-17 11:48 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 16.01.2020 21:24, H.J. Lu wrote:
> We should improve gas documentation. The current far branches
> work fine. Why bother to add new far branches without giving
> developer a clue how to use them?
That's the subject of CPU documentation, not that of any assembler.
The current far branches "work fine" as far as they're being made
accessible (encodable) by gas. The 64-bit forms Intel CPUs support
didn't work fine at all (because one had to use hand crafted REX.W
prefixes), as per Andrew's bug report. There's no difference here
to the prior work you did to support the Intel64 / AMD64
differences for certain other insns - you've simply made gas
capable of properly encoding them in a vendor dependent manner.
You didn't accompany this with any documentation explaining "how
to use" these. If, retroactively, you think this should have been
accompanied by such documentation, may I ask that you add such,
which will then allow me to see what I could (should as per your
opinion) add for the corrected variants here? Recall - I _still_
don't know what exactly you're after.
This would then further allow me to know whether the remaining
Intl64 / AMD64 differences that gas doesn't properly support yet
will also need to be accompanied by doc updates when I get around
to adjusting them.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-17 11:48 ` Jan Beulich
@ 2020-01-17 18:06 ` H.J. Lu
2020-01-20 10:12 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-17 18:06 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Fri, Jan 17, 2020 at 3:48 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 16.01.2020 21:24, H.J. Lu wrote:
> > We should improve gas documentation. The current far branches
> > work fine. Why bother to add new far branches without giving
> > developer a clue how to use them?
>
> That's the subject of CPU documentation, not that of any assembler.
> The current far branches "work fine" as far as they're being made
> accessible (encodable) by gas. The 64-bit forms Intel CPUs support
> didn't work fine at all (because one had to use hand crafted REX.W
> prefixes), as per Andrew's bug report. There's no difference here
> to the prior work you did to support the Intel64 / AMD64
> differences for certain other insns - you've simply made gas
> capable of properly encoding them in a vendor dependent manner.
> You didn't accompany this with any documentation explaining "how
> to use" these. If, retroactively, you think this should have been
> accompanied by such documentation, may I ask that you add such,
Yes, it is not very obvious how to use them, we should add some
documentation. Which one do you have in mind?
> which will then allow me to see what I could (should as per your
> opinion) add for the corrected variants here? Recall - I _still_
> don't know what exactly you're after.
>
> This would then further allow me to know whether the remaining
> Intl64 / AMD64 differences that gas doesn't properly support yet
> will also need to be accompanied by doc updates when I get around
> to adjusting them.
>
> Jan
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-17 18:06 ` H.J. Lu
@ 2020-01-20 10:12 ` Jan Beulich
2020-01-20 13:43 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-20 10:12 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 17.01.2020 19:06, H.J. Lu wrote:
> On Fri, Jan 17, 2020 at 3:48 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 16.01.2020 21:24, H.J. Lu wrote:
>>> We should improve gas documentation. The current far branches
>>> work fine. Why bother to add new far branches without giving
>>> developer a clue how to use them?
>>
>> That's the subject of CPU documentation, not that of any assembler.
>> The current far branches "work fine" as far as they're being made
>> accessible (encodable) by gas. The 64-bit forms Intel CPUs support
>> didn't work fine at all (because one had to use hand crafted REX.W
>> prefixes), as per Andrew's bug report. There's no difference here
>> to the prior work you did to support the Intel64 / AMD64
>> differences for certain other insns - you've simply made gas
>> capable of properly encoding them in a vendor dependent manner.
>> You didn't accompany this with any documentation explaining "how
>> to use" these. If, retroactively, you think this should have been
>> accompanied by such documentation, may I ask that you add such,
>
> Yes, it is not very obvious how to use them, we should add some
> documentation. Which one do you have in mind?
All which currently have the Intel64 or AMD64 attribute. If all
present ones had extra documentation, then (as said) it would be
more obvious that _and_ what documentation needs/wants adding
for ones covered anew.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-20 10:12 ` Jan Beulich
@ 2020-01-20 13:43 ` H.J. Lu
2020-01-20 14:34 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-20 13:43 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Mon, Jan 20, 2020 at 2:12 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 17.01.2020 19:06, H.J. Lu wrote:
> > On Fri, Jan 17, 2020 at 3:48 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 16.01.2020 21:24, H.J. Lu wrote:
> >>> We should improve gas documentation. The current far branches
> >>> work fine. Why bother to add new far branches without giving
> >>> developer a clue how to use them?
> >>
> >> That's the subject of CPU documentation, not that of any assembler.
> >> The current far branches "work fine" as far as they're being made
> >> accessible (encodable) by gas. The 64-bit forms Intel CPUs support
> >> didn't work fine at all (because one had to use hand crafted REX.W
> >> prefixes), as per Andrew's bug report. There's no difference here
> >> to the prior work you did to support the Intel64 / AMD64
> >> differences for certain other insns - you've simply made gas
> >> capable of properly encoding them in a vendor dependent manner.
> >> You didn't accompany this with any documentation explaining "how
> >> to use" these. If, retroactively, you think this should have been
> >> accompanied by such documentation, may I ask that you add such,
> >
> > Yes, it is not very obvious how to use them, we should add some
> > documentation. Which one do you have in mind?
>
> All which currently have the Intel64 or AMD64 attribute. If all
> present ones had extra documentation, then (as said) it would be
> more obvious that _and_ what documentation needs/wants adding
> for ones covered anew.
Let's start with one first. Please name one.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-20 13:43 ` H.J. Lu
@ 2020-01-20 14:34 ` Jan Beulich
2020-01-22 13:22 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-20 14:34 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 20.01.2020 14:42, H.J. Lu wrote:
> On Mon, Jan 20, 2020 at 2:12 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 17.01.2020 19:06, H.J. Lu wrote:
>>> On Fri, Jan 17, 2020 at 3:48 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 16.01.2020 21:24, H.J. Lu wrote:
>>>>> We should improve gas documentation. The current far branches
>>>>> work fine. Why bother to add new far branches without giving
>>>>> developer a clue how to use them?
>>>>
>>>> That's the subject of CPU documentation, not that of any assembler.
>>>> The current far branches "work fine" as far as they're being made
>>>> accessible (encodable) by gas. The 64-bit forms Intel CPUs support
>>>> didn't work fine at all (because one had to use hand crafted REX.W
>>>> prefixes), as per Andrew's bug report. There's no difference here
>>>> to the prior work you did to support the Intel64 / AMD64
>>>> differences for certain other insns - you've simply made gas
>>>> capable of properly encoding them in a vendor dependent manner.
>>>> You didn't accompany this with any documentation explaining "how
>>>> to use" these. If, retroactively, you think this should have been
>>>> accompanied by such documentation, may I ask that you add such,
>>>
>>> Yes, it is not very obvious how to use them, we should add some
>>> documentation. Which one do you have in mind?
>>
>> All which currently have the Intel64 or AMD64 attribute. If all
>> present ones had extra documentation, then (as said) it would be
>> more obvious that _and_ what documentation needs/wants adding
>> for ones covered anew.
>
> Let's start with one first. Please name one.
CALL r/m (and then naturally also JMP r/m).
(There aren't this many yet, the other ones being CALL disp,
JMP disp, SYSENTER, and SYSEXIT.)
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-13 17:33 ` H.J. Lu
@ 2020-01-20 15:31 ` Jan Beulich
2020-01-20 15:34 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-20 15:31 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 13.01.2020 18:33, H.J. Lu wrote:
> On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
>>
>> Some encodings are about to gain a warning - move them from test cases
>> not expecting any diagnostics to the new, dedicated ones, to allow
>> better focus on the actual changes in the subsequent patch.
>>
>> The new tests added have some wrong expectations right now, which will
>> be corrected by the next patch. The test is being added here to make
>> more visible which cases actually were wrong (and hence get changed),
>> besides demonstrating that in the vast majority of cases the subsequent
>> change doesn't alter generated code.
>
> We can't change the encoding nor disallow it. At most, we can issue a
> warning. If it is the case, calling it "wrong" isn't accurate.
If you look at the following patch you'll find that the two cases
where an encoding actually changes, this will then be accompanied
by a warning. I don't see why disallowing an insn which we've
mistakenly accepted so far wouldn't be permitted. How would we
ever fix any bugs involving e.g. mis-parsing of operands, or
wrongly coded insn templates. By there then being an error, it'll
be quite clear what needs changing on the source side. I'm also
pretty sure that such has happened quite a few times in the past.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-20 15:31 ` Jan Beulich
@ 2020-01-20 15:34 ` H.J. Lu
2020-01-22 11:03 ` Jan Beulich
2020-01-22 16:04 ` Jan Beulich
0 siblings, 2 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-20 15:34 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Mon, Jan 20, 2020 at 7:30 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 13.01.2020 18:33, H.J. Lu wrote:
> > On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>
> >> Some encodings are about to gain a warning - move them from test cases
> >> not expecting any diagnostics to the new, dedicated ones, to allow
> >> better focus on the actual changes in the subsequent patch.
> >>
> >> The new tests added have some wrong expectations right now, which will
> >> be corrected by the next patch. The test is being added here to make
> >> more visible which cases actually were wrong (and hence get changed),
> >> besides demonstrating that in the vast majority of cases the subsequent
> >> change doesn't alter generated code.
> >
> > We can't change the encoding nor disallow it. At most, we can issue a
> > warning. If it is the case, calling it "wrong" isn't accurate.
>
> If you look at the following patch you'll find that the two cases
> where an encoding actually changes, this will then be accompanied
Please open a bug for wrong encoding before we decide what to do
about it. At minimum, we need a record.
> by a warning. I don't see why disallowing an insn which we've
> mistakenly accepted so far wouldn't be permitted. How would we
> ever fix any bugs involving e.g. mis-parsing of operands, or
> wrongly coded insn templates. By there then being an error, it'll
> be quite clear what needs changing on the source side. I'm also
> pretty sure that such has happened quite a few times in the past.
>
> Jan
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-20 15:34 ` H.J. Lu
@ 2020-01-22 11:03 ` Jan Beulich
2020-01-22 12:20 ` H.J. Lu
2020-01-22 16:04 ` Jan Beulich
1 sibling, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-22 11:03 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 20.01.2020 16:33, H.J. Lu wrote:
> On Mon, Jan 20, 2020 at 7:30 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 13.01.2020 18:33, H.J. Lu wrote:
>>> On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
>>>>
>>>> Some encodings are about to gain a warning - move them from test cases
>>>> not expecting any diagnostics to the new, dedicated ones, to allow
>>>> better focus on the actual changes in the subsequent patch.
>>>>
>>>> The new tests added have some wrong expectations right now, which will
>>>> be corrected by the next patch. The test is being added here to make
>>>> more visible which cases actually were wrong (and hence get changed),
>>>> besides demonstrating that in the vast majority of cases the subsequent
>>>> change doesn't alter generated code.
>>>
>>> We can't change the encoding nor disallow it. At most, we can issue a
>>> warning. If it is the case, calling it "wrong" isn't accurate.
>>
>> If you look at the following patch you'll find that the two cases
>> where an encoding actually changes, this will then be accompanied
>
> Please open a bug for wrong encoding before we decide what to do
> about it. At minimum, we need a record.
While I still don't see the point, here you go: PR/25438.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-22 11:03 ` Jan Beulich
@ 2020-01-22 12:20 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-22 12:20 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Wed, Jan 22, 2020 at 3:03 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 20.01.2020 16:33, H.J. Lu wrote:
> > On Mon, Jan 20, 2020 at 7:30 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 13.01.2020 18:33, H.J. Lu wrote:
> >>> On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>>>
> >>>> Some encodings are about to gain a warning - move them from test cases
> >>>> not expecting any diagnostics to the new, dedicated ones, to allow
> >>>> better focus on the actual changes in the subsequent patch.
> >>>>
> >>>> The new tests added have some wrong expectations right now, which will
> >>>> be corrected by the next patch. The test is being added here to make
> >>>> more visible which cases actually were wrong (and hence get changed),
> >>>> besides demonstrating that in the vast majority of cases the subsequent
> >>>> change doesn't alter generated code.
> >>>
> >>> We can't change the encoding nor disallow it. At most, we can issue a
> >>> warning. If it is the case, calling it "wrong" isn't accurate.
> >>
> >> If you look at the following patch you'll find that the two cases
> >> where an encoding actually changes, this will then be accompanied
> >
> > Please open a bug for wrong encoding before we decide what to do
> > about it. At minimum, we need a record.
>
> While I still don't see the point, here you go: PR/25438.
>
> Jan
movzbw %al, %ecx
movzbw %al, %rcx
movzbl %al, %cx
movzbl %al, %rcx
movzbq %al, %cx
movzbq %al, %ecx
should be hard error. Clearly they are typos.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-20 14:34 ` Jan Beulich
@ 2020-01-22 13:22 ` H.J. Lu
2020-01-22 14:24 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-22 13:22 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Mon, Jan 20, 2020 at 6:33 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 20.01.2020 14:42, H.J. Lu wrote:
> > On Mon, Jan 20, 2020 at 2:12 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 17.01.2020 19:06, H.J. Lu wrote:
> >>> On Fri, Jan 17, 2020 at 3:48 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>
> >>>> On 16.01.2020 21:24, H.J. Lu wrote:
> >>>>> We should improve gas documentation. The current far branches
> >>>>> work fine. Why bother to add new far branches without giving
> >>>>> developer a clue how to use them?
> >>>>
> >>>> That's the subject of CPU documentation, not that of any assembler.
> >>>> The current far branches "work fine" as far as they're being made
> >>>> accessible (encodable) by gas. The 64-bit forms Intel CPUs support
> >>>> didn't work fine at all (because one had to use hand crafted REX.W
> >>>> prefixes), as per Andrew's bug report. There's no difference here
> >>>> to the prior work you did to support the Intel64 / AMD64
> >>>> differences for certain other insns - you've simply made gas
> >>>> capable of properly encoding them in a vendor dependent manner.
> >>>> You didn't accompany this with any documentation explaining "how
> >>>> to use" these. If, retroactively, you think this should have been
> >>>> accompanied by such documentation, may I ask that you add such,
> >>>
> >>> Yes, it is not very obvious how to use them, we should add some
> >>> documentation. Which one do you have in mind?
> >>
> >> All which currently have the Intel64 or AMD64 attribute. If all
> >> present ones had extra documentation, then (as said) it would be
> >> more obvious that _and_ what documentation needs/wants adding
> >> for ones covered anew.
> >
> > Let's start with one first. Please name one.
>
> CALL r/m (and then naturally also JMP r/m).
I used
data16 jmp foo
I think assembler should just support the common ISA. If one wants more,
they can use REX prefix. Now you added a new syntax. You should document
it.
> (There aren't this many yet, the other ones being CALL disp,
> JMP disp, SYSENTER, and SYSEXIT.)
>
> Jan
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-22 13:22 ` H.J. Lu
@ 2020-01-22 14:24 ` Jan Beulich
2020-01-22 14:34 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-22 14:24 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 22.01.2020 14:21, H.J. Lu wrote:
> On Mon, Jan 20, 2020 at 6:33 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 20.01.2020 14:42, H.J. Lu wrote:
>>> On Mon, Jan 20, 2020 at 2:12 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 17.01.2020 19:06, H.J. Lu wrote:
>>>>> On Fri, Jan 17, 2020 at 3:48 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>>>
>>>>>> On 16.01.2020 21:24, H.J. Lu wrote:
>>>>>>> We should improve gas documentation. The current far branches
>>>>>>> work fine. Why bother to add new far branches without giving
>>>>>>> developer a clue how to use them?
>>>>>>
>>>>>> That's the subject of CPU documentation, not that of any assembler.
>>>>>> The current far branches "work fine" as far as they're being made
>>>>>> accessible (encodable) by gas. The 64-bit forms Intel CPUs support
>>>>>> didn't work fine at all (because one had to use hand crafted REX.W
>>>>>> prefixes), as per Andrew's bug report. There's no difference here
>>>>>> to the prior work you did to support the Intel64 / AMD64
>>>>>> differences for certain other insns - you've simply made gas
>>>>>> capable of properly encoding them in a vendor dependent manner.
>>>>>> You didn't accompany this with any documentation explaining "how
>>>>>> to use" these. If, retroactively, you think this should have been
>>>>>> accompanied by such documentation, may I ask that you add such,
>>>>>
>>>>> Yes, it is not very obvious how to use them, we should add some
>>>>> documentation. Which one do you have in mind?
>>>>
>>>> All which currently have the Intel64 or AMD64 attribute. If all
>>>> present ones had extra documentation, then (as said) it would be
>>>> more obvious that _and_ what documentation needs/wants adding
>>>> for ones covered anew.
>>>
>>> Let's start with one first. Please name one.
>>
>> CALL r/m (and then naturally also JMP r/m).
>
> I used
>
> data16 jmp foo
>
> I think assembler should just support the common ISA. If one wants more,
> they can use REX prefix. Now you added a new syntax. You should document
> it.
I'm sorry, but we're moving in circles. I've previously indicated
that I'd be fine to add documentation, as long as I know what
precisely you're after, and what part of the documentation it is
that you want to have extended (i.e. preferably where similar
information for other stuff already exists). Adding something new
has not typically been a reason to extend the documentation, when
what has got added was a natural extension of what's been there
before. Or else there would be mention of how to use various
other insns; first an foremost there would be mention of all the
64-bit extensions to pre-existing 32-bit insns back when x86-64
support was added.
Once again, give me a handle on what you want me to do, or be so
kind and supply the pieces yourself (either for me to merge into
the patch, or to commit later on top of it). Please excuse my
ignorance, but I _simply don't see_ what needs documenting here
given the documentation that is available. And I don't see
myself start from scratch something entirely new.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers
2020-01-22 14:24 ` Jan Beulich
@ 2020-01-22 14:34 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-22 14:34 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Wed, Jan 22, 2020 at 6:24 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 22.01.2020 14:21, H.J. Lu wrote:
> > On Mon, Jan 20, 2020 at 6:33 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 20.01.2020 14:42, H.J. Lu wrote:
> >>> On Mon, Jan 20, 2020 at 2:12 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>
> >>>> On 17.01.2020 19:06, H.J. Lu wrote:
> >>>>> On Fri, Jan 17, 2020 at 3:48 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>>>
> >>>>>> On 16.01.2020 21:24, H.J. Lu wrote:
> >>>>>>> We should improve gas documentation. The current far branches
> >>>>>>> work fine. Why bother to add new far branches without giving
> >>>>>>> developer a clue how to use them?
> >>>>>>
> >>>>>> That's the subject of CPU documentation, not that of any assembler.
> >>>>>> The current far branches "work fine" as far as they're being made
> >>>>>> accessible (encodable) by gas. The 64-bit forms Intel CPUs support
> >>>>>> didn't work fine at all (because one had to use hand crafted REX.W
> >>>>>> prefixes), as per Andrew's bug report. There's no difference here
> >>>>>> to the prior work you did to support the Intel64 / AMD64
> >>>>>> differences for certain other insns - you've simply made gas
> >>>>>> capable of properly encoding them in a vendor dependent manner.
> >>>>>> You didn't accompany this with any documentation explaining "how
> >>>>>> to use" these. If, retroactively, you think this should have been
> >>>>>> accompanied by such documentation, may I ask that you add such,
> >>>>>
> >>>>> Yes, it is not very obvious how to use them, we should add some
> >>>>> documentation. Which one do you have in mind?
> >>>>
> >>>> All which currently have the Intel64 or AMD64 attribute. If all
> >>>> present ones had extra documentation, then (as said) it would be
> >>>> more obvious that _and_ what documentation needs/wants adding
> >>>> for ones covered anew.
> >>>
> >>> Let's start with one first. Please name one.
> >>
> >> CALL r/m (and then naturally also JMP r/m).
> >
> > I used
> >
> > data16 jmp foo
> >
> > I think assembler should just support the common ISA. If one wants more,
> > they can use REX prefix. Now you added a new syntax. You should document
> > it.
>
> I'm sorry, but we're moving in circles. I've previously indicated
> that I'd be fine to add documentation, as long as I know what
> precisely you're after, and what part of the documentation it is
> that you want to have extended (i.e. preferably where similar
> information for other stuff already exists). Adding something new
> has not typically been a reason to extend the documentation, when
> what has got added was a natural extension of what's been there
> before. Or else there would be mention of how to use various
> other insns; first an foremost there would be mention of all the
> 64-bit extensions to pre-existing 32-bit insns back when x86-64
> support was added.
>
> Once again, give me a handle on what you want me to do, or be so
> kind and supply the pieces yourself (either for me to merge into
> the patch, or to commit later on top of it). Please excuse my
> ignorance, but I _simply don't see_ what needs documenting here
> given the documentation that is available. And I don't see
> myself start from scratch something entirely new.
>
We should add a new section to document different mnemonics between
Intel64 and AMD64 , something like "lcall *(%rax)" is common and
"lcallq *(%rax)" is for Intel64 with REX_W.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-20 15:34 ` H.J. Lu
2020-01-22 11:03 ` Jan Beulich
@ 2020-01-22 16:04 ` Jan Beulich
2020-01-22 16:09 ` H.J. Lu
1 sibling, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-22 16:04 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 20.01.2020 16:33, H.J. Lu wrote:
> On Mon, Jan 20, 2020 at 7:30 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 13.01.2020 18:33, H.J. Lu wrote:
>>> On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
>>>>
>>>> Some encodings are about to gain a warning - move them from test cases
>>>> not expecting any diagnostics to the new, dedicated ones, to allow
>>>> better focus on the actual changes in the subsequent patch.
>>>>
>>>> The new tests added have some wrong expectations right now, which will
>>>> be corrected by the next patch. The test is being added here to make
>>>> more visible which cases actually were wrong (and hence get changed),
>>>> besides demonstrating that in the vast majority of cases the subsequent
>>>> change doesn't alter generated code.
>>>
>>> We can't change the encoding nor disallow it. At most, we can issue a
>>> warning. If it is the case, calling it "wrong" isn't accurate.
>>
>> If you look at the following patch you'll find that the two cases
>> where an encoding actually changes, this will then be accompanied
>
> Please open a bug for wrong encoding before we decide what to do
> about it. At minimum, we need a record.
Seeing you say "We should make them hard errors now." in that bug,
I hope it is clear that that's an orthogonal job, which - once
done - will convert what gets warned about in the next patch (i.e.
the cases where you're worried about encoding changes) into errors
at the same time. Hence I'd like to ask what the disposition of
this and the next patch is: With your cited remark in the bug, I
don't see what adjustments you want to see done here. IOW it would
seem to me that both patches could go in as they are.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-22 16:04 ` Jan Beulich
@ 2020-01-22 16:09 ` H.J. Lu
2020-01-22 16:28 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-22 16:09 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Wed, Jan 22, 2020 at 8:04 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 20.01.2020 16:33, H.J. Lu wrote:
> > On Mon, Jan 20, 2020 at 7:30 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 13.01.2020 18:33, H.J. Lu wrote:
> >>> On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>>>
> >>>> Some encodings are about to gain a warning - move them from test cases
> >>>> not expecting any diagnostics to the new, dedicated ones, to allow
> >>>> better focus on the actual changes in the subsequent patch.
> >>>>
> >>>> The new tests added have some wrong expectations right now, which will
> >>>> be corrected by the next patch. The test is being added here to make
> >>>> more visible which cases actually were wrong (and hence get changed),
> >>>> besides demonstrating that in the vast majority of cases the subsequent
> >>>> change doesn't alter generated code.
> >>>
> >>> We can't change the encoding nor disallow it. At most, we can issue a
> >>> warning. If it is the case, calling it "wrong" isn't accurate.
> >>
> >> If you look at the following patch you'll find that the two cases
> >> where an encoding actually changes, this will then be accompanied
> >
> > Please open a bug for wrong encoding before we decide what to do
> > about it. At minimum, we need a record.
>
> Seeing you say "We should make them hard errors now." in that bug,
> I hope it is clear that that's an orthogonal job, which - once
> done - will convert what gets warned about in the next patch (i.e.
> the cases where you're worried about encoding changes) into errors
> at the same time. Hence I'd like to ask what the disposition of
> this and the next patch is: With your cited remark in the bug, I
> don't see what adjustments you want to see done here. IOW it would
> seem to me that both patches could go in as they are.
>
All MOVZX with incorrect operands should be hard errors in
16-bit, 32-bit and 64-bit modes.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-22 16:09 ` H.J. Lu
@ 2020-01-22 16:28 ` Jan Beulich
2020-01-22 17:32 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-22 16:28 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 22.01.2020 17:09, H.J. Lu wrote:
> On Wed, Jan 22, 2020 at 8:04 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 20.01.2020 16:33, H.J. Lu wrote:
>>> On Mon, Jan 20, 2020 at 7:30 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 13.01.2020 18:33, H.J. Lu wrote:
>>>>> On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
>>>>>>
>>>>>> Some encodings are about to gain a warning - move them from test cases
>>>>>> not expecting any diagnostics to the new, dedicated ones, to allow
>>>>>> better focus on the actual changes in the subsequent patch.
>>>>>>
>>>>>> The new tests added have some wrong expectations right now, which will
>>>>>> be corrected by the next patch. The test is being added here to make
>>>>>> more visible which cases actually were wrong (and hence get changed),
>>>>>> besides demonstrating that in the vast majority of cases the subsequent
>>>>>> change doesn't alter generated code.
>>>>>
>>>>> We can't change the encoding nor disallow it. At most, we can issue a
>>>>> warning. If it is the case, calling it "wrong" isn't accurate.
>>>>
>>>> If you look at the following patch you'll find that the two cases
>>>> where an encoding actually changes, this will then be accompanied
>>>
>>> Please open a bug for wrong encoding before we decide what to do
>>> about it. At minimum, we need a record.
>>
>> Seeing you say "We should make them hard errors now." in that bug,
>> I hope it is clear that that's an orthogonal job, which - once
>> done - will convert what gets warned about in the next patch (i.e.
>> the cases where you're worried about encoding changes) into errors
>> at the same time. Hence I'd like to ask what the disposition of
>> this and the next patch is: With your cited remark in the bug, I
>> don't see what adjustments you want to see done here. IOW it would
>> seem to me that both patches could go in as they are.
>
> All MOVZX with incorrect operands should be hard errors in
> 16-bit, 32-bit and 64-bit modes.
Only once other insns behave in a similar way. Programmers should
be able to predict assembler behavior, and hence derive what'll
happen for one insn/operands combination from what happens from
any other, sufficiently similar one. This is what the patch helps
with. The consistency in behavior won't be broken down the road
when you or someone else switches the behavior you talk about
from being warnings to being errors. But it can't be the purpose
of this (or any) patch to introduce special cases for certain
insns when none are warranted. In fact we should try to reduce
the number of special cases (which I think I'm slowly making
progress with, see e.g. the change to md_assemble() by patch 4,
which, yes, unavoidably comes with the need to insert less
arbitrary special casing code in process_suffix()).
If you make the change you've outlined, I'll be happy to re-base
the patches here on top, which will merely mean adjustments to
the testsuite additions. If, however, said change will take time,
then may I please get approval to get in the two patches here?
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-22 16:28 ` Jan Beulich
@ 2020-01-22 17:32 ` H.J. Lu
2020-01-23 10:38 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-22 17:32 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
[-- Attachment #1: Type: text/plain, Size: 3297 bytes --]
On Wed, Jan 22, 2020 at 8:28 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 22.01.2020 17:09, H.J. Lu wrote:
> > On Wed, Jan 22, 2020 at 8:04 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 20.01.2020 16:33, H.J. Lu wrote:
> >>> On Mon, Jan 20, 2020 at 7:30 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>
> >>>> On 13.01.2020 18:33, H.J. Lu wrote:
> >>>>> On Fri, Dec 27, 2019 at 1:24 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>>>>>
> >>>>>> Some encodings are about to gain a warning - move them from test cases
> >>>>>> not expecting any diagnostics to the new, dedicated ones, to allow
> >>>>>> better focus on the actual changes in the subsequent patch.
> >>>>>>
> >>>>>> The new tests added have some wrong expectations right now, which will
> >>>>>> be corrected by the next patch. The test is being added here to make
> >>>>>> more visible which cases actually were wrong (and hence get changed),
> >>>>>> besides demonstrating that in the vast majority of cases the subsequent
> >>>>>> change doesn't alter generated code.
> >>>>>
> >>>>> We can't change the encoding nor disallow it. At most, we can issue a
> >>>>> warning. If it is the case, calling it "wrong" isn't accurate.
> >>>>
> >>>> If you look at the following patch you'll find that the two cases
> >>>> where an encoding actually changes, this will then be accompanied
> >>>
> >>> Please open a bug for wrong encoding before we decide what to do
> >>> about it. At minimum, we need a record.
> >>
> >> Seeing you say "We should make them hard errors now." in that bug,
> >> I hope it is clear that that's an orthogonal job, which - once
> >> done - will convert what gets warned about in the next patch (i.e.
> >> the cases where you're worried about encoding changes) into errors
> >> at the same time. Hence I'd like to ask what the disposition of
> >> this and the next patch is: With your cited remark in the bug, I
> >> don't see what adjustments you want to see done here. IOW it would
> >> seem to me that both patches could go in as they are.
> >
> > All MOVZX with incorrect operands should be hard errors in
> > 16-bit, 32-bit and 64-bit modes.
>
> Only once other insns behave in a similar way. Programmers should
> be able to predict assembler behavior, and hence derive what'll
> happen for one insn/operands combination from what happens from
> any other, sufficiently similar one. This is what the patch helps
> with. The consistency in behavior won't be broken down the road
> when you or someone else switches the behavior you talk about
> from being warnings to being errors. But it can't be the purpose
> of this (or any) patch to introduce special cases for certain
> insns when none are warranted. In fact we should try to reduce
> the number of special cases (which I think I'm slowly making
> progress with, see e.g. the change to md_assemble() by patch 4,
> which, yes, unavoidably comes with the need to insert less
> arbitrary special casing code in process_suffix()).
>
> If you make the change you've outlined, I'll be happy to re-base
> the patches here on top, which will merely mean adjustments to
> the testsuite additions. If, however, said change will take time,
> then may I please get approval to get in the two patches here?
>
I am checking in this patch.
--
H.J.
[-- Attachment #2: 0001-x86-Always-disallow-double-word-suffix-with-word-gen.patch --]
[-- Type: text/x-patch, Size: 7154 bytes --]
From be4c5e58bdc839898739e0332aee84abf6e5299a Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Wed, 22 Jan 2020 09:24:14 -0800
Subject: [PATCH] x86: Always disallow double word suffix with word general
register
In 64-bit mode, double word suffix in mnemonic with word general register
is disallowed. Otherwise, assembler gives a warning:
$ cat /tmp/x.s
movl %ax, %bx
movl %ds, %ax
movl %ax, %cs
$ gcc -c /tmp/x.s
/tmp/x.s: Assembler messages:
/tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix
/tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix
/tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix
$ gcc -c /tmp/x.s -m32
/tmp/x.s: Assembler messages:
/tmp/x.s: Assembler messages:
/tmp/x.s:1: Warning: using `%ebx' instead of `%bx' due to `l' suffix
/tmp/x.s:1: Warning: using `%eax' instead of `%ax' due to `l' suffix
/tmp/x.s:2: Warning: using `%eax' instead of `%ax' due to `l' suffix
/tmp/x.s:3: Warning: using `%eax' instead of `%ax' due to `l' suffix
This patch makes it a hard error in all modes. Now we get:
$ gcc -c /tmp/x.s -m32
/tmp/x.s: Assembler messages:
/tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix
/tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix
/tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix
PR gas/25438
* config/tc-i386.c (check_long_reg): Always disallow double word
suffix in mnemonic with word general register.
* testsuite/gas/i386/general.s: Replace word general register
with double word general register for movl.
* testsuite/gas/i386/inval.s: Add tests for movl with word general
register.
* testsuite/gas/i386/general.l: Updated.
* testsuite/gas/i386/inval.l: Likewise.
---
gas/ChangeLog | 12 ++++++++++++
gas/config/tc-i386.c | 24 ++++++------------------
gas/testsuite/gas/i386/general.l | 12 +++---------
gas/testsuite/gas/i386/general.s | 6 +++---
gas/testsuite/gas/i386/inval.l | 7 +++++++
gas/testsuite/gas/i386/inval.s | 4 ++++
6 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2d247a1012..8a18aa7774 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25438
+ * config/tc-i386.c (check_long_reg): Always disallow double word
+ suffix in mnemonic with word general register.
+ * testsuite/gas/i386/general.s: Replace word general register
+ with double word general register for movl.
+ * testsuite/gas/i386/inval.s: Add tests for movl with word general
+ register.
+ * testsuite/gas/i386/general.l: Updated.
+ * testsuite/gas/i386/inval.l: Likewise.
+
2020-01-22 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 3a2a1b7435..34778ae760 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6672,28 +6672,16 @@ check_long_reg (void)
i.suffix);
return 0;
}
- /* Warn if the e prefix on a general reg is missing. */
- else if ((!quiet_warnings || flag_code == CODE_64BIT)
- && i.types[op].bitfield.word
+ /* Error if the e prefix on a general reg is missing. */
+ else if (i.types[op].bitfield.word
&& (i.tm.operand_types[op].bitfield.class == Reg
|| i.tm.operand_types[op].bitfield.instance == Accum)
&& i.tm.operand_types[op].bitfield.dword)
{
- /* Prohibit these changes in the 64bit mode, since the
- lowering is more complicated. */
- if (flag_code == CODE_64BIT)
- {
- as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
- register_prefix, i.op[op].regs->reg_name,
- i.suffix);
- return 0;
- }
-#if REGISTER_WARNINGS
- as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
- register_prefix,
- (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
- register_prefix, i.op[op].regs->reg_name, i.suffix);
-#endif
+ as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
+ register_prefix, i.op[op].regs->reg_name,
+ i.suffix);
+ return 0;
}
/* Warn if the r prefix on a general reg is present. */
else if (i.types[op].bitfield.qword
diff --git a/gas/testsuite/gas/i386/general.l b/gas/testsuite/gas/i386/general.l
index acd44403ee..470527716a 100644
--- a/gas/testsuite/gas/i386/general.l
+++ b/gas/testsuite/gas/i386/general.l
@@ -9,8 +9,6 @@
.*:25: Warning:.*
.*:27: Warning:.*
.*:29: Warning:.*
-.*:39: Warning:.*
-.*:41: Warning:.*
.*:48: Warning:.*
.*:51: Warning:.*
.*:124: Warning:.*
@@ -30,7 +28,6 @@
.*:142: Warning:.*
.*:143: Warning:.*
.*:144: Warning:.*
-.*:178: Warning:.*
.*:224: Warning:.*
.*:233: Warning:.*
.*:234: Warning:.*
@@ -84,11 +81,9 @@
36 007e 1F popl %ds
37 007f 8CD8 mov %ds,%eax
38 0081 8CD8 movl %ds,%eax
- 39 0083 8CD8 movl %ds,%ax
-.*Warning:.*
+ 39 0083 8CDB movl %ds,%ebx
40 0085 8ED8 mov %eax,%ds
- 41 0087 8ED8 movl %ax,%ds
-.*Warning:.*
+ 41 0087 8EDB movl %ebx,%ds
42 0089 8ED8 movl %eax,%ds
43
44 008b 661E pushw %ds
@@ -244,8 +239,7 @@
175 01a9 66F7F1 div %cx,%ax
176 01ac F7F1 div %ecx,%eax
177 01ae 8EDE mov %si,%ds
- 178 01b0 8EDE movl %si,%ds # warning here
-.*Warning:.*
+ 178 01b0 8EDF movl %edi,%ds
179 01b2 1E pushl %ds
180 01b3 1E push %ds
181 01b4 A0000000 00 mov 0,%al
diff --git a/gas/testsuite/gas/i386/general.s b/gas/testsuite/gas/i386/general.s
index 39bbfe3e0b..77f54ae91f 100644
--- a/gas/testsuite/gas/i386/general.s
+++ b/gas/testsuite/gas/i386/general.s
@@ -36,9 +36,9 @@
popl %ds
mov %ds,%eax
movl %ds,%eax
- movl %ds,%ax
+ movl %ds,%ebx
mov %eax,%ds
- movl %ax,%ds
+ movl %ebx,%ds
movl %eax,%ds
pushw %ds
@@ -175,7 +175,7 @@
div %cx,%ax
div %ecx,%eax
mov %si,%ds
- movl %si,%ds # warning here
+ movl %edi,%ds
pushl %ds
push %ds
mov 0,%al
diff --git a/gas/testsuite/gas/i386/inval.l b/gas/testsuite/gas/i386/inval.l
index 3d52a17d2e..0159e97a3f 100644
--- a/gas/testsuite/gas/i386/inval.l
+++ b/gas/testsuite/gas/i386/inval.l
@@ -88,6 +88,9 @@
.*:98: Error: .*rol.*
.*:99: Error: .*rcl.*
.*:102: Error: .*
+.*:104: Error: .*
+.*:105: Error: .*
+.*:106: Error: .*
GAS LISTING .*
@@ -196,3 +199,7 @@ GAS LISTING .*
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\.att_syntax prefix
[ ]*[1-9][0-9]*[ ]+movsd \(%esi\), %ss:\(%edi\), %ss:\(%eax\)
+[ ]*[1-9][0-9]*[ ]+
+[ ]*[1-9][0-9]*[ ]+movl %ds, %ax
+[ ]*[1-9][0-9]*[ ]+movl %ax, %ds
+[ ]*[1-9][0-9]*[ ]+movl %ax, %bx
diff --git a/gas/testsuite/gas/i386/inval.s b/gas/testsuite/gas/i386/inval.s
index 47655e545e..3ff58b34c6 100644
--- a/gas/testsuite/gas/i386/inval.s
+++ b/gas/testsuite/gas/i386/inval.s
@@ -100,3 +100,7 @@ movnti word ptr [eax], ax
.att_syntax prefix
movsd (%esi), %ss:(%edi), %ss:(%eax)
+
+ movl %ds, %ax
+ movl %ax, %ds
+ movl %ax, %bx
--
2.24.1
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-22 17:32 ` H.J. Lu
@ 2020-01-23 10:38 ` Jan Beulich
2020-01-23 12:53 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-23 10:38 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 22.01.2020 18:31, H.J. Lu wrote:
> I am checking in this patch.
Hard to believe that you don't even give people any chance to comment.
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,3 +1,15 @@
> +2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
> +
> + PR gas/25438
> + * config/tc-i386.c (check_long_reg): Always disallow double word
> + suffix in mnemonic with word general register.
What about check_byte_reg() and check_word_reg()? I can only repeat
again - the assembler should behave consistently in regards like
this one.
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-23 10:38 ` Jan Beulich
@ 2020-01-23 12:53 ` H.J. Lu
2020-01-23 13:13 ` Jan Beulich
0 siblings, 1 reply; 54+ messages in thread
From: H.J. Lu @ 2020-01-23 12:53 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Thu, Jan 23, 2020 at 2:38 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 22.01.2020 18:31, H.J. Lu wrote:
> > I am checking in this patch.
>
> Hard to believe that you don't even give people any chance to comment.
>
> > --- a/gas/ChangeLog
> > +++ b/gas/ChangeLog
> > @@ -1,3 +1,15 @@
> > +2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
> > +
> > + PR gas/25438
> > + * config/tc-i386.c (check_long_reg): Always disallow double word
> > + suffix in mnemonic with word general register.
>
> What about check_byte_reg() and check_word_reg()? I can only repeat
> again - the assembler should behave consistently in regards like
> this one.
Please add more examples to PR gas/25438.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-23 12:53 ` H.J. Lu
@ 2020-01-23 13:13 ` Jan Beulich
2020-01-23 13:43 ` H.J. Lu
0 siblings, 1 reply; 54+ messages in thread
From: Jan Beulich @ 2020-01-23 13:13 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
On 23.01.2020 13:52, H.J. Lu wrote:
> On Thu, Jan 23, 2020 at 2:38 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 22.01.2020 18:31, H.J. Lu wrote:
>>> I am checking in this patch.
>>
>> Hard to believe that you don't even give people any chance to comment.
>>
>>> --- a/gas/ChangeLog
>>> +++ b/gas/ChangeLog
>>> @@ -1,3 +1,15 @@
>>> +2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
>>> +
>>> + PR gas/25438
>>> + * config/tc-i386.c (check_long_reg): Always disallow double word
>>> + suffix in mnemonic with word general register.
>>
>> What about check_byte_reg() and check_word_reg()? I can only repeat
>> again - the assembler should behave consistently in regards like
>> this one.
>
> Please add more examples to PR gas/25438.
What? I'm sorry, but I'm starting to get upset, also seeing your
completely ignorant "Please submit a single patch to fix this bug"
you've just added to that bug (but I'll reply there).
Jan
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests
2020-01-23 13:13 ` Jan Beulich
@ 2020-01-23 13:43 ` H.J. Lu
0 siblings, 0 replies; 54+ messages in thread
From: H.J. Lu @ 2020-01-23 13:43 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Thu, Jan 23, 2020 at 5:13 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.01.2020 13:52, H.J. Lu wrote:
> > On Thu, Jan 23, 2020 at 2:38 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 22.01.2020 18:31, H.J. Lu wrote:
> >>> I am checking in this patch.
> >>
> >> Hard to believe that you don't even give people any chance to comment.
> >>
> >>> --- a/gas/ChangeLog
> >>> +++ b/gas/ChangeLog
> >>> @@ -1,3 +1,15 @@
> >>> +2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
> >>> +
> >>> + PR gas/25438
> >>> + * config/tc-i386.c (check_long_reg): Always disallow double word
> >>> + suffix in mnemonic with word general register.
> >>
> >> What about check_byte_reg() and check_word_reg()? I can only repeat
> >> again - the assembler should behave consistently in regards like
> >> this one.
> >
> > Please add more examples to PR gas/25438.
>
> What? I'm sorry, but I'm starting to get upset, also seeing your
Please give examples for issues with check_byte_reg() and check_word_reg()
in PR gas/25438.
> completely ignorant "Please submit a single patch to fix this bug"
> you've just added to that bug (but I'll reply there).
>
I looked at your changes. Your patches move codes around more
than once, which can be done in a patch.
--
H.J.
^ permalink raw reply [flat|nested] 54+ messages in thread
end of thread, other threads:[~2020-01-23 13:43 UTC | newest]
Thread overview: 54+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-27 9:13 [PATCH v3 00/10] x86: operand size handling improvements Jan Beulich
2019-12-27 9:18 ` [PATCH v3 05/10] x86-64: also support MOVSXD with 16-bit destination Jan Beulich
2019-12-27 9:18 ` [PATCH v3 04/10] x86: replace adhoc ambiguous operand checking for MOVSX/MOVZX Jan Beulich
2019-12-27 9:19 ` [PATCH v3 02/10] x86: replace adhoc ambiguous operand checking for CRC32 Jan Beulich
2020-01-13 17:27 ` H.J. Lu
2019-12-27 9:20 ` [PATCH v3 07/10] x86: drop further pointless/bogus DefaultSize Jan Beulich
2020-01-13 17:37 ` H.J. Lu
2019-12-27 9:20 ` [PATCH v3 06/10] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich
2020-01-13 17:36 ` H.J. Lu
2019-12-27 9:20 ` [PATCH v3 08/10] x86-64: also diagnose far returns / IRET with ambiguous operand size Jan Beulich
2020-01-13 17:38 ` H.J. Lu
2019-12-27 9:21 ` [PATCH v3 09/10] x86-64: honor vendor specifics for near RET Jan Beulich
2020-01-13 17:40 ` H.J. Lu
2019-12-27 9:22 ` [PATCH v3 01/10] x86: improve handling of insns with ambiguous operand sizes Jan Beulich
2020-01-03 8:32 ` Jan Beulich
2020-01-09 22:36 ` H.J. Lu
2020-01-10 8:54 ` Jan Beulich
2020-01-10 20:46 ` H.J. Lu
2020-01-13 12:57 ` Jan Beulich
2020-01-13 14:45 ` H.J. Lu
2019-12-27 9:24 ` [PATCH v3 03/10] x86: move certain MOVSX/MOVZX tests Jan Beulich
2020-01-13 17:33 ` H.J. Lu
2020-01-20 15:31 ` Jan Beulich
2020-01-20 15:34 ` H.J. Lu
2020-01-22 11:03 ` Jan Beulich
2020-01-22 12:20 ` H.J. Lu
2020-01-22 16:04 ` Jan Beulich
2020-01-22 16:09 ` H.J. Lu
2020-01-22 16:28 ` Jan Beulich
2020-01-22 17:32 ` H.J. Lu
2020-01-23 10:38 ` Jan Beulich
2020-01-23 12:53 ` H.J. Lu
2020-01-23 13:13 ` Jan Beulich
2020-01-23 13:43 ` H.J. Lu
2019-12-27 9:27 ` [PATCH v3 10/10] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich
2020-01-13 17:43 ` H.J. Lu
2020-01-14 15:01 ` Jan Beulich
2020-01-14 17:06 ` H.J. Lu
2020-01-15 7:49 ` Jan Beulich
2020-01-15 13:29 ` H.J. Lu
2020-01-15 17:03 ` Jan Beulich
2020-01-15 21:59 ` H.J. Lu
2020-01-16 9:16 ` Jan Beulich
2020-01-16 14:58 ` H.J. Lu
2020-01-16 15:14 ` Jan Beulich
2020-01-16 20:25 ` H.J. Lu
2020-01-17 11:48 ` Jan Beulich
2020-01-17 18:06 ` H.J. Lu
2020-01-20 10:12 ` Jan Beulich
2020-01-20 13:43 ` H.J. Lu
2020-01-20 14:34 ` Jan Beulich
2020-01-22 13:22 ` H.J. Lu
2020-01-22 14:24 ` Jan Beulich
2020-01-22 14:34 ` H.J. Lu
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